Memory lifecycle state sensors

Examples of the present disclosure generally relate to memory lifecycle states, and more specifically, to memory lifecycle state sensors.

Memory aging refers to a gradual degradation of physical and electrical properties of a memory after the memory has been written too many times over its lifecycle. As the physical and electrical properties of the memory gradually degrade, more current is needed in order to write to the memory (e.g., in order to overwrite patterns of values previously written to the memory). Continued use of aged memory is undesirable due to its decreasing reliability and the additional current consumption is inefficient.

Memory lifecycle state sensors are described in some embodiments. In one or more embodiments, a memory lifecycle state sensor includes a memory and at least one processor. The at least one processor is configured to write a first value to a cell of the memory at a first voltage. In various embodiments, the cell is storing a second value written to the cell at a second voltage that is greater than the first voltage. In some embodiments, the at least one processor is configured to read a value from the cell and compare the value with the first value. In certain embodiments, an indication of a lifecycle state for the cell is generated based on comparing the value with the first value, the first voltage, and the second voltage.

Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description or as a limitation on the scope of the claims. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated, or if not so explicitly described.

Memory aging is the gradual degradation of physical and electrical properties of memory which occurs after writing to the memory many times over the memory's lifecycle. Compared to memory that is not aged, aged memory requires more current in order to successfully write values to the memory (e.g., in order to overwrite patterns of values previously written to the memory). As a result, aged memory is unreliable and continued use of the aged memory is inefficient.

Examples herein describe memory lifecycle state sensors which include a memory and a processor. In some embodiments, the processor executes instructions which cause the processor to write reference values to a cell of the memory at a first voltage that is greater than a normal operating voltage for writing values to the memory. In one or more examples, the processor reads the reference values from the cell of the memory to ensure that the reference values are successfully written to the memory and stored in the cell.

In certain embodiments, instructions executed by the processor cause the processor to write test values to the cell of the memory at a second voltage that is less than the first voltage. In some examples, the test values are different from the corresponding reference values and the second voltage may be the normal operating voltage for writing values to the memory. In various embodiments, the processor executes instructions that cause the processor to read values from the cell of the memory and compare the values read from the cell of the memory with the test values.

If a value included in the values read from the cell of the memory does not match the corresponding test value, then the second voltage is not sufficient to write the corresponding test value over a value included in the reference values stored in the cell of the memory. The memory is likely aged memory since the first voltage is sufficient to write the value included in the reference values to the cell. In some embodiments, the processor executes instructions which cause the processor to generate an indication of a lifecycle state for the memory as “end of useful life.” The described systems and techniques are capable of identifying/detecting the aged memory whether the aged memory has been written to normal number of times over a relatively long period of time or whether the aged memory has been written to a high number of times over a relatively short period of time.

1 FIG. 100 100 102 104 1 104 2 102 illustrates an example memory lifecycle state sensor, according to some embodiments. The memory lifecycle state sensoris illustrated to include a processor, a memory-, and a memory-. In one or more embodiments, the processoris representative of a variety of types of processors such as central processing units (CPUs), graphics processing units (GPUs), processors implemented using field-programmable gate arrays (FPGAs) (e.g., a soft processors), accelerators, etc.

104 1 104 1 104 1 104 1 106 108 110 112 114 116 118 104 1 104 1 106 108 110 112 114 116 118 In some embodiments, the memory-is a volatile memory. However, in other embodiments, the memory-may be a non-volatile memory. In various embodiments, the memory-is representative of random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), custom RAM (CRAM), etc. The memory-is illustrated to include cells,,,,,,. In some examples, the memory-may be aged such that physical and electrical properties of the memory-have gradually degraded after writing many values to some or all of the cells,,,,,,.

1 FIG. 104 2 120 122 124 126 128 130 132 104 2 104 1 104 1 104 2 104 2 104 1 120 122 104 1 102 102 106 108 110 112 114 116 118 104 1 In the example illustrated in, the memory-includes cells,,,,,,. In some embodiments, the memory-is an additional memory to the memory-(e.g., the memory-is RAM and the memory-is additional RAM). In other embodiments, the memory-is a known non-aged portion of the memory-. In certain embodiments, the cellstores reference values 1, 0, 1, 0, 1, and the cellstores test values 0, 1, 0, 1, 0. In some examples, each of the reference values 1, 0, 1, 0, 1 is different from a corresponding one of the test values 0, 1, 0, 1, 0. In other examples, the test values may be 0, 0, 0, 0, 0. In one or more embodiments, in order to identify/determine a lifecycle state for the memory-(e.g., within useful life, nearing end of useful life, end of useful life, etc.), the processorexecutes instructions that cause the processorto write the reference values 1, 0, 1, 0, 1 to the cell(or another one of the cells,,,,,) at a first voltage. In some examples, the first voltage is greater than a normal operating voltage for writing values to the memory-.

106 102 102 106 106 102 102 106 104 1 After writing the reference values 1, 0, 1, 0, 1 to the cellat the first voltage, the processormay execute instructions which cause the processorto read the reference values 1, 0, 1, 0, 1 from the cell, for example, to confirm that the reference values 1, 0, 1, 0, 1 were successfully written to the cell. In certain embodiments, the processorexecutes instructions which cause the processorto write the test values 0, 1, 0, 1, 0 to the cell(e.g., to overwrite the reference values 1, 0, 1, 0, 1) at a second voltage. In some embodiments, the second voltage is less than the first voltage. In one or more examples, the second voltage can be the normal operating voltage for writing values to the memory-.

106 102 102 106 102 106 104 1 126 104 2 102 102 106 126 101 11 12 126 126 102 128 1 FIG. 1 FIG. In various embodiments, after writing the test values 0, 1, 0, 1, 0 to the cellat the second voltage, the processorexecutes instructions which cause the processorto read values from the cell. In the illustrated example, the processorwrites the values read from the cellof the memory-to the cellof the memory-. In some embodiments, the processorexecutes instructions that cause the processorto compare the test values 0, 1, 0, 1, 0 with the values read from the cell(which are stored in the cell) such as by using a logical XNOR. The logical XNOR outputs a “1” if two inputs are the same and outputs a “0” if the two inputs are not the same. A truth tablefor the logical XNOR is illustrated in. As shown, for a pair of inputs,having values of 0, 0, respectively, the logical XNOR outputs a value of 1. For instance, if the pair of inputs 11, 12 have values of 0, 1, respectively, then the logical XNOR outputs a value of 0. Similarly, if the pair of inputs 11, 12 have values of 1, 0, respectively, then the logical XNOR outputs a value of 0. Finally, if the pair of inputs 11, 12 have values of 1, 1, respectively, then the logical XNOR outputs a value of 1. Accordingly, if one of the test values 0, 1, 0, 1, 0 does match a corresponding value stored in the cell, then the logical XNOR outputs “1.” Conversely, if one of the test values 0, 1, 0, 1, 0 does not match a corresponding value stored in the cell, then the logical XNOR outputs “0.” In the example illustrated in, the processorwrites the outputs from the logical XNOR to the cell.

128 128 128 128 128 128 106 106 128 104 1 104 1 102 134 104 1 102 134 104 1 104 1 134 104 1 104 1 For example, a first value in the cellis 1 based on inputs of 0, 0; a second value in the cellis 1 based on inputs of 1, 1; a third value in the cellis 1 based on inputs of 0, 0; a fourth value in the cellis 0 based on inputs of 1, 0; and a fifth value in the cellis 1 based on inputs of 0, 0. Since the fourth value in the cellis 0, writing the test values 0, 1, 0, 1, 0 to the cellat the second voltage failed to overwrite one of the reference values 1, 0, 1, 0, 1 that were written to the cellat the first voltage. Accordingly, in this example, a higher voltage than the second voltage is needed to reliably write values to the cellwhich indicates that the memory-is aged. In various examples, since the memory-is aged, the processorexecutes instructions that cause the processor to generate an indicationof the lifecycle state for the memory-as “end of useful life.” For example, the processorgenerates the indicationof the lifecycle state for the memory-in response to identifying/determining that the memory-is aged. In one or more examples, the indicationof the lifecycle state for the memory-is generated for display in a user interface, for addition to a memory aging log, for communication to a technician in order to replace the memory-, etc.

106 126 102 106 102 102 102 106 106 106 106 106 102 102 102 106 102 134 104 1 In an alternative example in which the values read from the celland written to the celleach match corresponding ones of the test values 0, 1, 0, 1, 0, the processorexecutes instructions to write the reference values 1, 0, 1, 0, 1 to the cellfor future aging detection. In some embodiments, the processormay be configured to execute instructions that cause the processorto perform the aging detection in iterations in which the processorwrites the reference values 1, 0, 1, 0, 1 to the cellat the first voltage, decreases a value of the second voltage, writes the test values 0, 1, 0, 1, 0 to the cellat the second voltage with the decreased value, reads values from the cell, and compares the values read from the cellwith the test values 0, 1, 0, 1, 0. In these embodiments, if the values read from the celleach match corresponding ones of the test values 0, 1, 0, 1, 0, then the processorexecutes instructions which cause the processorto perform another iteration of the aging detection using a further decreased value of the second voltage. For example, the processorcontinues to decrease the value of the second voltage and perform iterations of aging detection until writing the test values 0, 1, 0, 1, 0 to the cellat a particular value of the second voltage fails to overwrite one or more of the reference values 1, 0, 1, 0, 1. In this example, the processorgenerates the indicationof the lifecycle state for the memory-based on the particular value of the second voltage (e.g., and the first voltage).

100 104 2 104 2 104 1 102 102 106 102 106 118 108 106 108 108 106 Although the memory lifecycle state sensoris illustrated to include the memory-which can be representative of known non-aged memory, in some examples, functionality described with respect to the memory-is included in the memory-. In certain examples, if the processorexecutes instructions which cause the processorto perform aging detection relative to the cell, it may be preferable for the processorto write values read from the cell(for comparison with the test values 0, 1, 0, 1, 0) to the cellrather than the cell. For example, because of the close proximity of the cells,, an amount of gradual degradation of physical and electrical properties of the cellis likely similar to an amount of gradual degradation of physical and electrical properties of the cell.

2 FIG. 200 200 202 104 1 202 204 206 208 102 102 202 210 212 214 202 210 212 214 illustrates a first exampleof memory lifecycle state sensors writing reference values at different voltages, according to some embodiments. The first exampleincludes a memorywhich may be representative of the memory-or a different memory. The memoryis illustrated to include cells,,, and the processorexecutes instructions which cause the processorto write the reference values 1, 0, 1, 0, 1 to the memoryat a high voltage, a medium voltage, and a low voltagein order to identify/determine a lifecycle state for the memory. For example, the high voltageis greater than the medium voltagewhich is greater than the low voltage.

102 204 202 210 102 102 204 204 102 102 204 202 210 202 204 102 204 204 216 102 102 216 102 218 218 204 2 FIG. In one or more embodiments, the processorwrites the reference values 1, 0, 1, 0, 1 to the cellof the memoryat the high voltage. In some examples, the processorexecutes instructions which cause the processorto read the reference values 1, 0, 1, 0, 1 from the cellto confirm that the reference values 1, 0, 1, 0, 1 are stored in the cell. The processorthen executes instructions which cause the processorto write the test values 0, 1, 0, 1, 0 to the cellat a normal operating voltage for writing values to the memory. In certain embodiments, the high voltageis greater than the normal operating voltage for writing values to the memory. In some embodiments, after writing the test values 0, 1, 0, 1, 0 to the cell, the processorreads values from the celland writes the values read from the cellto cellfor comparison with the test values 0, 1, 0, 1, 0. In various examples, the processorexecutes instructions which cause the processorto compare the test values 0, 1, 0, 1, 0 with corresponding values written to the cellusing the logical XNOR. For example, the processorwrites the outputs from the logical XNOR to cell. As shown in, each value in the cellis 1 which indicates that the values read from the cellmatch the corresponding test values 0, 1,0, 1, 0.

102 102 206 202 212 102 206 206 206 102 206 202 212 202 212 202 In certain embodiments, the processorexecutes instructions that cause the processorto write the reference values 1, 0, 1, 0, 1 to the cellof the memoryat the medium voltage. In one or more examples, the processormay read the reference values 1, 0, 1, 0, 1 from the cellto confirm that the reference values 1, 0, 1, 0, 1 are stored in the cell. After writing the reference values 1, 0, 1, 0, 1 to the cell, the processorwrites the test values 0, 1, 0, 1, 0 to the cellat the normal operating voltage for writing values to the memory. In some embodiments, the medium voltageis greater than the normal operating voltage for writing values to the memory. In other embodiments, the medium voltageis less than or equal to the normal operating voltage for writing values to the memory.

206 102 206 206 220 102 220 102 222 218 222 206 In various embodiments, after writing the test values 0, 1, 0, 1, 0 to the cell, the processorexecutes instructions which cause the processor to read values from the cell, and write the values read from the cellto cell. For example, the processorcompares the test values 0, 1, 0, 1, 0 and corresponding values written to the cellas using the logical XNOR, and the processorwrites outputs from the logical XNOR to cell. Like the cell, each value in the cellis 1 which indicates that the values read from the cellmatch the corresponding test values 0, 1, 0, 1, 0.

102 102 208 202 214 102 102 208 208 208 102 208 202 214 202 214 202 In some embodiments, the processorexecutes instructions which cause the processorto write the reference values 1, 0, 1, 0, 1 to the cellof the memoryat the low voltage. For example, the processormay execute instructions which cause the processorto read the reference values 1, 0, 1, 0, 1 from the cellin order to confirm that the reference values 1, 0, 1, 0, 1 are stored in the cell. In one or more examples, after writing the reference values 1, 0, 1, 0, 1 to the cell, the processorwrites the test values 0, 1, 0, 1, 0 to the cellat the normal operating voltage for writing values to the memory. In some embodiments, the low voltageis greater than the normal operating voltage for writing values to the memory. In other embodiments, the low voltageis less than or equal to the normal operating voltage for writing values to the memory.

208 102 102 208 102 208 224 102 102 224 226 218 222 226 208 In certain embodiments, after writing the test values 0, 1, 0, 1, 0 to the cell, the processorexecutes instructions that cause the processorto read values from the cell. For example, the processorwrites the values read from the cellto cellfor comparison with the test values 0, 1, 0, 1, 0 using the logical XNOR. In various examples, the processorexecutes instructions that cause the processorto compare the test values 0, 1, 0, 1, 0 and corresponding values written to the cellusing the logical XNOR, and then write outputs from the logical XNOR to cell. Like the cells,each value in the cellis 1 which indicates that the values read from the cellmatch the corresponding test values 0, 1, 0, 1, 0.

210 212 214 102 202 102 102 134 202 102 204 210 206 212 208 214 Since the test values 0, 1, 0, 1, 0 are successfully written over the reference values 1, 0, 1, 0, 1 when these values were written at each of the high voltage, the medium voltage, and the low voltage, the processorexecutes instructions to identify/determine a lifecycle state for the memoryas “within useful life.” For example, the processorexecutes instructions that cause the processorto generate the indicationof the lifecycle state for the memoryas “within useful life.” In various embodiments, the processorthen writes the reference values 1, 0, 1, 0, 1 to the cellat the high voltage, to the cellat the medium voltage, and to the cellat the low voltagefor future aging detection.

3 FIG. 2 FIG. 300 300 202 102 102 204 210 206 212 208 214 202 102 204 206 208 202 illustrates a second exampleof memory lifecycle state sensors writing reference values at different voltages, according to some embodiments. The second exampleincludes the memory. In some embodiments, the processorexecutes instructions which cause the processorto write the reference values 1, 0, 1, 0, 1 to the cellat the high voltage, write the reference values 1, 0, 1, 0, 1 to the cellat the medium voltage, and write the reference values 1, 0, 1, 0, 1 to the cellthe low voltagein order to identify/determine a lifecycle state for the memoryin a same manner as described with respect to. In various embodiments, the processorwrites the test values 0, 1, 0, 1, 0 to the cells,,at the normal operating voltage for writing values to the memory.

102 204 204 302 102 102 302 102 102 304 304 304 304 304 304 304 204 204 202 3 FIG. In one or more embodiments, the processorreads values from the celland writes the values read from the cellto cell. In some examples, the processorexecutes instructions that cause the processorto compare the test values 0, 1, 0, 1, 0 with corresponding values written to the cellusing the logical XNOR. In these examples, the instructions executed by the processorcause the processorto write outputs from the logical XNOR to cell. As shown in, a first value in the cellis 1 based on inputs of 0, 0; a second value in the cellis 1 based on inputs of 1, 1; a third value in the cellis 0 based on inputs of 0, 1; a fourth value in the cellis 1 based on inputs of 1, 1; and a fifth value in the cellis 1 based on inputs of 0, 0. Because the third value in the cellis 0, writing the test values 0, 1, 0, 1, 0 to the celldid not overwrite all of the reference values 1, 0, 1, 0, 1 stored in the cellwhich indicates that the memoryis aged.

102 102 206 206 306 102 102 306 102 102 308 308 202 In some embodiments, the processorexecutes instructions that cause the processorto read values from the celland write the values read from the cellto cell. For example, the processorexecutes instructions that cause the processorto compare the test values 0, 1, 0, 1, 0 with corresponding values written to the cellusing the logical XNOR. The instructions executed by the processorcause the processorto write outputs from the logical XNOR to cell. In the illustrated example, each of value in the cellis 1 which indicates that the memoryis not aged.

102 102 208 208 310 102 102 310 102 102 312 312 202 3 FIG. In various embodiments, the processorexecutes instructions that cause the processorto read values from the celland write the values read from the cellto cell. In some examples, the processorexecutes instructions that cause the processorto compare the test values 0, 1, 0, 1, 0 with corresponding values written to the cellusing the logical XNOR. For example, the instructions executed by the processorcause the processorto write outputs from the logical XNOR to cell. As shown in, each of value in the cellis 1 which indicates that the memoryis not aged.

202 202 202 210 202 212 214 210 202 102 102 134 202 102 204 210 206 212 208 214 In certain embodiments, writing the test values 0, 1, 0, 1, 0 to the memoryat the normal operating voltage for writing values to the memoryfailed to overwrite one of the reference values 1, 0, 1, 0, 1 when the reference values 1, 0, 1, 0, 1 were written to the memoryat the high voltage, but successfully overwrote each of the reference values 1, 0, 1, 0, 1 when the reference values 1, 0, 1, 0, 1 were written to the memoryat the medium voltageand the low voltage. In an example in which the high voltageis greater than the normal operating voltage for writing values to the memory, the processorexecutes instructions that cause the processorto generate the indicationof the lifecycle state for the memoryas “nearing end of useful life.” In some embodiments, the processorthen writes the reference values 1, 0, 1, 0, 1 to the cellat the high voltage, to the cellat the medium voltage, and to the cellat the low voltagefor future aging detection.

4 FIG. 2 FIG. 400 400 202 102 102 204 210 206 212 208 214 202 102 102 204 206 208 202 illustrates a third exampleof memory lifecycle state sensors writing reference values at different voltages, according to some embodiments. As shown, the third exampleincludes the memory. In one or more embodiments, the processorexecutes instructions which cause the processorto write the reference values 1, 0, 1, 0, 1 to the cellat the high voltage, write the reference values 1, 0, 1, 0, 1 to the cellat the medium voltage, and write the reference values 1, 0, 1, 0, 1 to the cellthe low voltagein order to identify/determine a lifecycle state for the memoryin a same manner as described with respect to. In some embodiments, the processorexecutes instructions that cause the processorto write the test values 0, 1, 0, 1, 0 to the cells,,at the normal operating voltage for writing values to the memory.

102 102 204 204 402 102 102 402 102 102 404 404 404 404 404 404 404 204 204 202 In certain embodiments, the processorexecutes instructions which cause the processorto read values from the celland write the values read from the cellto cell. In some examples, the processorexecutes instructions that cause the processorto compare the test values 0, 1, 0, 1, 0 with corresponding values written to the cellusing the logical XNOR. In these examples, the instructions executed by the processorcause the processorto write outputs from the logical XNOR to cell. In the illustrated example, a first value in the cellis 1 based on inputs of 0, 0; a second value in the cellis 1 based on inputs of 1, 1; a third value in the cellis 1 based on inputs of 0, 0; a fourth value in the cellis 0 based on inputs of 1, 0; and a fifth value in the cellis 1 based on inputs of 0, 0. Since the fourth value in the cellis 0, writing the test values 0, 1, 0, 1, 0 to the celldid not overwrite all of the reference values 1, 0, 1, 0, 1 stored in the cell. In various examples, failing to overwrite each of the reference values 1, 0, 1, 0, 1 indicates that the memoryis aged.

102 102 206 206 406 102 102 406 102 102 408 408 408 408 408 408 408 406 408 202 4 FIG. In some embodiments, the processorexecutes instructions that cause the processorto read values from the celland write the values read from the cellto cell. In one or more embodiments, the processorexecutes instructions that cause the processorto compare the test values 0, 1, 0, 1, 0 with corresponding values written to the cellusing the logical XNOR. For example, the instructions executed by the processorcause the processorto write outputs from the logical XNOR to cell. As shown in, a first value in the cellis 0 based on inputs of 0, 1; a second value in the cellis 1 based on inputs of 1, 1; a third value in the cellis 1 based on inputs of 0, 0; a fourth value in the cellis 1 based on inputs of 1, 1; and a fifth value in the cellis 1 based on inputs of 0, 0. Because the first value in the cellis 0, writing the first test value 0 to the cellfailed to overwrite the first reference value 1 stored in the cellwhich indicates that the memoryis aged.

102 102 208 208 410 102 102 410 102 102 412 412 202 4 FIG. In various embodiments, the processorexecutes instructions that cause the processorto read values from the celland write the values read from the cellto cell. In one or more embodiments, the processorexecutes instructions that cause the processorto compare the test values 0, 1, 0, 1, 0 with corresponding values written to the cellusing the logical XNOR. In some examples, the instructions executed by the processorcause the processorto write outputs from the logical XNOR to cell. As shown in, each of value in the cellis 1 which indicates that the memoryis not aged.

202 214 202 210 212 102 102 134 202 102 204 206 208 134 202 In one or more embodiments, although the test values 0, 1, 0, 1, 0 successfully overwrote each of the reference values 1, 0, 1, 0, 1 written to the memoryat the low voltage, the test values 0, 1, 0, 1, 0 failed to overwrite the reference values 1, 0, 1, 0, 1 written to the memoryat the high voltageand at the medium voltage. In these embodiments, the processorexecutes instructions that cause the processorto generate the indicationof the lifecycle state for the memoryas “end of useful life.” In some embodiments, the processormay not write the reference values 1, 0, 1, 0, 1 to the cells,,for future aging detection based on the indicationof the lifecycle state for the memorybeing “end of useful life.”

5 FIG. 500 502 504 502 502 506 502 104 1 504 502 502 504 illustrates an example distributionof memory lifecycle state sensors in a memory, according to some embodiments. A memoryincludes memory lifecycle state sensor circuitry having multiple memory lifecycle state sensorsarranged throughout the memory. As shown, the memoryis included in an integrated circuit (IC) die(e.g., as a memory IC). For example, the memoryis representative of the memory-or a different memory. In some embodiments, the memory lifecycle state sensorsare included in portions of the memorywhere aging can occur. If/when one of the portions of the memoryages and degrades, then the aging is detected by one of the memory lifecycle state sensors.

6 FIG. 600 602 102 102 106 104 1 210 604 102 102 108 104 1 212 is a flow diagram depicting a methodfor generating an indication of a lifecycle state for a memory, according to some embodiments. At, reference values are written to a first cell of a memory at a first voltage. In various embodiments, the processorexecutes instructions which cause the processorto write the reference values to the cellof the memory-at the high voltage. At, the reference values are written to a second cell of the memory at a second voltage that is less than the first voltage. In some embodiments, the processorexecutes instructions that cause the processorto write the reference values to the cellof the memory-at the medium voltage.

606 102 102 106 108 214 608 102 102 106 108 At, test values are written to the first cell and the second cell at a third voltage that is less than the second voltage. In certain embodiments, the processorexecutes instructions that cause the processorto write the test values to the celland the cellat the low voltage. At, first values are read from the first cell and second values are read from the second cell. In one or more embodiments, instructions executed by the processorcause the processorto read the first values from the celland read the second values from the cell.

610 102 102 612 102 102 134 104 1 At, the first values and the second values are compared with the test values. In some embodiments, the processorexecutes instructions which cause the processorto compare the first values and the second values with the test values. At, an indication is generated of a lifecycle state for the memory based on comparing the first values and the second values with the test values. In various embodiments, instructions executed by the processorcause the processorto generate the indicationof the lifecycle state for the memory-based on comparing the first values and the second values with the test values.

In the preceding, reference is made to embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to specific described embodiments. Instead, any combination of the described features and elements, whether related to different embodiments or not, is contemplated to implement and practice contemplated embodiments. Furthermore, although embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the scope of the present disclosure. Thus, the preceding aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s).

While the foregoing is directed to specific examples, other and further examples may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.