Active matrix (AM) driven display device using a semiconductor light emitting device

This application is the National Stage filing under 35 U.S.C. 371 of International Application No. PCT/KR2020/015678, filed on Nov. 10, 2020, the contents of which are all hereby incorporated by reference herein in its entirety.

The present disclosure relates to a display device using a semiconductor light emitting device. Specifically, the present disclosure may be applied to a technology field for reducing image quality defects caused by leakage of a switch TFT in active matrix (AM) driving.

A light emitting diode (LED) is a well-known semiconductor light emitting device that converts current into light. Starting with commercialization of a red LED using a GaAsP compound semiconductor in 1962, the LED has been used as a light source for displaying an image of an electronic device including an information communication device along with a GaP:N-based green LED. The semiconductor light emitting device has various advantages over a filament-based light emitting device, such as a long life, low power consumption, excellent initial driving characteristics, and high vibration resistance.

The semiconductor light emitting device has recently been miniaturized and is widely applied to a flexible display and a stretchable display. The semiconductor light emitting devices may be classified into a mini LED and a micro LED in size. For convenience, the mini LED may have a size of hundreds of micrometers and the micro LED may have a size of several to several tens of micrometers.

As the semiconductor light emitting device is miniaturized, it is possible to implement a display with a high resolution. Active matrix (AM) driving is more advantageous than passive matrix (PM) driving for the display with the high resolution. In the case of AM driving, there is a problem in that an image quality defect (flicker) phenomenon occurs due to a signal leakage from a switch thin film transistor (TFT). To reduce such problem, there is a method for reducing leakage characteristics of the switch TFT or increasing a capacitance of a capacitor. There is a problem in reducing the leakage characteristics of the switch TFT that a range of improvement is narrow due to characteristics of the device itself. There is a disadvantage that it is difficult to control the increase in the capacitance of the capacitor because of a fixed resolution (a pixel size).

One embodiment of the present disclosure is to provide a display device that is active matrix (AM) driven.

One embodiment of the present disclosure is to reduce image quality defects (flicker) resulted from a signal leakage occurring in a switch TFT in an AM driven display device.

One embodiment of the present disclosure is to easily expand a capacitance of a capacitor at a predetermined resolution (pixel size).

Furthermore, another purpose of one embodiment of the present disclosure is to solve various problems not mentioned herein. A person skilled in the art may understand this via entire contents of the present document and drawings.

One embodiment of the present disclosure to achieve the above purpose provides an active matrix (AM) driven display device using a semiconductor light emitting device including a driving TFT for driving the semiconductor light emitting device, a switch TFT for receiving a scan signal so as to be turned on or off, and transmitting a data signal to a gate terminal of the driving TFT, a first capacitor formed between a first metal pattern connected to the gate terminal of the driving TFT and a second metal pattern connected to a source terminal or a drain terminal of the driving TFT, and a second capacitor formed between an active layer of the driving TFT and the second metal pattern.

In addition, according to one embodiment, the first capacitor may be formed as the first metal pattern and the second metal pattern, extending in an area where the driving TFT is disposed, overlap each other with an insulator interposed therebetween.

In addition, according to one embodiment, the second capacitor may be formed as the active layer and the second metal pattern, extending in an area where the driving TFT is disposed, overlap each other with an insulator interposed therebetween.

In addition, according to one embodiment, the second metal pattern may include an upper second metal pattern disposed on the first metal pattern, and a lower second metal pattern connected to the upper second metal pattern with a via hole and disposed on a layer below a layer of the upper second metal pattern.

In addition, according to one embodiment, the lower second metal pattern may be disposed on the same layer as the first metal pattern.

In addition, according to one embodiment, the first capacitor and the first capacitor may be formed in a first area and a second area not overlapping each other, respectively.

In addition, according to one embodiment, the first capacitor and the second capacitor may be connected in parallel with each other on a driving circuit connected to the semiconductor light emitting device.

In addition, according to one embodiment, the second metal pattern may be connected to a power supply for providing a first fixed voltage and a second fixed voltage to be applied with the first fixed voltage.

In addition, according to one embodiment, the first fixed voltage and the second fixed voltage may be VSS and VDD or the VDD and the VSS, respectively.

In addition, according to one embodiment, the semiconductor light emitting device may be connected to the drain terminal of the driving TFT and applied with the second fixed voltage when the second metal pattern is connected to the source terminal of the driving TFT, and the semiconductor light emitting device may be connected to the source terminal of the driving TFT and applied with the second fixed voltage when the second metal pattern is connected to the drain terminal of the driving TFT.

In addition, according to one embodiment, the semiconductor light emitting device may include a plurality of semiconductor light emitting devices connected in series to each other via a third metal pattern.

In addition, according to one embodiment, the third metal pattern may be disposed so as not to overlap an area where the first capacitor is disposed.

In addition, according to one embodiment, the third metal pattern may be disposed so as not to overlap an area where the second capacitor is disposed.

In addition, according to one embodiment, in the switch TFT, the scan signal may be input to a gate terminal, the data signal may be input to one of a source terminal and a drain terminal, and the other of the source terminal and the drain terminal may be connected to the gate terminal of the driving TFT.

In addition, according to one embodiment, the display may further include an output area in which a plurality of unit light emitting areas are arranged, and each of the unit light emitting areas may include the semiconductor light emitting device, the switch TFT, the driving TFT, the first capacitor, and the second capacitor.

The display device using the semiconductor light emitting device according to the embodiment may be active matrix (AM) driven to output the image or may be locally dimmed by applying a backlight to a liquid crystal panel.

The display device using the semiconductor light emitting device according to the embodiment may be AM driven and may reduce the image quality defects (the flicker) caused by the signal leakage occurring in the switch TFT.

The display device using the semiconductor light emitting device according to the embodiment may easily expand the capacitance of the capacitor at the predetermined resolution (the pixel size).

Furthermore, according to another embodiment of the present disclosure, there are additional technical effects not mentioned herein. A person skilled in the art may understand this via the entire contents of the present document and drawings.

Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts, and redundant description thereof will be omitted. As used herein, the suffixes “module” and “unit” are added or used interchangeably to facilitate preparation of this specification and are not intended to suggest distinct meanings or functions. In describing embodiments disclosed in this specification, relevant well-known technologies may not be described in detail in order not to obscure the subject matter of the embodiments disclosed in this specification. In addition, it should be noted that the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and should not be construed as limiting the technical spirit disclosed in the present specification.

Furthermore, although the drawings are separately described for simplicity, embodiments implemented by combining at least two or more drawings are also within the scope of the present disclosure.

In addition, when an element such as a layer, region or module is described as being “on” another element, it is to be understood that the element may be directly on the other element or there may be an intermediate element between them.

The display device described herein is a concept including all display devices that display information with a unit pixel or a set of unit pixels. Therefore, the display device may be applied not only to finished products but also to parts. For example, a panel corresponding to a part of a digital TV also independently corresponds to the display device in the present specification. The finished products include a mobile phone, a smartphone, a laptop, a digital broadcasting terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation system, a slate PC, a tablet, an Ultrabook, a digital TV, a desktop computer, and the like.

However, it will be readily apparent to those skilled in the art that the configuration according to the embodiments described herein is applicable even to a new product that will be developed later as a display device.

In addition, the semiconductor light emitting device mentioned in this specification is a concept including an LED, a micro LED, and the like.

1 FIG. is a conceptual view illustrating an embodiment of a display device using a semiconductor light emitting device according to the present disclosure.

1 FIG. 100 As shown in, information processed by a controller (not shown) of a display devicemay be displayed using a flexible display.

The flexible display may include, for example, a display that can be warped, bent, twisted, folded, or rolled by external force.

Furthermore, the flexible display may be, for example, a display manufactured on a thin and flexible substrate that can be warped, bent, folded, or rolled like paper while maintaining the display characteristics of a conventional flat panel display.

1 FIG. When the flexible display remains in an unbent state (e.g., a state having an infinite radius of curvature) (hereinafter referred to as a first state), the display area of the flexible display forms a flat surface. When the display in the first state is changed to a bent state (e.g., a state having a finite radius of curvature) (hereinafter referred to as a second state) by external force, the display area may be a curved surface. As shown in, the information displayed in the second state may be visual information output on a curved surface. Such visual information may be implemented by independently controlling the light emission of sub-pixels arranged in a matrix form. The unit pixel may mean, for example, a minimum unit for implementing one color.

The unit pixel of the flexible display may be implemented by a semiconductor light emitting device. In the present disclosure, a light emitting diode (LED) is exemplified as a type of the semiconductor light emitting device configured to convert electric current into light. The LED may be formed in a small size, and may thus serve as a unit pixel even in the second state.

Hereinafter, a flexible display implemented using the LED will be described in more detail with reference to the drawings.

2 FIG. 1 FIG. is a partially enlarged view showing part A of.

3 3 FIGS.A andB 2 FIG. are cross-sectional views taken along lines B-B and C-C in.

4 FIG. 3 FIG. is a conceptual view illustrating the flip-chip type semiconductor light emitting device of.

5 5 FIGS.A toC are conceptual views illustrating various examples of implementation of colors in relation to a flip-chip type semiconductor light emitting device.

2 3 3 FIGS.,A andB 100 100 As shown in, the display deviceusing a passive matrix (PM) type semiconductor light emitting device is exemplified as the display deviceusing a semiconductor light emitting device. However, the examples described below are also applicable to an active matrix (AM) type semiconductor light emitting device.

100 110 120 130 140 150 1 FIG. 2 FIG. The display deviceshown inmay include a substrate, a first electrode, a conductive adhesive layer, a second electrode, and at least one semiconductor light emitting device, as shown in.

110 110 110 The substratemay be a flexible substrate. For example, to implement a flexible display device, the substratemay include glass or polyimide (PI). Any insulative and flexible material such as polyethylene naphthalate (PEN) or polyethylene terephthalate (PET) may be employed. In addition, the substratemay be formed of either a transparent material or an opaque material.

110 120 120 110 The substratemay be a wiring substrate on which the first electrodeis disposed. Thus, the first electrodemay be positioned on the substrate.

3 FIG.A 160 110 120 170 160 160 110 160 110 As shown in, an insulating layermay be disposed on the substrateon which the first electrodeis positioned, and an auxiliary electrodemay be positioned on the insulating layer. In this case, a stack in which the insulating layeris laminated on the substratemay be a single wiring substrate. More specifically, the insulating layermay be formed of an insulative and flexible material such as PI, PET, or PEN, and may be integrated with the substrateto form a single substrate.

170 120 150 160 120 170 120 171 160 171 The auxiliary electrode, which is an electrode that electrically connects the first electrodeand the semiconductor light emitting device, is positioned on the insulating layer, and is disposed to correspond to the position of the first electrode. For example, the auxiliary electrodemay have a dot shape and may be electrically connected to the first electrodeby an electrode holeformed through the insulating layer. The electrode holemay be formed by filling a via hole with a conductive material.

2 3 FIG.orA 130 160 160 130 130 110 160 130 110 130 As shown in, a conductive adhesive layermay be formed on one surface of the insulating layer, but embodiments of the present disclosure are not limited thereto. For example, a layer performing a specific function may be formed between the insulating layerand the conductive adhesive layer, or the conductive adhesive layermay be disposed on the substratewithout the insulating layer. In a structure in which the conductive adhesive layeris disposed on the substrate, the conductive adhesive layermay serve as an insulating layer.

130 130 130 The conductive adhesive layermay be a layer having adhesiveness and conductivity. For this purpose, a material having conductivity and a material having adhesiveness may be mixed in the conductive adhesive layer. In addition, the conductive adhesive layermay have ductility, thereby providing making the display device flexible.

130 130 130 As an example, the conductive adhesive layermay be an anisotropic conductive film (ACF), an anisotropic conductive paste, a solution containing conductive particles, or the like. The conductive adhesive layermay be configured as a layer that allows electrical interconnection in the direction of the Z-axis extending through the thickness, but is electrically insulative in the horizontal X-Y direction. Accordingly, the conductive adhesive layermay be referred to as a Z-axis conductive layer (hereinafter, referred to simply as a “conductive adhesive layer”).

The ACF is a film in which an anisotropic conductive medium is mixed with an insulating base member. When the ACF is subjected to heat and pressure, only a specific portion thereof becomes conductive by the anisotropic conductive medium. Hereinafter, it will be described that heat and pressure are applied to the ACF. However, another method may be used to make the ACF partially conductive. The other method may be, for example, application of only one of the heat and pressure or UV curing.

In addition, the anisotropic conductive medium may be, for example, conductive balls or conductive particles. For example, the ACF may be a film in which conductive balls are mixed with an insulating base member. Thus, when heat and pressure are applied to the ACF, only a specific portion of the ACF is allowed to be conductive by the conductive balls. The ACF may contain a plurality of particles formed by coating the core of a conductive material with an insulating film made of a polymer material. In this case, as the insulating film is destroyed in a portion to which heat and pressure are applied, the portion is made to be conductive by the core. At this time, the cores may be deformed to form layers that contact each other in the thickness direction of the film. As a more specific example, heat and pressure are applied to the whole ACF, and an electrical connection in the Z-axis direction is partially formed by the height difference of a counterpart adhered by the ACF.

As another example, the ACF may contain a plurality of particles formed by coating an insulating core with a conductive material. In this case, as the conductive material is deformed (pressed) in a portion to which heat and pressure are applied, the portion is made to be conductive in the thickness direction of the film. As another example, the conductive material may be disposed through the insulating base member in the Z-axis direction to provide conductivity in the thickness direction of the film. In this case, the conductive material may have a pointed end.

The ACF may be a fixed array ACF in which conductive balls are inserted into one surface of the insulating base member. More specifically, the insulating base member may be formed of an adhesive material, and the conductive balls may be intensively disposed on the bottom portion of the insulating base member. Thus, when the base member is subjected to heat and pressure, it may be deformed together with the conductive balls, exhibiting conductivity in the vertical direction.

However, the present disclosure is not necessarily limited thereto, and the ACF may be formed by randomly mixing conductive balls in the insulating base member, or may be composed of a plurality of layers with conductive balls arranged on one of the layers (as a double-ACF).

The anisotropic conductive paste may be a combination of a paste and conductive balls, and may be a paste in which conductive balls are mixed with an insulating and adhesive base material. Also, the solution containing conductive particles may be a solution containing any conductive particles or nanoparticles.

3 FIG.A 140 160 170 130 160 170 140 Referring back to, the second electrodeis positioned on the insulating layerand spaced apart from the auxiliary electrode. That is, the conductive adhesive layeris disposed on the insulating layerhaving the auxiliary electrodeand the second electrodepositioned thereon.

130 170 140 160 150 150 120 140 After the conductive adhesive layeris formed with the auxiliary electrodeand the second electrodepositioned on the insulating layer, the semiconductor light emitting deviceis connected thereto in a flip-chip form by applying heat and pressure. Thereby, the semiconductor light emitting deviceis electrically connected to the first electrodeand the second electrode.

4 FIG. Referring to, the semiconductor light emitting device may be a flip chip-type light emitting device.

156 155 156 154 155 153 154 152 153 156 156 170 130 152 140 3 FIG. For example, the semiconductor light emitting device may include a p-type electrode, a p-type semiconductor layeron which the p-type electrodeis formed, an active layerformed on the p-type semiconductor layer, an n-type semiconductor layerformed on the active layer, and an n-type electrodedisposed on the n-type semiconductor layerand horizontally spaced apart from the p-type electrode. In this case, the p-type electrodemay be electrically connected to the auxiliary electrode, which is shown in, by the conductive adhesive layer, and the n-type electrodemay be electrically connected to the second electrode.

2 3 3 FIGS.,A andB 170 150 Referring back to, the auxiliary electrodemay be elongated in one direction. Thus, one auxiliary electrode may be electrically connected to the plurality of semiconductor light emitting devices. For example, p-type electrodes of semiconductor light emitting devices on left and right sides of an auxiliary electrode may be electrically connected to one auxiliary electrode.

150 130 150 156 170 152 140 150 130 150 170 150 140 More specifically, the semiconductor light emitting devicemay be press-fitted into the conductive adhesive layerby heat and pressure. Thereby, only the portions of the semiconductor light emitting devicebetween the p-type electrodeand the auxiliary electrodeand between the n-type electrodeand the second electrodemay exhibit conductivity, and the other portions of the semiconductor light emitting devicedo not exhibit conductivity as they are not press-fitted. In this way, the conductive adhesive layerinterconnects and electrically connects the semiconductor light emitting deviceand the auxiliary electrodeand interconnects and electrically connects the semiconductor light emitting deviceand the second electrode.

150 180 The plurality of semiconductor light emitting devicesmay constitute a light emitting device array, and a phosphor conversion layermay be formed on the light emitting device array.

150 120 120 The light emitting device array may include a plurality of semiconductor light emitting devices having different luminance values. Each semiconductor light emitting devicemay constitute a unit pixel and may be electrically connected to the first electrode. For example, a plurality of first electrodesmay be provided, and the semiconductor light emitting devices may be arranged in, for example, several columns. The semiconductor light emitting devices in each column may be electrically connected to any one of the plurality of first electrodes.

150 In addition, since the semiconductor light emitting devices are connected in a flip-chip form, semiconductor light emitting devices grown on a transparent dielectric substrate may be used. The semiconductor light emitting devices may be, for example, nitride semiconductor light emitting devices. Since the semiconductor light emitting devicehas excellent luminance, it may constitute an individual unit pixel even when it has a small size.

3 FIG. 190 150 190 130 150 As shown in, a partition wallmay be formed between the semiconductor light emitting devices. In this case, the partition wallmay serve to separate individual unit pixels from each other, and may be integrated with the conductive adhesive layer. For example, by inserting the semiconductor light emitting deviceinto the ACF, the base member of the ACF may form the partition wall.

190 In addition, when the base member of the ACF is black, the partition wallmay have reflectance and increase contrast even without a separate black insulator.

190 190 As another example, a reflective partition wall may be separately provided as the partition wall. In this case, the partition wallmay include a black or white insulator depending on the purpose of the display device. When a partition wall including a white insulator is used, reflectivity may be increased. When a partition wall including a black insulator is used, it may have reflectance and increase contrast.

180 150 150 180 180 181 182 The phosphor conversion layermay be positioned on the outer surface of the semiconductor light emitting device. For example, the semiconductor light emitting devicemay be a blue semiconductor light emitting device that emits blue (B) light, and the phosphor conversion layermay function to convert the blue (B) light into a color of a unit pixel. The phosphor conversion layermay be a red phosphoror a green phosphorconstituting an individual pixel.

181 182 120 120 140 That is, the red phosphorcapable of converting blue light into red (R) light may be laminated on a blue semiconductor light emitting device at a position of a unit pixel of red color, and the green phosphorcapable of converting blue light into green (G) light may be laminated on the blue semiconductor light emitting device at a position of a unit pixel of green color. Only the blue semiconductor light emitting device may be used alone in the portion constituting the unit pixel of blue color. In this case, unit pixels of red (R), green (G), and blue (B) may constitute one pixel. More specifically, a phosphor of one color may be laminated along each line of the first electrode. Accordingly, one line on the first electrodemay be an electrode for controlling one color. That is, red (R), green (G), and blue (B) may be sequentially disposed along the second electrode, thereby implementing a unit pixel.

150 However, embodiments of the present disclosure are not limited thereto. Unit pixels of red (R), green (G), and blue (B) may be implemented by combining the semiconductor light emitting deviceand the quantum dot (QD) rather than using the phosphor.

191 191 Also, a black matrixmay be disposed between the phosphor conversion layers to improve contrast. That is, the black matrixmay improve contrast of light and darkness.

However, embodiments of the present disclosure are not limited thereto, and anther structure may be applied to implement blue, red, and green colors.

5 FIG.A Referring to, each semiconductor light emitting device may be implemented as a high-power light emitting device emitting light of various colors including blue by using gallium nitride (GaN) as a main material and adding indium (In) and/or aluminum (Al).

In this case, each semiconductor light emitting device may be a red, green, or blue semiconductor light emitting device to form a unit pixel (sub-pixel). For example, red, green, and blue semiconductor light emitting devices R, G, and B may be alternately disposed, and unit pixels of red, green, and blue may constitute one pixel by the red, green and blue semiconductor light emitting devices. Thereby, a full-color display may be implemented.

5 FIG.B 150 181 182 183 a Referring to, the semiconductor light emitting devicemay include a white light emitting device W having a yellow phosphor conversion layer, which is provided for each device. In this case, in order to form a unit pixel, a red phosphor conversion layer, a green phosphor conversion layer, and a blue phosphor conversion layermay be disposed on the white light emitting device W. In addition, a unit pixel may be formed using a color filter repeating red, green, and blue on the white light emitting device W.

5 FIG.C 181 185 183 Referring to, a red phosphor conversion layer, a green phosphor conversion layer, and a blue phosphor conversion layermay be provided on a ultraviolet light emitting device. Not only visible light but also ultraviolet (UV) light may be used in the entire region of the semiconductor light emitting device. In an embodiment, UV may be used as an excitation source of the upper phosphor in the semiconductor light emitting device.

Referring back to this example, the semiconductor light emitting device is positioned on the conductive adhesive layer to constitute a unit pixel in the display device. Since the semiconductor light emitting device has excellent luminance, individual unit pixels may be configured despite even when the semiconductor light emitting device has a small size.

Regarding the size of such an individual semiconductor light emitting device, the length of each side of the device may be, for example, 80 μm or less, and the device may have a rectangular or square shape. When the semiconductor light emitting device has a rectangular shape, the size thereof may be less than or equal to 20 μm×80 μm.

In addition, even when a square semiconductor light emitting device having a side length of 10 μm is used as a unit pixel, sufficient brightness to form a display device may be obtained.

Therefore, for example, in case of a rectangular pixel having a unit pixel size of 600 μm×300 μm (i.e., one side by the other side), a distance of a semiconductor light emitting device becomes sufficiently long relatively.

Thus, in this case, it is able to implement a flexible display device having high image quality over HD image quality.

6 FIG. The above-described display device using the semiconductor light emitting device may be prepared by a new fabricating method. Such a fabricating method will be described with reference toas follows.

6 FIG. shows cross-sectional views of a method of fabricating a display device using a semiconductor light emitting device according to the present disclosure.

6 FIG. 130 160 170 140 160 110 110 120 170 140 120 140 110 160 Referring to, first of all, a conductive adhesive layeris formed on an insulating layerlocated between an auxiliary electrodeand a second electrode. The insulating layeris tacked on a wiring substrate. On the wiring substrate, a first electrode, the auxiliary electrodeand the second electrodeare disposed. In this case, the first electrodeand the second electrodemay be disposed in mutually orthogonal directions, respectively. In order to implement a flexible display device, the wiring substrateand the insulating layermay include glass or polyimide (PI) each.

130 160 For example, the conductive adhesive layermay be implemented by an anisotropic conductive film. To this end, an anisotropic conductive film may be coated on the substrate on which the insulating layeris located.

112 150 170 140 150 170 140 Subsequently, a temporary substrate, on which a plurality of semiconductor light emitting devicesconfiguring individual pixels are located to correspond to locations of the auxiliary electrodeand the second electrodes, is disposed in a manner that the semiconductor light emitting deviceconfronts the auxiliary electrodeand the second electrode.

112 112 150 In this regard, the temporarysubstrateis a growing substrate for growing the semiconductor light emitting deviceand may include a sapphire or silicon substrate.

The semiconductor light emitting device is configured to have a space and size for configuring a display device when formed in unit of wafer, thereby being effectively used for the display device.

110 112 110 112 150 170 140 150 150 150 Subsequently, the wiring substrateand the temporary substrateare thermally compressed together. By the thermocompression, the wiring substrateand the temporary substrateare bonded together. Owing to the property of an anisotropic conductive film having conductivity by thermocompression, only a portion among the semiconductor light emitting device, the auxiliary electrodeand the second electrodehas conductivity, via which the electrodes and the semiconductor light emitting devicemay be connected electrically. In this case, the semiconductor light emitting deviceis inserted into the anisotropic conductive film, by which a partition may be formed between the semiconductor light emitting devices.

112 112 Then the temporary substrateis removed. For example, the temporary substratemay be removed using Laser Lift-Off (LLO) or Chemical Lift-Off (CLO).

112 150 110 150 Finally, by removing the temporary substrate, the semiconductor light emitting devicesexposed externally. If necessary, the wiring substrateto which the semiconductor light emitting devicesare coupled may be coated with silicon oxide (SiOx) or the like to form a transparent insulating layer (not shown).

150 150 In addition, a step of forming a phosphor layer on one side of the semiconductor light emitting devicemay be further included. For example, the semiconductor light emitting devicemay include a blue semiconductor light emitting device emitting Blue (B) light, and a red or green phosphor for converting the blue (B) light into a color of a unit pixel may form a layer on one side of the blue semiconductor light emitting device.

The above-described fabricating method or structure of the display device using the semiconductor light emitting device may be modified into various forms. For example, the above-described display device may employ a vertical semiconductor light emitting device.

Furthermore, a modification or embodiment described in the following may use the same or similar reference numbers for the same or similar configurations of the former example and the former description may apply thereto.

7 FIG. 8 FIG. 8 FIG. 9 FIG. 8 FIG. is a perspective diagram of a display device using a semiconductor light emitting device according to another embodiment of the present disclosure,is a cross-sectional diagram taken along a cutting line D-D shown in, andis a conceptual diagram showing a vertical type semiconductor light emitting device shown in.

Referring to the present drawings, a display device may employ a vertical semiconductor light emitting device of a Passive Matrix (PM) type.

210 220 230 240 250 The display device includes a substrate, a first electrode, a conductive adhesive layer, a second electrodeand at least one semiconductor light emitting device.

210 220 210 The substrateis a wiring substrate on which the first electrodeis disposed and may contain polyimide (PI) to implement a flexible display device. Besides, the substratemay use any substance that is insulating and flexible.

210 210 220 The first electrodeis located on the substrateand may be formed as a bar type electrode that is long in one direction. The first electrodemay be configured to play a role as a data electrode.

230 210 220 230 230 The conductive adhesive layeris formed on the substratewhere the first electrodeis located. Like a display device to which a light emitting device of a flip chip type is applied, the conductive adhesive layermay include one of an Anisotropic Conductive Film (ACF), an anisotropic conductive paste, a conductive particle contained solution and the like. Yet, in the present embodiment, a case of implementing the conductive adhesive layerwith the anisotropic conductive film is exemplified.

220 210 250 250 220 250 220 After the conductive adhesive layer has been placed in the state that the first electrodeis located on the substrate, if the semiconductor light emitting deviceis connected by applying heat and pressure thereto, the semiconductor light emitting deviceis electrically connected to the first electrode. In doing so, the semiconductor light emitting deviceis preferably disposed to be located on the first electrode.

If heat and pressure is applied to an anisotropic conductive film, as described above, since the anisotropic conductive film has conductivity partially in a thickness direction, the electrical connection is established. Therefore, the anisotropic conductive film is partitioned into a conductive portion and a non-conductive portion.

230 250 220 Furthermore, since the anisotropic conductive film contains an adhesive component, the conductive adhesive layerimplements mechanical coupling between the semiconductor light emitting deviceand the first electrodeas well as mechanical connection.

250 230 250 250 250 Thus, the semiconductor light emitting deviceis located on the conductive adhesive layer, via which an individual pixel is configured in the display device. As the semiconductor light emitting devicehas excellent luminance, an individual unit pixel may be configured in small size as well. Regarding a size of the individual semiconductor light emitting device, a length of one side may be equal to or smaller than 80 μm for example and the individual semiconductor light emitting devicemay include a rectangular or square device. For example, the rectangular device may have a size equal to or smaller than 20 μm×80 μm.

250 The semiconductor light emitting devicemay have a vertical structure.

240 250 220 Among the vertical type semiconductor light emitting devices, a plurality of second electrodesrespectively and electrically connected to the vertical type semiconductor light emitting devicesare located in a manner of being disposed in a direction crossing with a length direction of the first electrode.

9 FIG. 250 256 255 256 254 255 253 254 252 253 256 220 230 252 240 250 Referring to, the vertical type semiconductor light emitting deviceincludes a p-type electrode, a p-type semiconductor layerformed on the p-type electrode, an active layerformed on the p-type semiconductor layer, an n-type semiconductor layerformed on the active layer, and an n-type electrodeformed on then-type semiconductor layer. In this case, the p-type electrodelocated on a bottom side may be electrically connected to the first electrodeby the conductive adhesive layer, and the n-type electrodelocated on a top side may be electrically connected to a second electrodedescribed later. Since such a vertical type semiconductor light emitting devicecan dispose the electrodes at top and bottom, it is considerably advantageous in reducing a chip size.

8 FIG. 280 250 250 251 280 280 281 282 Referring toagain, a phosphor layermay formed on one side of the semiconductor light emitting device. For example, the semiconductor light emitting devicemay include a blue semiconductor light emitting deviceemitting blue (B) light, and a phosphor layerfor converting the blue (B) light into a color of a unit pixel may be provided. In this regard, the phosphor layermay include a red phosphorand a green phosphorconfiguring an individual pixel.

281 282 Namely, at a location of configuring a red unit pixel, the red phosphorcapable of converting blue light into red (R) light may be stacked on a blue semiconductor light emitting device. At a location of configuring a green unit pixel, the green phosphorcapable of converting blue light into green (G) light may be stacked on the blue semiconductor light emitting device. Moreover, the blue semiconductor light emitting device may be singly usable for a portion that configures a blue unit pixel. In this case, the unit pixels of red (R), green (G) and blue (B) may configure a single pixel.

Yet, the present disclosure is non-limited by the above description. In a display device to which a light emitting device of a flip chip type is applied, as described above, a different structure for implementing blue, red and green may be applicable.

240 250 250 240 250 Regarding the present embodiment again, the second electrodeis located between the semiconductor light emitting devicesand connected to the semiconductor light emitting devices electrically. For example, the semiconductor light emitting devicesare disposed in a plurality of columns, and the second electrodemay be located between the columns of the semiconductor light emitting devices.

250 240 250 Since a distance between the semiconductor light emitting devicesconfiguring the individual pixel is sufficiently long, the second electrodemay be located between the semiconductor light emitting devices.

240 The second electrodemay be formed as an electrode of a bar type that is long in one direction and disposed in a direction vertical to the first electrode.

240 250 240 250 240 250 In addition, the second electrodeand the semiconductor light emitting devicemay be electrically connected to each other by a connecting electrode protruding from the second electrode. Particularly, the connecting electrode may include a n-type electrode of the semiconductor light emitting device. For example, the n-type electrode is formed as an ohmic electrode for ohmic contact, and the second electrode covers at least one portion of the ohmic electrode by printing or deposition. Thus, the second electrodeand the n-type electrode of the semiconductor light emitting devicemay be electrically connected to each other.

8 FIG. 240 230 210 250 240 240 240 230 Referring toagain, the second electrodemay be located on the conductive adhesive layer. In some cases, a transparent insulating layer (not shown) containing silicon oxide (SiOx) and the like may be formed on the substratehaving the semiconductor light emitting deviceformed thereon. If the second electrodeis placed after the transparent insulating layer has been formed, the second electrodeis located on the transparent insulating layer. Alternatively, the second electrodemay be formed in a manner of being spaced apart from the conductive adhesive layeror the transparent insulating layer.

240 250 240 250 If a transparent electrode of Indium Tin Oxide (ITO) or the like is sued to place the second electrodeon the semiconductor light emitting device, there is a problem that ITO substance has poor adhesiveness to an n-type semiconductor layer. Therefore, according to the present disclosure, as the second electrodeis placed between the semiconductor light emitting devices, it is advantageous in that a transparent electrode of ITO is not used. Thus, light extraction efficiency can be improved using a conductive substance having good adhesiveness to an n-type semiconductor layer as a horizontal electrode without restriction on transparent substance selection.

8 FIG. 290 250 250 290 250 290 230 250 Referring toagain, a partitionmay be located between the semiconductor light emitting devices. Namely, in order to isolate the semiconductor light emitting deviceconfiguring the individual pixel, the partitionmay be disposed between the vertical type semiconductor light emitting devices. In this case, the partitionmay play a role in separating the individual unit pixels from each other and be formed with the conductive adhesive layeras an integral part. For example, by inserting the semiconductor light emitting devicein an anisotropic conductive film, a base member of the anisotropic conductive film may form the partition.

290 In addition, if the base member of the anisotropic conductive film is black, the partitionmay have reflective property as well as a contrast ratio may be increased, without a separate block insulator.

190 290 For another example, a reflective partition may be separately provided as the partition. The partitionmay include a black or white insulator depending on the purpose of the display device.

240 230 250 290 250 240 250 250 240 250 In case that the second electrodeis located right onto the conductive adhesive layerbetween the semiconductor light emitting devices, the partitionmay be located between the vertical type semiconductor light emitting deviceand the second electrodeeach. Therefore, an individual unit pixel may be configured using the semiconductor light emitting device. Since a distance between the semiconductor light emitting devicesis sufficiently long, the second electrodecan be placed between the semiconductor light emitting devices. And, it may bring an effect of implementing a flexible display device having HD image quality.

8 FIG. 291 291 In addition, as shown in, a black matrixmay be disposed between the respective phosphors for the contrast ratio improvement. Namely, the black matrixmay improve the contrast between light and shade.

10 FIG. 11 FIG. 11 FIG. 10 FIG. is a structural diagram of a display device according to an embodiment.is a circuit diagram of a unit light emitting area according to an embodiment. Specifically, the circuit diagram inillustrates an area E inin an enlarged manner.

300 300 300 A display deviceaccording to one embodiment may be the display deviceusing a semiconductor light emitting device LD. In addition, the display devicemay be a device that outputs an image via active matrix (AM) driving or a flat lighting device (a back light unit, BLU) capable of local dimming via the AM driving.

300 310 310 310 310 320 330 340 350 The display deviceaccording to one embodiment may include an image output panelfor outputting the image and a controller for providing a signal to the image output panel. In the image output panel, a plurality of unit light emitting areas E are arranged along rows and columns, so that each light emitting area E may emit light independently. The controller for providing the signal to the image output panelmay include a row driver, a column driver, a timing controller, and a power supply.

The unit light emitting area E may include at least one semiconductor light emitting device LD and a driving circuit DC for driving the semiconductor light emitting device LD. The driving circuit DC is basically a 2T1C driving circuit for the AM driving, and is able to be serially connected to one end of the semiconductor light emitting device LD.

The semiconductor light emitting device LD may be a mini LED or a micro LED. In this regard, the mini LED may be an LED having a size of hundreds of microns, and the micro LED may be an LED having a size of several to several tens of microns. The mini LED may be an LED with a growing substrate, and the micro LED may be an LED from which the growing substrate is removed.

The driving circuit DC may be divided into a switching unit and a driver.

1 1 320 1 1 2 1 The switching unit may include a first transistor (switch TFT) Tfor driving the semiconductor light emitting device LD ON or OFF. A scan line Si may be connected to a gate terminal of the first transistor Tto receive a scan signal via the row driver. In addition, a data line Dj may be connected to a drain terminal of the first transistor T, and a source terminal of the first transistor Tmay be connected to a gate terminal of a second transistor (driving TFT) Tincluded in the driver. Depending on a type of the first transistor T, the components respectively connected to the drain terminal and the source terminal may be reversed.

2 1 2 1 2 2 2 1 2 2 1 2 11 FIG. 11 FIG. The driver may include the second transistor Tand a first capacitor C. The driver may be serially connected to the semiconductor light emitting device LD. Specifically, the semiconductor light emitting device LD may be connected to a drain or source terminal of the second transistor T. The first capacitor Cmay be connected to a gate terminal of the second transistor Tand the drain or source terminal of the second transistor Tto which the semiconductor light emitting device LD is not connected. Specifically, (a) inshows an embodiment in which the semiconductor light emitting device LD is connected to the source terminal of the second transistor Tand the first capacitor Cis connected to and located between the gate terminal and the drain terminal of the second transistor T. (b) inshows an embodiment in which a semiconductor light emitting device LE is connected to the drain terminal of the second transistor Tand the first capacitor Cis connected to and located between the gate terminal and the source terminal of the second transistor T.

350 2 2 2 11 FIG. 11 FIG. A first fixed voltage and a second fixed voltage applied from the power supplymay be applied to the driver and the other end of the semiconductor light emitting device LD. The first fixed voltage may be applied to the other end of the semiconductor light emitting device LD, and the second fixed voltage may be applied to the drain or source terminal of the second transistor Tto which the semiconductor light emitting device LD is not connected. In this regard, the first fixed voltage may be VDD, and the second fixed voltage may be VSS. In some cases, the first fixed voltage may be VSS and the second fixed voltage may be VDD. Specifically, (a) inshows an embodiment in which the first fixed voltage applied to the other end of the semiconductor light emitting device LD is the VSS and the second fixed voltage applied to the drain terminal of the second transistor Tto which the semiconductor light emitting device LD is not connected is the VDD. (b) inshows an embodiment in which the first fixed voltage applied to the other end of the semiconductor light emitting device LE is the VDD and the second fixed voltage applied to the source terminal of the second transistor Tto which the semiconductor light emitting device LD is not connected is the VSS.

310 320 1 1 330 1 1 The image output panelmay include the plurality of unit light emitting areas E along the rows and the columns, and the row drivermay sequentially provide the scan signals to scan lines Sto Sn respectively disposed on the rows. Specifically, the scan signals may be sequentially provided to the scan lines Sto Sn during one frame. The column drivermay provide data signals to column lines Dto Dm respectively disposed on the columns. Specifically, the data signals may be simultaneously provided to the column lines Dto Dm during the one frame.

340 340 330 1 2 320 330 1 2 The timing controllermay receive input image data Data and an input control signal for controlling display of the input image data from an external graphic controller (not shown). The input control signals may include, for example, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a main clock MCLK. The timing controllermay transmit the input image data Data to the column driver, generate a scan control signal CONTand a data control signal CONTand transmit the signals to the row driverand the column driver, respectively. The scan control signal CONTmay include a scan start signal SSP instructing to start a scan and at least one clock signal SCLK, and the data control signal CONTmay include a horizontal synchronization start signal STH instructing transmission of the input image data for pixels P in one row and at least one clock signal DCLK.

350 350 350 350 2 350 350 st nd st nd The power supplymay apply the first fixed voltage and the second fixed voltage to the unit light emitting area E. The power supplymay apply the first fixed voltage and the second fixed voltage to each unit light emitting area E. However, in this case, the circuit may become complicated. To prevent such problem, the power supplymay apply the first fixed voltage and the second fixed voltage to the unit light emitting area E for each column or row. Specifically, the power supplymay include power supply lines 1line and 2line for providing the first fixed voltage and the second fixed voltage for each column. The first power supply line 1line may be connected to the other end of the semiconductor light emitting device LD to apply the first fixed voltage thereto. The second power supply line 2line may be connected to the second transistor Tto apply the second fixed voltage thereto. In some cases, the power supplymay provide the first fixed voltage and the second fixed voltage for each row. The first fixed voltage and the second fixed voltage applied from the power supplymay form a potential difference across the semiconductor light emitting device LD in response to the scan signal and the data signal.

11 FIG. 11 FIG. A pixel structure constructed in the unit light emitting area E may have the circuit diagram inand may be formed in various ways. Hereinafter, an embodiment of the pixel structure having the circuit diagram inand constructed in the unit light emitting area E will be described.

12 17 FIGS.to 12 FIG. 11 FIG. 13 FIG. 12 FIG. 14 FIG. 12 FIG. 15 FIG. 16 FIG. 17 FIG. 12 FIG. are views for illustrating an embodiment of the pixel structure constructed in the unit light emitting area E. Specifically,is a plan view of a pixel structure having a circuit diagram in.is a plan view of a first layer in.is a plan view of a second layer in.shows a via hole for connecting a first layer and a second layer to each other.is a view for illustrating a connection relationship between a second layer, a driving TFT, and a semiconductor light emitting device.is a cross-sectional view taken along a line X-X′ in.

12 17 FIGS.to 11 FIG. Specifically,illustrate a pixel structure corresponding to (b) in.

400 500 400 500 400 500 400 400 The pixel structure may be formed as a first layerand a second layerare stacked and connected to each other using a via hole. The first layerand the second layermay be metal layers and may form conductive wires through which electricity flows, and at least one of an insulating layer and a protective layer may be included between the first and second layers. In some cases, a plurality of insulating layers or a plurality of protective layers may be disposed. The first layermay be disposed on the second layer, and in some cases, the second layermay be disposed on the first layer.

400 500 400 500 400 500 Each of the first layerand the second layermay include a plurality of segmented metal patterns. The metal patterns of the first layerand the second layermay be connected to each other with a via hole to function as the conductive wires through which the electricity flows. In some cases, overlapping metal patterns with a unit potential difference may serve as a capacitor. Hereinafter, structures of the first layerand the second layerwill be described in detail.

411 412 400 510 500 411 412 400 510 500 The VSS voltage may be applied to VSS metal patternsandof the first layerand a VSS metal patternof the second layer. The VSS metal patternsandof the first layerand the VSS metal patternof the second layermay be connected to each other with a via hole.

421 422 400 520 500 421 422 400 520 500 The VDD voltage may be applied to VDD metal patternsandof the first layerand a VDD metal patternof the second layer. The VDD metal patternsandof the first layerand the VDD metal patternof the second layermay be connected to each other with a via hole.

411 412 421 422 400 510 520 500 411 412 421 422 400 510 520 500 st nd The VSS metal patternsandand the VDD metal patternsandof the first layerand the VSS metal patternand the VDD metal patternof the second layermay be arranged around edges of the pixel structure. The VSS metal patternsandand the VDD metal patternsandof the first layer, and the VSS metal patternand the VDD metal patternof the second layermay be components connected to or included in the first power supply line 1line and the second power supply line 2line.

411 412 400 421 422 400 431 411 412 421 422 The VSS metal patternsandof the first layermay be segmented from each other and the VDD metal patternsandof the first layermay be segmented from each other, and the scan metal patternthrough which the scan signal flows may extend between the patternsandand between the patternsand.

411 412 510 421 422 520 531 531 500 The metal patterns,, andto which the VSS voltage is applied may be spaced apart from the metal patterns,, andto which the VDD voltage is applied so as to define a space therebetween, and a data metal patternthrough which the data signal flows may extend through the space. The data metal patternmay be included in the second layer.

1 2 411 412 510 421 422 520 400 500 The first transistor T, the second transistor T, and the at least one semiconductor light emitting device LD may be included in an area surrounded by the metal patterns,, andto which the VSS voltage is applied and the metal patterns,, andto which the VDD voltage is applied. The metal patterns disposed in the first layerand the metal patterns disposed in the second layermay serve as conductive wires for electrically connecting components with each other.

431 1 531 1 500 541 1 2 The scan metal patternmay be connected to the gate terminal of the first transistor T. The data metal patternmay be connected to the source terminal of the first transistor T. The second layermay include a connection metalfor connecting the drain terminal of the first transistor Tand the gate terminal of the second transistor Tto each other.

400 441 2 500 542 2 441 542 441 542 17 FIG. The first layermay include a first metal patternconnected to the gate terminal of the second transistor T. The second layermay include a second metal patternconnected to the source terminal of the second transistor T. The first metal patternand the second metal patternmay not be connected to each other via a via hole. The first metal patternand the second metal patternmay be formed so as to at least partially overlap each other (see).

1 441 542 2 610 620 441 542 1 441 542 1 441 542 1 Specifically, a first capacitor Cmay be formed as the first metal patternand the second metal patternextending from the area where the transistor Tis disposed overlap each other with insulating layersandinterposed therebetween. An area where the first metal patternand the second metal patternoverlap may each other correspond to the first capacitor C. A size of the area where the first metal patternand the second metal patternoverlap each other may be related to the capacitance of the first capacitor C. The larger the area where the first metal patternand the second metal patternoverlap each other, the greater the capacitance of the first capacitor Cmay be.

542 500 412 400 2 4121 412 400 542 441 4121 542 542 542 542 500 4121 4121 412 400 4121 400 441 The second metal patterndisposed on the second layermay be connected to the VSS metal patterndisposed on the first layerthrough the via hole. In this regard, the second metal pattern may correspond to a metal pattern connected to the second transistor T. Specifically, the second metal pattern may correspond to a layer forming a capacitor. That is, a partial areaof the VSS metal patternincluded in the first layermay correspond to the second metal pattern. Specifically, the second metal pattern may include an upper second metal patterndisposed on the first metal pattern, and a lower second metal patternconnected to the upper second metal patternvia the via hole and disposed on a layer below the upper second metal pattern. In this regard, the upper second metal patternmay correspond to the second metal patterndisposed on the second layer. The lower second metal patternmay correspond to the portionextending inwardly of the VSS metal patternin the first layer. The lower second metal patternmay be disposed on the first layerand disposed on the same layer as the first metal pattern.

400 500 442 543 2 442 400 543 543 The first layerand the second layermay respectively include drain metalsandconnected to the drain terminal of the second transistor T. The drain metalof the first layerand the drain metalof the second layermay be connected to each other with a via hole.

1 4 451 452 453 551 552 553 1 4 451 551 452 552 453 553 1 442 543 451 551 2 451 551 452 552 452 552 453 553 4 453 553 421 422 520 A plurality of semiconductor light emitting devices LDto LDmay be connected to each other in series via third metal patterns,,,,, and. Specifically, the plurality of semiconductor light emitting devices LDto LDmay be composed of four semiconductor light emitting devices, and the third metal patterns may be segmented into first portionsand, second portionsand, and third portionsand. A first semiconductor light emitting device LDmay be disposed between the drain metalsandand the first portionsand, a second semiconductor light emitting device LDmay be disposed between the first portionsandand the second portionsand, a third semiconductor light emitting device may be disposed between the second portionsandand the third portionsand, and a fourth semiconductor light emitting device LDmay be disposed between the third portionsandand the VDD metals,and.

451 551 452 452 453 553 451 400 551 500 551 500 531 452 400 552 500 452 400 452 452 452 431 452 452 412 452 452 412 542 453 400 553 500 553 500 553 553 531 553 553 a b c b c a b a b a b. In this regard, the first portionsand, the second portionsand, and the third portionsandmay be arranged in a clockwise or counterclockwise direction. Specifically, the first portionof the first layerand the first portionof the second layermay be connected to each other with a via hole, and the first portionof the second layermay be segmented into two pieces for a data metalto extend therebetween. The second portionof the first layerand the second portionof the second layermay be connected to each other with a via hole, and the second portionof the first layermay be segmented into three pieces,, andfor the scan metalto extend between the piecesandand for the VSS metalto extend inwardly between the piecesand. The VSS metalextending inwardly may be connected to the second metal patternwith a via hole. The third portionof the first layerand the third portionof the second layermay be connected to each other with a via hole. The third portionof the second layermay be segmented into two piecesandfor the data metalto extend between the piecesand

16 FIG. 2 531 1 4 2 4 Referring to, a signal flow will be described. When the data signal is introduced to the gate terminal of the second transistor Tvia the data metal, a voltage difference is generated across each of the semiconductor light emitting devices LDto LD, and an LED signal line is formed from the drain terminal of the second transistor Tto pass through the first semiconductor light emitting device and then pass through the fourth semiconductor light emitting device LD.

11 FIG. The pixel structure corresponding to (a) inmay be included in the present disclosure within a range easily changeable by a person skilled in the art.

1 1 1 1 In forming the pixel structure for the AM driving, it may be important to secure the capacitance of the first capacitor C. As the capacitance of the first capacitor Cincreases, a flicker phenomenon resulted from a signal leaked from the first transistor Tmay be prevented from occurring. The flicker phenomenon refers to image quality defects in which the semiconductor light emitting device LD flickers as the signal leaked from the first transistor Tis applied to the driving TFT.

1 400 500 1 1 2 1 An area occupied by the first capacitor Cmay be defined limitedly by occupied areas and overlap relationships of the plurality of metal patterns respectively disposed on the first layerand the second layer. As a size of the unit light emitting area E decreases, it may become difficult to secure the capacitance of the first capacitor Cby expanding the area occupied by the first capacitor C. Therefore, another embodiment including a second capacitor Cto offset the capacitance limit of the first capacitor Cwill be described.

18 FIG. 11 FIG. is a circuit diagram of a unit light emitting area according to another embodiment. For the same component,will be referred to.

18 FIG. 2 1 2 1 1 1 2 The driving circuit DC shown inshows an embodiment in which the second capacitor Cis additionally connected in parallel to the first capacitor C. The second capacitor Cmay be connected in parallel to the first capacitor C, and may play a role of supplementing the capacitance of the first capacitor C. That is, a sum of the capacitance of the first capacitor Cand a capacitance of the second capacitor Cmay correspond to a capacitance of a capacitor of the driving circuit DC.

19 FIG. 18 FIG. 20 FIG. 19 FIG. 21 FIG. 19 FIG. 12 17 FIGS.to 19 FIG. 12 FIG. 20 FIG. 710 is a plan view of a pixel structure having a circuit diagram in.is a plan view of an active layer of a driving TFT included in.is a cross-sectional view oftaken along a line Y-Y′. For a description of the same component below, reference may be made to. Specifically, the pixel structure indiffers from the pixel structure inin an area of an active layerin.

710 1 2 710 710 2 20 FIG. The active layerinmay include an active layer included in first transistor Tand an active layer included in the second transistor T. The active layer, as a component that physically connects the drain and source terminals of the transistor to each other, may be a component that electrically connects the drain and source terminals to each other when a voltage is applied to the gate terminal. Hereinafter, a description will be made by limiting the active layeras a component included in the second transistor T.

710 2 2 710 542 610 620 710 4121 2 Specifically, the active layerincluded in the second transistor Tmay extend in an area where the second transistor Tis disposed, and the active layermay overlap the second metal patternwith the insulating layersandtherebetween to form the second capacitor. Specifically, the active layermay overlap the lower second metal patternto form the second capacitor C.

710 400 500 1 400 500 1 710 400 1 2 The active layermay be disposed between the first layerand the second layer. That is, the first capacitor Cmay be formed between the first layerand the second layer, and the second capacitor Cmay be formed between the active layerand the first layer. In this regard, the first capacitor Cand the second capacitor Cmay be respectively formed in a first area and a second area that do not overlap each other.

2 552 500 3 552 710 3 2 3 2 3 1 4 3 2 3 In a process of designing the pixel structure, the second capacitor Cmay partially overlap the third metaldisposed on the second layer. In this case, a parasitic capacitor Cmay be formed between the third metaland the active layer. On the circuit diagram, the parasitic capacitor Cmay be formed between a node between the second semiconductor light emitting device LDand the third semiconductor light emitting device LDand the gate terminal of the second transistor T. The parasitic capacitor Cmay generate a luminance difference between the semiconductor light emitting devices LDto LD. In addition, the parasitic capacitor Cmay reduce the capacitance of the second capacitor C. Therefore, it may be preferable not to form such a parasitic capacitor C. Hereinafter, a pixel structure according to another embodiment will be described.

22 FIG. 22 FIG. 18 FIG. 21 FIG. is a cross-sectional view of a pixel structure according to another embodiment. Specifically,is a cross-sectional view of the pixel structure corresponding toviewed from a direction corresponding to that in.

3 553 1 2 To minimize the generation of the parasitic capacitor C, it may be desirable that the third metal patternis disposed so as not to overlap the first capacitor Cor the second capacitor Cwhen designing the pixel structure.

553 553 2 First, the overlapped area may be reduced by reducing a width of the third metal pattern. The third metal pattern, as a component that connects the semiconductor light emitting devices LD to each other, may be minimized in the width in the area overlapping the second capacitor C.

710 553 710 400 500 553 400 500 3 710 553 4 553 4121 553 4 3 552 710 Second, the active layermay be disposed so as not to overlap the third metal pattern. The active layermay be disposed between the first layerand the second layerand overlap the third metal patternin an area narrower than a distance between the first layerand the second layer. Because the capacitance of the parasitic capacitor Cincreases as the distance decreases, it may be desirable that the active layerand the third metal patternare disposed so as not to overlap each other. In this regard, a parasitic capacitor Cmay also be formed between the third metal patternand the lower second metal pattern. However, because the width of the third metal patternis reduced and a spacing between the pieces of the third metal pattern is widened, an influence of the parasitic capacitor Cmay be less than that of the parasitic capacitor Cformed between the third metaland the active layer.

The above description is merely illustrative of the technical idea of the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains will be able to make various modifications and variations without departing from the essential characteristics of the present disclosure.

Therefore, embodiments disclosed in the present disclosure are not intended to limit the technical idea of the present disclosure, but to describe, and the scope of the technical idea of the present disclosure is not limited by such embodiments.

The scope of protection of the present disclosure should be interpreted by the claims below, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present disclosure.