Circuit snapback and charge diversion for cross-point arrays

Memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Non-volatile memory can be made to appear non-volatile at least for a limited time by, external to the memory chip, adding battery back to the power supply.

The memory cells may reside in a cross-point memory array. In a memory array with a cross-point type architecture, one set of conductive lines run across the surface of a substrate and another set of conductive lines are formed above the other set of conductive lines running in an orthogonal direction relative to the initial layer. The memory cells are located at the cross-point junctions of the two sets of conductive lines. Cross-point memory arrays are sometimes referred to as cross-bar memory arrays.

A programmable resistance memory cell is formed from a material having a programmable resistance. In a binary approach, the programmable resistance memory cell can be programmed into one of two resistance states: high resistance state (HRS) and low resistance state (LRS). In some approaches, more than two resistance states may be used. One type of programmable resistance memory cell is a magnetoresistive random access memory (MRAM) cell. An MRAM cell uses magnetization to represent stored data, in contrast to some other memory technologies that use electronic charges (DRAM) or voltages (SRAM) to store data. A bit of data is written to an MRAM cell by changing the direction of magnetization of a magnetic element (“the free layer”) within the MRAM cell, and a bit is read by measuring the resistance of the MRAM cell, such resistance changing with the direction of magnetization. However, the cross-point memory array may have other types of memory cells. For example, the cross-point memory array may have memory cell of other technologies such as ReRam, PCM (Phase Change Memory), or FeRam.

In a cross-point memory array, each memory cell may contain a threshold switching selector in series with the material having the programmable resistance. The threshold switching selector has a high resistance (in an off or non-conductive state) until it is biased to a voltage higher than its threshold voltage (Vt) or current above its threshold current, (It), and until its voltage bias falls below Vhold (“Voffset”) or current below a holding current Ihold. After the Vt is exceeded and while Vhold is exceeded across the threshold switching selector, the threshold switching selector has a relatively lower resistance (in an on or conductive state). The threshold switching selector remains on until its current is lowered below a holding current Ihold, or the voltage is lowered below a holding voltage, Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. To read a memory cell, the threshold switching selector is activated by being turned on before the resistance state of the memory cell is determined. One example of a threshold switching selector is an Ovonic Threshold Switch (OTS). Other examples of threshold switching selectors include, but are not limited to, Volatile Conductive Bridge (VCB), Metal-Insulator-Metal (MIM), or other material that provides a highly non-linear dependence of current on select voltage.

A forced current technique can be used for reading or writing a programmable resistance memory cell in a cross-point array whereby a current is driven to the memory cell that is address selected for read or write (“selected memory cell”). The cross-point array is composed of orthogonal wire sets in two or more planes. For example, a current is driven to a selected wire in the X direction while a voltage is applied to selected wire in the Y direction. The current will charge up the voltage across the selected memory cell until the threshold switching selector turns on. Then, while the current is driven through the programmable resistance memory element of the selected memory cell, the voltage across the selected cell is sensed.

The switching on of a threshold switching selector can result in a snapback current. Specifically, the voltage across the memory cell drops rapidly after the threshold switching selector turns on, resulting in a snapback current. This snapback current can flow through the programmable resistance memory element, which could potentially change the state of the programmable resistance memory element prior to sensing the memory element bit state; e.g., a read disturb that results in a miss-read. Thus, programmable resistance memory elements such as, but not limited to MRAM elements, could inadvertently and undesirably have their state changed due to snapback currents that flow through the memory elements during the read operation.

Technology is disclosed for a memory system and method for reading programmable resistance memory cells in a cross-bar memory array. Each memory cell may have a threshold switching selector in series with a programmable resistance memory element. The memory system has control circuitry adjacent to the cross-bar memory array that is used to generate and deliver currents to the cross-bar memory array. The capacitance associated with this control circuitry can impact the magnitude of a snapback current that results when the threshold switching selector switches on. The memory system temporarily provides capacitive isolation of the selected memory cell from this circuit capacitance while the snapback current is present. In one technique the memory system temporarily increases resistance of one or more decode transistors that select the word line, which provides capacitive isolation. However, to read the memory cell the resistance of the one or more decode transistors should be low. Therefore, the capacitive isolation is removed prior to reading the cell by changing the resistance of the one or more decode transistors to a higher resistance. This higher resistance provides for a better signal-to-noise ratio when sensing the memory cell. However, the removal of the capacitive isolation may itself result in a snapback current that could inadvertently flip the state of the memory cell. An embodiment of the memory system provides a discharge path to a node between the control circuitry and the selected memory cell during a period in which the capacitive isolation is removed. This discharge path prevents a current that may arise from removing the capacitive isolation from inadvertently flipping the state of the memory cell. In one embodiment, the discharge path includes a voltage source, such as a step voltage pulse. In one embodiment, the discharge path includes a capacitor. Another advantage of the discharge path is that the capacitive isolation may be made stronger. The stronger capacitive isolation provides better protection against the snapback current from the threshold switching selector turning on.

One technique for reading programmable resistance memory cells is referred to as a globally referenced read. A globally referenced read is sometimes referred to as a midpoint read or midpoint referenced read. A globally referenced read may use a reference voltage that is between the lower resistance state (LRS) and the higher resistance state (HRS). Here, the LRS and HRS refer to the voltage that appears across the cell in response to the read current. For example, the midpoint reference may be a reference voltage that is midway between two voltages that correspond to sensing a cell having either the LRS or the HRS. In a forced current approach, memory cell's state is determined based on whether the sensed voltage, Vsense, is higher or lower than the midpoint reference voltage, Vref.

1 2 1 1 2 1 2 1 2 Another technique for reading programmable resistance memory cells is commonly referred to as a self-referenced read (SRR). In an SRR, rather than using a midpoint reference that is independent of the state of the cell, the reference is generated based on sensing the cell itself. In a destructive SRR, it is possible that the state of the memory cell is changed (e.g., destroyed) by a write operation of the SRR. One SRR technique includes a first read (Read), followed by a destructive write to a known state (e.g., the high resistance state HRS), and a second read (Read). The results of the two reads are compared to determine the original state of the cell. One technique for the first read is to apply a read current through the memory cell, resulting in a voltage across the cell having a magnitude that is representative of the resistance of the memory cell. The voltage is stored and may be adjusted (for example, up or down by 150 mV) for comparison with a voltage sample from the second read. The voltage adjustment can be approximately half the signal difference across the MRAM for each state. For example, if the MRAM low resistance state (LRS) is 25 Kohm, the high resistance state 50 Kohm, and the read current 15 μA, the difference from a state change is 375 mV so an adjustment of approximately 182.5 mV could be made from Readstored voltage of SRR. The determination of the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage. For example, if the first sampled voltage from Readof SRR was adjusted up and the write was to the HRS, then if the cell was originally in the HRS then the second sampled voltage from Readshould be about the same as Readand therefore lower than the first read voltage after adjusting it up. However, if the cell was originally in the LRS, then the second sampled voltage from Readshould be higher than the adjusted up voltage from Readdue to the higher Readvoltage resulting from writing the bit from low resistance LRS to the HRS.

In an embodiment the memory system is used to read programmable resistance memory cells that reside in a cross-point memory array. In a memory array with a cross-point type architecture, one set of conductive lines run across the surface of a substrate and another set of conductive lines are formed over the other set of conductive lines, running over the substrate in a direction perpendicular to the other set of conductive lines. The memory cells are located at the cross-point junctions of the two sets of conductive lines. Cross-point memory arrays are sometimes referred to as cross-bar memory arrays. In an embodiment, the memory cells each have a magnetoresistive memory element in series with an OTS, which may be referred to as MRAM memory cell. However, the cross-point memory array may have other types of memory cells. For example, the cross-point memory array may have memory cells of other technologies such as ReRam, PCM (Phase Change Memory), FeRam. Also, the threshold switching selector is not required to be an OTS and could be a pair of diodes with anode to cathode . . .

In some embodiments, the programmable resistance memory cell has a magnetoresistive random access memory (MRAM) element. As used herein, direction of magnetization is the direction that the magnetic moment is oriented with respect to a reference direction set by another element of the MRAM (“the reference layer”). In some embodiments, the low resistance is referred to as a parallel or P-state or LRS, and the high resistance is referred to as an anti-parallel or AP-state or HRS. MRAM can use the spin-transfer torque effect to change the direction of the magnetization from P-state to AP-state and vice-versa, which typically requires bipolar (bi-directional write) operation for writes. However, SRR of programmable resistance memory cells as disclosed herein is not limited to memory cells having MRAM elements or OTS elements.

1 FIG. 100 120 100 is a block diagram of one embodiment of a non-volatile memory system (or more briefly “memory system”)connected to a host system. Memory systemcan implement the technology presented herein for a system for reading a programmable resistance memory cell having a threshold switching selector. In an embodiment, the memory cells have a programmable resistance memory element (e.g., MRAM element) in series with a threshold switching selector such as an OTS. Many types of memory systems can be used with the technology proposed herein. Example memory systems include dual in-line memory modules (DIMMs), solid state drives (“SSDs”), memory cards and embedded memory devices; however, other types of memory systems can also be used.

100 102 104 140 140 140 140 102 164 140 102 140 102 126 120 102 104 104 104 100 140 140 164 124 122 124 1 FIG. Memory systemofcomprises a memory controller, memoryfor storing data, and local memory(e.g., MRAM, ReRAM, DRAM). The local memorymay be non-volatile and retain data after power off. The local memorymay be volatile and not be expected to retain data after power off. In one embodiment the local memoryis MRAM. In an embodiment, the local memory MRAM is not required to retain data after power-off. However, the local memory MRAM may retain data after power-off. In one embodiment, memory controllerand/or local memory controllerprovides access to programmable resistance memory cells in local memory. For example, memory controllermay provide for access in a cross-point array of MRAM cells in local memory. In another embodiment the memory controlleror interfaceor both are eliminated and the memory packages are connected directly to the hostthrough a bus such as DDRn. Or they are connected to a Host memory management unit (MMU). In another instance, the memory controlleror portions are moved onto the memoryfor direct connection of the memoryto the host, such as by providing parity bits, ECC, and wear level on the memoryalong with an DDRn interface to/from the host or MMU. The term memory system, as used throughout this document, is not limited to memory system. For example, the local memoryor the combination of local memoryand local memory controllercould be considered to be a memory system. Likewise, host memoryor the combination of host processorand host memoryconsidered to be a memory system.

100 102 152 156 158 160 164 172 152 120 152 154 154 154 156 158 160 164 172 174 164 140 140 1 FIG. The components of memory systemdepicted inare electrical circuits. The memory controllerhas host interface, processor, ECC engine, memory interface, local memory controller, refresh logic, and wear level 174. The host interfaceis connected to and in communication with host. Host interfaceis also connected to a network-on-chip (NOC). A NOC is a communication subsystem on an integrated circuit. NOC's can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and the links of the NOC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, NOCcan be replaced by a bus. Connected to and in communication with NOCis processor, ECC engine, memory interface, local memory controller, refresh logic, and wear level. Local memory controlleris used to operate and communicate with local high speed memory(e.g., MRAM). In other embodiments, local high speed memorycan be DRAM, SRAM or another type of volatile memory.

158 158 140 104 158 158 158 158 156 140 104 ECC engineperforms error correction services. For example, ECC engineperforms data encoding and decoding of parity bits provided on or off the memory as part of the code word used for error correction of the data fetched from memoryor. In one embodiment, ECC engineis an electrical circuit programmed by software. For example, ECC enginecan be a processor that can be programmed. In other embodiments, ECC engineis a custom and dedicated hardware circuit without any software. In one embodiment, the function of ECC engineis implemented by processor. In one embodiment, local memoryhas an ECC engine with or without a wear level engine. In one embodiment, memoryhas an ECC engine with or without a wear level engine.

156 174 174 156 172 156 156 156 156 102 140 104 140 Processorperforms the various controller memory operations, such as programming, erasing, reading, and memory management processes including wear level. A separate wear levelis depicted, but the wear levelmay be implemented by processor. Also, refresh logicis depicted, but the refresh may also be implemented by the processor. In one embodiment, processoris programmed by firmware. In other embodiments, processoris a custom and dedicated hardware circuit without any software. Processoralso implements a translation module, as a software/firmware process or as a dedicated hardware circuit. In many systems, the non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory dies. To implement this system, memory controller(e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory die. One example implementation is to maintain tables (i.e., the L2P tables mentioned above) that identify the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word “tables” they need not literally be tables. Rather, the logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of a storage system is so large that the local memorycannot hold all of the L2P tables. In such a case, the entire set of L2P tables are stored in memoryand a subset of the L2P tables are cached (L2P cache) in the local high speed memory.

160 104 104 104 160 102 Memory interfacecommunicates with memory. In an embodiment, memorycontains programmable resistance memory cells in a cross-point array. In an embodiment, memorycontains NAND memory cells. In one embodiment, memory interface provides a Toggle Mode interface. Other interfaces can also be used. In some example implementations, memory interface(or another portion of controller) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory die.

140 140 140 140 In one embodiment, local memoryhas an ECC engine. Local memorymay be used to help perform other functions such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Pat. No. 10,545,692, titled “Memory Maintenance Operations During Refresh Window”, and U.S. Pat. No. 10,885,991, titled “Data Rewrite During Refresh Window”, both of which are hereby incorporated by reference in their entirety. In an embodiment, the local memoryis synchronous. In an embodiment, the local memoryis asynchronous.

104 102 102 104 In one embodiment, memorycomprises a plurality of memory packages. Each memory package includes one or more memory dies. Therefore, memory controlleris connected to one or more memory dies. In one embodiment, the memory package can include types of memory, such as storage class memory (SCM) based on programmable resistance random access memory (such as ReRAM, MRAM, FeRAM or RRAM) or a phase change memory (PCM). In one embodiment, memory controllerprovides access to memory cells in a cross-point array in a memory.

102 120 152 100 120 122 124 126 128 124 124 Memory controllercommunicates with host systemvia an interfacethat implements a protocol such as, for example, Compute Express Link (CXL). Or such controller can be eliminated and the memory packages can be placed directly on the host bus, DDRn or CXL for examples. For working with memory system, host systemincludes a host processor, host memory, and interfaceconnected along bus. Host memoryis the host's physical memory, and can be DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of storage. In an embodiment, host memorycontains a cross-point array of programmable resistance memory cells, with each memory cell comprising a programmable resistance memory element and a threshold switching selector in series with the programmable resistance memory element.

120 100 100 120 124 122 124 Host systemis external to and separate from memory system. In one embodiment, memory systemis embedded in host system. Host memorymay be referred to herein as a memory system. The combination of the host processorand host memorymay be referred to herein as a memory system. In an embodiment, such host memory can be cross-point memory using MRAM.

2 FIG. 292 292 140 292 104 292 124 292 202 202 202 292 220 208 202 220 260 222 224 226 220 220 228 202 292 210 206 202 202 210 260 212 214 216 is a block diagram that depicts one example of a memory diethat can implement the technology described herein. In one embodiment, memory dieis included in local memory, and in an embodiment memory dieis included in memory. In one embodiment, memory dieis included in host memory. Memory dieincludes a memory structurethat can include any of memory cells described in the following. The memory structuremay include one or more memory arrays. The array terminal lines of memory structureinclude the various layer(s) of word lines organized as rows, and the various layer(s) of bit lines organized as columns. However, other orientations can also be implemented, including for example diagonal patterns to save space. Memory dieincludes row control circuitry, whose outputsare connected to respective word lines of the memory structure. Row control circuitryreceives a group of M row address signals and one or more various control signals from System Control Logic circuit, and typically may include such circuits as row decoders, row drivers, and block select circuitryfor both reading and writing operations. Row control circuitrymay also include read/write circuitry. In an embodiment, row decode and control circuitryhas sense amplifiers, which each contain circuitry for sensing a condition (e.g., voltage) of a word line of the memory structure. In an embodiment, by sensing a word line voltage, a condition or bit state of a memory cell in a cross-point array is determined, either directly by a sense amp comparing the accessed memory cell voltage with a reference voltage. Or less directly by first accessing the memory cell and storing a read voltage generated by forcing a read current through the cell and adjusting it up or down by 150 mv (or half the voltage difference resulting from changing the bit state), then writing the cell to AP state, and again accessing the memory cell with a read current and comparing the resulting voltage with the stored voltage adjusted 150 mV for example (or half the difference in voltage resulting from two different bit states. Memory diealso includes column decode and control circuitrywhose input/outputsare connected to respective bit lines of the memory structure. Although only a single block is shown for memory structure, a memory die can include multiple arrays or “tiles” that can be individually accessed. Column control circuitryreceives a group of N column address signals and one or more various control signals from System Control Logic, and typically may include such circuits as column decoders, column decoders and drivers, block select circuitry, as well as read/write circuitry, and I/O multiplexers.

260 260 104 260 262 262 262 262 260 264 202 264 260 266 202 260 272 274 120 102 272 269 274 System control logicreceives data and commands from a host system and provides output data and status to the host system. In other embodiments, system control logicreceives data and commands from a separate controller circuit and provides output data to that controller circuit, with the controller circuit communicating with the host system. Such controller system may implement an interface such as DDR, DIMM, CXL, PCIe and others. In another embodiment those data and commands are sent and received directly from the memory packagesto the Host without a separate controller, and any controller needed is within each die or within a die added to a multi-chip memory package. In some embodiments, the system control logiccan include a state machinethat provides die-level control of memory operations. In one embodiment, the state machineis programmable by software. In other embodiments, the state machinedoes not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, the state machineis replaced by a micro-controller or microprocessor. The system control logiccan also include a power control modulethat controls the power, current source currents, and voltages supplied to the rows and columns of the memory structureduring memory operations and may include charge pumps and regulator circuit for creating regulating voltages, and on/off control of each for word line bit line selection of the memory cells. In some embodiments, the power controlincludes one or more current sources. The current source(s) may be used to provide read and/or write currents. System control logicincludes storage, which may be used to store parameters for operating the memory structure. System control logicalso includes refresh logicand wear leveling logic. Such system control logic may be commanded by the hostor memory controllerto refresh logic, which may load an on-chip stored row and column address (Pointer) which may be incremented after refresh. Such address bit(s) may be selected only (to refresh the OTS). Or such address may be read, corrected by steering through ECC engine, and then stored in a “spare” location, which is also being incremented (so all codewords are periodically read, corrected, and relocated in the entire chip under control of wear leveling logic) to in effect wear level so use of each bit across the chip is more uniform. Such operation may be more directly controlled by the host of an external controller, for example a PCIe or CXL or DDRn controller located separately from the memory chip or on the memory die.

102 292 268 268 102 268 268 228 258 102 268 102 Commands and data are transferred between memory controllerand the memory dievia memory controller interface(also referred to as a “communication interface”). Such interface may be PCIe, CXL, DDRn for example. Memory controller interfaceis an electrical interface for communicating with memory controller. Examples of memory controller interfacealso include a Toggle Mode Interface. Other I/O interfaces can also be used. For example, memory controller interfacemay implement a Toggle Mode Interface that connects to the Toggle Mode interfaces of memory interface/for memory controller. In one embodiment, memory controller interfaceincludes a set of input and/or output (I/O) pins that connect to the controller. In another embodiment, the interface is JEDEC standard DDRn or LPDDRn, such as DDR5 or LPDDR5, or a subset thereof with smaller page and/or relaxed timing.

260 269 269 269 202 269 269 269 269 269 System control logiclocated in a controller on the memory die in the memory packages may include Error Correction Code (ECC) engine. ECC enginemay be referred to as an on-die ECC engine, as it is on the same semiconductor die as the memory cells. That is, the on-die ECC enginemay be used to encode data and parity bits that are to be stored in the memory structure, and to decode the decoded data and correct errors. The encoded data may be referred to herein as a codeword or as an ECC codeword. ECC enginemay be used to perform a decoding algorithm and to perform error correction. Hence, the ECC enginemay decode the ECC codeword. In an embodiment, the ECC engineis able to decode the data more rapidly by direct decoding without iteration. Having the ECC engineon the same die as the memory cells allows for faster decoding. The ECC enginecan use a wide variety of decoding algorithms including, but not limited to, Reed Solomon, a Bose-Chaudhuri-Hocquenghem (BCH), and low-density parity check (LDPC).

292 260 260 In some embodiments, all of the elements of memory die, including the system control logic, can be formed as part of a single die. In other embodiments, some or all of the system control logiccan be formed on a different die; e.g., external controller chip.

202 202 In one embodiment, memory structurecomprises a three-dimensional memory array of non-volatile or volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile or volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon or silicon on insulator (or other type of) substrate. In another embodiment, memory structurecomprises a two-dimensional memory array of non-volatile memory cells.

202 202 202 202 The exact type of memory array architecture or memory cell included in memory structureis not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure. No particular non-volatile memory technology is required for purposes of the newly claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structureinclude ReRAM memories (resistive random access memories), magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structureinclude two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.

One example of a ReRAM or MRAM cross-point memory includes programmable resistance switching elements in series with an OTS selector arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment of cross-point is PCM in series with and OTS selector. In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.

Magnetoresistive random access memory (MRAM) stores data using magnetic storage elements. The elements are formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. For a field-controlled MRAM, one of the two layers is a permanent magnet set to a particular polarity; the other layer's magnetization can be changed by applying an external field to store memory. Other types of MRAM cells are possible. A memory device may be built from a grid of MRAM cells or as SOT magneto resistive memory. MRAM based memory embodiments will be discussed in more detail below.

Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). The memory cells are programmed by current pulses that can change the co-ordination of the PCM material or switch it between amorphous and crystalline states. Note that the use of “pulse” in this document does not require a square pulse but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage, light, or other wave. And the current forced for a write can, for example, be driven rapidly to a peak value and then linearly ramped lower with, for example, a 500 ns edge rate. Such peak current force may be limited by a zoned voltage compliance that varies by position of the memory cell along the word line or bit line. In an embodiment, a phase change memory cell has a phase change memory element in series with a threshold switching selector such as an OTS.

A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, memory construction or material composition, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

2 FIG. 202 292 202 260 292 202 The elements ofcan be grouped into two parts, the memory structureand the peripheral circuitry, including all of the other elements. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of the memory diethat is given over to the memory structure; however, this reduces the area of the memory die available for the peripheral circuitry or increases cost which is related to chip area. This can place quite severe restrictions on these peripheral elements. For example, the need to fit sense amplifier circuits within the available area can be a significant restriction on sense amplifier design architectures. With respect to the system control logic, reduced availability of area can limit the available functionalities that can be implemented on-chip. Consequently, a basic trade-off in the design of a memory dieis the amount of area to devote to the memory structureand the amount of area to devote to the peripheral circuitry. Such tradeoffs may result in more IR drop from use of larger x-y arrays of memory between driving circuits on the word line and bit line, which in turn may benefit more from use of voltage limit and zoning of the voltage compliance by memory cell position along the word line and bit line.

202 260 Another area in which the memory structureand the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, elements such as sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logicoften employ PMOS devices. In some cases, the memory structure will be based on CMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for NMOS-only technologies.

2 FIG. 3 FIG. 270 280 290 202 280 290 280 To improve upon these limitations, embodiments described below can separate the elements ofonto separately formed die that are then bonded together.depicts an integrated memory assemblyhaving a memory structure dieand a control die. The memory structureis formed on the memory structure dieand some or all of the peripheral circuitry elements, including one or more control circuits, are formed on the control die. For example, a memory structure diecan be formed of just the memory elements, such as the array of memory cells of MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all of the peripheral circuitry, even including elements such as decoders, current sources, and sense amplifiers, can then be moved to the control die. This allows each of the semiconductor die to be optimized individually according to its technology. This allows more space for the peripheral elements, which can now incorporate additional capabilities that could not be readily incorporated were they restricted to the margins of the same die holding the memory cell array. The two die can then be bonded together in a bonded multi-die integrated memory assembly, with the array on the one die connected to the periphery elements on the other die. Although the following will focus on an integrated memory assembly of one memory die and one control die, other embodiments can use additional die, such as two memory die and one control die, for example.

292 280 202 260 220 210 290 210 220 280 260 280 2 FIG. 3 FIG. As with memory dieof, the memory structure dieinincludes a memory structurethat can include multiple independently accessible arrays or “tiles.” System control logic, row control circuitry, and column control circuitryare located in control die. In some embodiments, all or a portion of the column control circuitryand all or a portion of the row control circuitryare located on the memory structure die. In some embodiments, some of the circuitry in the system control logicis located on the on the memory structure die.

3 FIG. 210 290 202 280 293 293 212 214 216 202 210 290 290 280 202 202 293 210 220 222 224 226 228 202 294 294 290 280 shows column control circuitryon the control diecoupled to memory structureon the memory structure diethrough electrical paths. For example, electrical pathsmay provide electrical connection between column decoder, column driver circuitry, and block selectand bit lines of memory structure. Electrical paths may extend from column control circuitryin control diethrough pads on control diethat are bonded to corresponding pads of the memory structure die, which are connected to bit lines of memory structure. Each bit line of memory structuremay have a corresponding electrical path in electrical paths, including a pair of bond pads, which connects to column control circuitry. Similarly, row control circuitry, including row decoder, row drivers, block select, and sense amplifiersare coupled to memory structurethrough electrical paths. Each of electrical pathmay correspond to, for example, a word line. Additional electrical paths may also be provided between control dieand memory structure die.

102 164 156 260 210 220 122 For purposes of this document, the phrase “a control circuit” can include one or more of memory controller, local memory controller, processor, system control logic, column control circuitry, row control circuitry, host processor, a micro-controller, a state machine, and/or other control circuitry, or other analogous circuits that are used to control non-volatile memory. The control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FPGA, ASIC, integrated circuit, or other type of circuit. Such control circuitry may include drivers such as direct drive via connection of a node through fully on transistors (gate to the power supply) driving to a fixed voltage such as a power supply. Such control circuitry may include a current source driver.

100 140 164 102 140 104 292 270 290 For purposes of this document, the term “apparatus” can include, but is not limited to, one or more of memory system, local memory, the combination of local memory controllerand/or memory controllerand local memory, memory, memory die, integrated memory assembly, and/or control die.

202 2 3 FIGS.and In the following discussion, the memory structureofwill be discussed in the context of a cross-point architecture. In a cross-point architecture, a first set of conductive lines or wires, such as word lines, run in a first direction relative to the underlying substrate and a second set of conductive lines or wires, such a bit lines, run in a second direction relative to the underlying substrate. The memory cells are sited at the intersection of the word lines and bit lines. The memory cells at these cross-points can be formed according to any of a number of technologies, including those described above. The following discussion will mainly focus on embodiments based on a cross-point architecture using MRAM memory cells, each in series with a threshold switching selector such as Ovonic Threshold Switch (OTS) to comprise a selectable memory bit. However, embodiments are not limited to providing currents to a cross-point architecture having MRAM cells, each with magnetic memory element in a series OTS selector. For example, the cross-point memory array may have memory cell of other technologies such as ReRam, PCM (Phase Change Memory), or FeRam.

4 FIG.A 4 FIG.A 2 3 FIG.orB 4 FIG.A 4 FIG.D 402 402 202 292 280 402 402 140 124 401 1 5 1 5 1 5 1 5 cell depicts one embodiment of a portion of a memory arraythat forms a cross-point architecture in an oblique view. Memory arrayofis one example of an implementation for memory structurein, where a memory dieor memory structure diecan include multiple such memory arrays. The memory arraymay be included in local memoryor host memory. The bit lines BL-BLare arranged in a first direction (represented as running into the page) relative to an underlying substrate (not shown) of the die and the word lines WL-WLare arranged in a second direction perpendicular to the first direction, or diagonal to provide intersections where memory cells are interconnected between WLs and BLs.is an example of a horizontal cross-point structure in which word lines WL-WLand BL-BLboth run in a horizontal direction relative to the substrate, while the memory cells, two of which are indicated at, are oriented so that the current through a memory cell (such as shown at I) runs in the vertical direction. In a memory array with additional layers of memory cells, such as discussed below with respect to, there would be corresponding additional layers of bit lines and word lines. One pattern, for example, would be from the bottom layer: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL memory cell, WL.

4 FIG.A 402 401 401 401 401 401 cell As depicted in, memory arrayincludes a plurality of memory cells. The memory cellsmay include re-writeable memory elements, such as can be implemented using ReRAM, MRAM, PCM, or other material with a programmable resistance. The memory cellsmay be referred to herein as programmable resistance memory cells. One type of programmable resistance memory cell is referred to as an MRAM cell, which is a memory cell that includes a MRAM memory element. The memory cellsmay also include threshold switching selectors as an additional series element within the memory cells, such as can be implemented using an Ovonic Threshold Switch (OTS), Volatile Conductive Bridge (VCB), Metal-Insulator-Metal (MIM), or other material that provides a highly non-linear dependence of current or resistance for varying select voltage. The following discussion will focus on memory cells composed of an MRAM memory elements combined in series with an Ovonic Threshold switch elements, although much of the discussion can be applied more generally. The current in the memory cells of the first memory level is shown as flowing upward as indicated by arrow I, but current can flow in either direction to either read or write the memory cell bit state, as is discussed in more detail in the following.

4 4 FIGS.B andC 4 FIG.A 4 FIG.B 4 FIG.C 1 1 n 1 M 1 N 401 respectively present side and top views of the cross-point structure in. The sideview ofshows one bottom wire, or word line, WLand the top wires, or bit lines, BL-BL. At the cross-point between each top wire and bottom wire is an MRAM memory cell, although PCM, ReRAM, FeRAM, or other technologies can be used as the memory element.is a top view illustrating the cross-point structure for M bottom wires WL-WLand N top wires BL-BL. In a binary embodiment, the MRAM cell at each cross-point can be programmed into one of two resistance states: high and low. More detail on embodiments for an MRAM memory cell design and techniques for their reading are given below. In some embodiments, sets of these wires are arrayed continuously as a “tile,” and such tiles may be paired adjacently in the Word Line (WL) direction and orthogonally in the Bit Line direction to create a module. Such a module may be composed of 2×2 tiles to form a four tile combination wherein the WL drivers between the tiles is “center driven” between the tiles with the WL running continuously over the transistor driver at the approximate center of the line. Similarly, BL drivers may be located between the pair of tiles paired in the BL direction to be center driven, whereby the transistor driver and its area is shared between a pair of tiles. Vias of copper or other types of low resistance may decode and connect the transistor driver/selects to the WL or BL. In addition to the memory element in the memory cell between WL and BL may also be included a series select element such as an OTS.

4 FIG.A 4 FIG.D The cross-point array ofillustrates an embodiment with one layer of word lines and bits lines, with the MRAM or other memory technology for the memory cells sited at the intersection of the two sets of conducting lines. To increase the storage density of a memory die, multiple layers of such memory cells and conductive lines can be formed. A two-layer example is illustrated in.

4 FIG.D 4 FIG.A 4 FIG.D 2 3 FIG.orB 4 FIG.D 4 FIG.D 418 401 403 403 202 420 418 420 1.1 1.4 1 5 1 5 2.1 2.4 nd depicts an embodiment of a portion of a two-level memory array that forms a cross-point architecture in an oblique view. As in,shows a first layerof memory cellsof a memory arrayconnected at the cross-points of the first layer of word lines WL-WLand bit lines BL-BLabove. Memory arraymay be included in memory structureof. A second layerof memory cells is formed above the bit lines BL-BLand between these bit lines and a second set of word lines WL-WL. In effect the BLs are shared. In the alternative a second layer may include another deck of BL above the BL shown and below the 2deck of WL. Althoughshows two layers,and, of memory cells, the structure can be extended upward through additional alternating layers of word lines and bit lines in a similar pattern. Depending on the embodiment, the word lines and bit lines of the array ofcan be biased for read or program operations such that current in each layer flows from the word line layer to the bit line layer or the other way around. The two layers can be structured to have current flow in the same direction in each layer for a given operation or to have current flow in the opposite directions by driver selection in the positive or negative direction. The memory cell may be placed in the same orientation within the first and second layers enabling use of current in oppositive directions by layer to read or write. Or the memory cell placed in a reversed or flipped direction when placed between the BL and WL in the second layer (enabling use of current in the same direction as is used to read or write in memory cells within the first layer. As will be apparent to someone reasonably skilled in the art, the 2 layers can be extended to 3 or more layers.

292 140 124 2 FIG. 1 FIG. 1 FIG. The use of a cross-point architecture allows for arrays with a small footprint and several such arrays can be formed on a single die. The memory cells formed at each cross-point can be a resistive type of memory cell, where data values are encoded as different resistance levels, either two levels such as with MRAM or into two or more levels for other memory element technologies such as PCM. Depending on the embodiment, the memory cells can be binary valued, having either a low resistance state or a high resistance state, or multi-level cells (MLCs) that can have additional resistance intermediate to the low resistance state and high resistance state. The cross-point arrays described here can be used in the memory dieof, the local memoryin, and/or the host memoryin, or in any other configuration where additional memory is useful. Resistive type memory cells can be formed according to many of the technologies mentioned above, such as ReRAM, PCM, FeRAM, or MRAM. The following discussion is presented mainly in the context of memory arrays using a cross-point architecture with binary valued MRAM memory cells, although much of the discussion is more generally applicable to other memory elements in memory cells within a cross-point array or other configurations apparent to those reasonably skilled in the art.

5 FIG. 4 4 FIGS.A-D 401 501 512 502 514 503 507 505 511 507 509 509 507 509 503 507 503 505 507 505 502 507 511 illustrates the structure of an embodiment for an MRAM cell. The MRAM cell may be used as the programmable resistance memory cellin, for example,. The MRAM cell includes a bottom electrode, spacer, a threshold switching selector, spacer, a pair of magnetic layers (reference layerand free layer) separated by a separation or tunneling layer of, in this example, magnesium oxide (MgO), and then a top electrodeseparated from the free layerby a spacer. The spacercan consist of an MgO capping layer in contact with the free layer. The spacercan also contain additional metal layers. In another embodiment, the locations of the reference layerand free layerare switched, with the reference layeron top of MgO, and the free layerbelow MgO. In another embodiment, the location of the threshold switching selectoris between the free layerand the top electrode.

501 511 501 511 503 507 503 503 503 5 FIG. In some embodiments, the bottom electrodeis a word line and the top electrodeis a bit line. In other embodiments, the bottom electrodeis a bit line and the top electrodeis a word line. The state of the memory cell is based on the relative orientation of the magnetizations of the reference layerand the free layer: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have the opposite orientation, the memory cell will be in an anti-parallel (AP) high resistance state (HRS). An MLC embodiment would include additional intermediate states. The orientation of the reference layeris fixed and, in the example of, is oriented upward. Reference layeris also known as a fixed layer or pinned layer. The reference layercan be composed of multiple ferromagnetic layers coupled anti-ferromagnetically in a structure commonly referred to a synthetic anti-ferromagnet or SAF for short.

507 503 507 503 503 507 503 Data is written to an MRAM memory cell by programming the free layerto either have the same orientation or opposite orientation relative to the reference layer. An array of MRAM memory cells may be placed in an initial, or erased, state by setting all of the MRAM memory cells to be in the low resistance state in which all of their free layers have a magnetic field orientation that is the same as their reference layers. Each of the memory cells is then selectively programmed (also referred to as “written”) by placing its free layerto be in the high resistance state by reversing the magnetic field to be opposite that of the reference layer. The reference layeris formed so that it will maintain its orientation when programming the free layer. The reference layercan have a more complicated design that includes synthetic anti-ferromagnetic layers and additional reference layers. For simplicity, the figures and discussion omit these additional layers and focus only on the fixed magnetic layer primarily responsible for tunneling magnetoresistance in the cell.

502 502 503 514 502 503 514 503 502 501 512 502 503 512 501 The threshold switching selectorhas a high resistance (in an off or non-conductive state) until it is biased to a voltage higher than its threshold voltage or current above its threshold current, and until its voltage bias falls below Vhold (also known as “Voffset”) or current below Ihold. After Vt is exceeded and while Vhold is exceeded across the switching selector, the switching selector has a low resistance (in an on or conductive state). The threshold switching selector remains on until its current is lowered below a holding current Ihold, or the voltage is lowered below a holding voltage, Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. Accordingly, to program a memory cell at a cross-point, a voltage or current is applied which is sufficient to turn on the associated threshold switching selector and set or reset the memory cell; and to read a memory cell, the threshold switching selector similarly is activated by being turned on before the resistance state of the memory cell is determined. One set of examples for a threshold switching selector is an ovonic threshold switching material of an Ovonic Threshold Switch (OTS). Example threshold switching materials include Ge—Se, Ge—Se—N, Ge—Se—As, Ge—Se—Sb—N, Ge58Se42, GeTe6, Si—Te, Zn—Te, C—Te, B—Te, Ge—As—Te—Si—N, Ge—As—Se—Te—Si and Ge—Se—As—Te, with atomic percentages ranging from a few percent to more than 90 percent for each element. In an embodiment, the threshold switching selector is a two terminal device. The threshold switching selectorcan also contain additional conducting layers on the interface with the reference layer. For example, spaceris depicted between switching selectorand reference layer. The spacer layeron the interface with reference layercan be a single conducting layer or composed of multiple conducting layers. The threshold switching selectorcan also contain additional conducting layers on the interface with the bottom electrode. For example, spaceris depicted between switching selectorand reference layer. The spacer layeron the interface with bottom electrodecan be a single conducting layer or composed of multiple conducting layers. Examples of conducting layers adjacent to the OTS include carbon, carbon nitride, carbon silicide, carbon tungsten, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, and others. Threshold voltage switches have a Threshold Voltage (Vt) above which the resistance of the device changes substantially from insulating, or quasi insulating, to conducting.

read write select read write 501 224 501 214 501 511 2 In an embodiment, a current-force approach is used to access the MRAM cell. The current-force approach may be used to read or write the MRAM cell. In the current-force approach, an access current (e.g., Ior I) is driven through the bottom electrodeby a current driver. The current will be provided by a transistor or resistor based current source. In an embodiment, the current driver may be a part of the address selected row driver circuitry (e.g., array drivers) for the electrode. However, alternatively the current driver may be a part of the address selected column driver circuitry (e.g., driver circuitry) for the electrode. A voltage (e.g., V) is provided to the top electrode. Herein, the terms “read current” (I) and “write current” (I) will be used in connection with access currents that are driven through MRAM cells (or other programmable resistance cells). The write current may change the state of the MRAM cell. As an example, a write current of about 30 μA for 50 ns may be used for an MRAM cell with a Critical Dimension (CD) of approximately 20 nanometers with RA 10 Ωμmto switch the MRAM state from the P-state to the AP-state. Read currents may be about half the write current if applied for a limited time, such as <20 ns. A write current that flows in one direction through the MRAM cell will change an AP-state MRAM cell to the P-state. A write current that flows in the other direction, such as in the read direction, through the MRAM cell will change a P-state MRAM cell from the P-state to the AP-state. In general until the cell state is determined or a voltage level is captured and stored that correlates to the memory cell state, a read current will preferably be set low enough and the read duration short enough so as not to change the state of an MRAM cell from the P-state to the AP-state or from the AP-state to the P-state during read. Typically the write current required to switch the MRAM state from the P-state to the AP-state is larger in absolute magnitude than the write current required to switch the MRAM state from the AP-state to the P-state, so this may be a preferred direction to read for offering my margin against a state change before the bit state is correctly sensed. Current magnitudes may be adjusted accordingly by write direction, or the current used for P to AP if a single magnitude is used.

1 1 2 In some embodiments, a read current may be applied in a P2AP direction or, alternatively, in an AP2P direction. In some embodiments, the MRAM cell is read by performing an SRR (self-referenced-read). In one embodiment, the SRR has a first read (Readin the P2AP direction), a first write (Writeto the AP-state), and a second read (Readin the P2AP direction). Then the original state of the cell may be restored by a second write (Write_Back to the P-state for bits initially in the P-state). Or in another embodiment, the SRR read current and destructive write currents are both reversed, for example, when addressing the second layer with a memory cell oriented the same as in the first layer.

1 2 In an embodiment, the voltage level of the memory cell due to Readin the P2AP direction is sensed and stored, for example on a capacitor; or by conversion to digital bits by an Analog to Digital converter and the bits stored in memory, for example in SRAM until after use in Read. The state stored on a capacitor can be adjusted, for example, 150 mv positive or negative by forcing a voltage on one terminal of a capacitor connected to the storage capacitor. Or the digital stored level can be adjusted by digitally adding or subtracting 150m V to the stored bits. The 150 mV can be adjusted to be dependent on the typical bit resistance. For example, if the bit low resistance state is 25K ohms and the high resistance 50K ohms, the difference is 25K ohms. If the read current is 15 μA, the difference voltage between the states if 25 Kohms×15 μA=375 mV, making a choice of 150m V acceptable but perhaps suggesting 187.5 mV may be more optimum, for example.

1 1 2 Although the foregoing describes reads in the P2AP direction and destructive writes to the AP-state (with write back after SRR to the P-state), in an alternative embodiment the first SRR has a first read (Readin the AP2P direction), a destructive write (Write) to the P-state and a second read (Read) in the AP2P direction.

511 501 501 511 1 2 511 501 511 501 511 501 501 511 In one embodiment, the MRAM cell is read by applying, for example, approximately 0V to the top electrodeby turning on a transistor connected between 511 and a power supply, while driving a current of, for example, 15 micro-Amperes (μA) through the bottom electrode. This read current may flow from the bottom electrodeto the top electrode. Note that the read may be Reador Readin the P2AP direction. P2AP means current flows in the direction that would write the bit from P to AP or AP to AP. In some embodiments, data is written to the MRAM cell using a bipolar write operation. In one embodiment, the MRAM cell is written from the AP-state to the P-state by applying, for example, 3V to the top electrode, while driving a write current of, for example, −30 μA through the bottom electrode. This write current will flow from the top electrodeto the bottom electrode. In one embodiment, the MRAM cell is written from the P-state to the AP-state by applying, for example, 0V to the top electrode, while driving a current of, for example, 30 μA through the bottom electrode. This write current will flow from electrodeto the electrode.

5 FIG. 501 511 501 511 501 511 As an alternative to the approach in, the select voltage can be applied to the bottom electrodewith the access current applied through the top electrode. In one such embodiment, the MRAM cell is read by applying, for example, 3V to the bottom electrode, while driving a read current of, for example, −15 μA through the top electrode. This read current may flow from the bottom electrodeto the top electrode.

501 511 501 511 501 511 511 501 In one embodiment, the MRAM cell is written from the AP-state to the P-state by applying, for example, −3V to the bottom electrode, while driving a write current of, for example, 30 μA through the top electrode. The electron current will flow from the bottom electrodeto the top electrode. In one embodiment, the MRAM cell is written from the P-state to the AP-state by applying, for example, 0V to the bottom electrode, while driving a current of, for example, −30 μA through the top electrode. The electron current will flow from the top electrodeto the bottom electrode. The direction of the current polarity to switch the magnetization of the bit into the P or AP state can vary based on reference layer design and the location of the reference layer with respect to the free layer.

4 4 FIGS.A-D 401 502 Some biasing techniques may result in voltage across non-selected memory cells of the array, which can induce “leakage” currents in non-selected memory cells. Although this wasted power consumption can be mitigated to some degree by designing the memory cells to have relatively high resistance levels for both high and low resistance states when WL or BL is address unselected, this overhead leakage will still result in increased current and power consumption as well as placing additional design constraints on the design of the memory cells and the array due to lack of read and write margin. One approach to address this unwanted current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. For example, a select transistor can be placed in series with each resistive memory cell element inso that the memory cellsis now a composite of a select transistor and a programmable resistance. Such an architecture may be referred to as 1T1R. Use of a select transistor, however, requires the introduction of additional control lines and cell area to be able to turn on the corresponding transistor of a selected memory cell. Additionally, transistors will often not scale in the same manner as the resistive memory element write current, so that as memory arrays move to smaller sizes the use of transistor based selectors can be a limiting factor in reducing cost, for example. An alternate approach to select transistors is the use of a threshold switching selector (e.g., threshold switching selector) in series with the programmable resistive element. A two terminal threshold switching selector does not require the aforementioned additional control lines and additional cell area to be able to turn on the corresponding select transistor of a selected memory cell. In some embodiments, the memory system performs a read as disclosed herein to read memory cells having a two terminal threshold switching selector in series with a programmable resistance memory element.

6 6 FIGS.A andB 6 6 FIGS.A andB 4 FIG.D 6 FIG.A 6 6 FIGS.A andB 4 FIG.D 5 FIG. 600 620 610 illustrate embodiments for the incorporation of threshold switching selectors into an MRAM memory array having a cross-point architecture. The examples ofshow two MRAM cells (Layer 1 Cell, Layer 2 Cell) in a two layer cross-point array, such as shown in, but in a side view. Keeping the orientation of the MRAM layers the same in the Layer 1 Cell and the Layer 2 Cell, as depicted in, allows the fabrication process to be the same for each layer. Whereas 6B has the memory cell inverted which allows the drive circuitry to work the same; e.g., BL goes Low to Read P2AP for each layer.show a lower first conducting line of word line 1, an upper first conducting line of word line 2, and an intermediate second conducting line of bit line. In these figures, all of these lines are shown running left to right across the page for ease of presentation, but in a cross-point array they would be more accurately represented as in the oblique view ofwhere the word lines, or first conducting lines or wires, run in one direction parallel to the surface of the underlying substrate and the bit lines, or second conducting lines or wires, run in a second direction parallel to the surface to the substrate that is largely orthogonal to the first direction. The MRAM memory cells are also represented in a simplified form, showing only the reference layer, free layer, and the intermediate tunnel barrier, but in an actual implementation would typically include the additional structure described above with respect to.

602 601 603 605 609 602 609 610 600 602 609 609 609 609 609 th An MRAM elementincluding free layer, tunnel barrier, and reference layeris formed above the threshold switching selector, where this series combination of the MRAM elementand the threshold switching selectortogether form the layer 1 cell between the bit lineand word line 1. The series combination of the MRAM elementand the threshold switching selectoroperate largely as described above when the threshold switching selectoris turned on. Initially, though, the threshold switching selectorneeds to be turned on by applying a voltage above the threshold voltage Vof the threshold switching selector, and then the biasing current or voltage needs to be maintained high enough above the holding current or holding voltage of the threshold switching selectorso that it stays on during the subsequent read or write operation.

612 611 613 615 619 612 619 610 620 610 620 2 1 1 On the second layer, an MRAM elementincludes free layer, tunnel barrier, and reference layeris formed above the threshold switching selector, with the series combination of the MRAM elementand the threshold switching selectortogether forming the layer 2 cell between the bit lineand word line 2. The layer 2 cell will operate as for the layer 1 cell, although the lower conductor now corresponds to a bit lineand the upper conductor is now a word line, word line 2. Additional paired layers may similarly share another bit line between them, having a pattern of WL1, BL1, WL2; WL3, BL, WL4; or have separate bit lines in a pattern such as WL, BL, WL2, BL2. Or separate bit lines in a pattern of WL1, BL1, BL2, WL2.

6 FIG.A 6 FIG.A 609 619 602 612 602 612 601 611 605 615 In the embodiment of, the threshold switching selector/is formed below the MRAM element/, but in alternate embodiments the threshold switching selector can be formed above the MRAM element for one or both layers. The MRAM memory cell is directional. In, the MRAM elementsandhave the same orientation, with the free layer/above (relative to the unshown substrate) the reference layer/. Forming the layers between the conductive lines with the same structure can have a number of advantages, particularly with respect to processing as each of the two layers, as well as subsequent layers in embodiments with more layers, can be formed according to the same processing sequence.

6 FIG.B 6 FIG.A 6 FIG.A 6 FIG.B 6 FIG.A 650 660 1 1 651 653 655 652 659 662 669 660 670 662 661 663 665 663 662 652 illustrates an alternate embodiment that is arranged similarly to that of, except that in the layer 2 cell the locations of the reference layer and free layer are reversed. More specifically, between word line 1and bit line, as inthe layer cellincludes an MRAM elementhaving a free layerformed over tunnel barrier, that is turn formed over the reference layer, with the MRAM elementformed over the threshold switching selector. The second layer of the embodiment ofagain has an MRAM elementformed over a threshold switching selectorbetween the bit lineand word line 2, but, relative to, with the MRAM elementinverted, having the reference layernow formed above the tunnel barrierand the free layernow under the tunnel barrier. Alternatively, the configuration of MRAM elementmay be used for the Layer 1 cell and the configuration of MRAM cellmay be used for the Layer 2 cell.

6 FIG.B 6 FIG.B 660 660 650 670 660 650 670 Although the embodiment ofrequires a different processing sequence for the forming of layers, in some embodiments it can have advantages. In particular, the directionality of the MRAM structure can make the embodiment ofattractive since when writing or reading in the same direction (with respect to the reference and free layers) the bit line will be biased the same for both the lower layer and the upper layer, and both word lines will be biased the same. For example, if both layer 1 and layer 2 memory cells are sensed in the P2AP direction (with respect to the reference and free layers), the bit line layerwill be biased such as in the P2AP direction, the bit lineis biased low (e.g., 0V) for both the upper and lower cell, with word line 1and word line 2both biased to a higher voltage level. Similarly, with respect to writing, for writing to the high resistance AP state the bit lineis biased low (e.g., 0V) for both the upper and lower cell, with word line 1and word line 2both biased to a higher voltage level.

To either read data from or write data to an MRAM memory cell involves passing a current through the memory cell. In embodiments where a threshold switching selector is placed in series with the MRAM element, before the current can pass through the MRAM element the threshold switching selector may be turned on by applying a sufficient voltage across and current through the series combination of the threshold switching selector and the MRAM element.

7 FIG. 2 3 FIG.orB 700 700 202 700 706 706 708 708 706 706 708 708 706 706 708 708 706 706 708 708 a h a d a h a b a h a b a h a b depicts an embodiment of a memory arrayhaving a cross-point architecture. The memory arraymay be included in memory structureof. The arrayhas a set of first conductive lines-and a set of second conductive lines-. In one embodiment, the set of first conductive lines-are word lines and the set of second conductive lines-are bit lines. For ease of discussion, the set of first conductive lines-may be referred to as word lines and the set of second conductive lines-may be referred to as bit lines. However, the set of first conductive lines-could be bit lines and the set of second conductive lines-could be word lines.

700 401 401 706 708 706 708 401 502 502 502 502 502 The memory arrayhas a number of programmable resistance memory cells. Each memory cellis connected between one of the first conductive linesand one of the second conductive lines(e.g., at the cross point of one of the first conductive linesand one of the second conductive lines). In one embodiment, each memory cellhas a magnetoresistive random access memory (MRAM) element in series with a threshold switching selector. The threshold switching selectoris configured to become conductive with lower resistance in response to application of a voltage level exceeding a threshold voltage of the threshold switching selector, and remains conductive with lower resistance until the current through the switching selectoris reduced below the selector holding current, Ihold. The threshold switching selectormay be a two terminal device. In an embodiment, the threshold switching selectorcomprises an OTS.

401 401 706 708 401 708 706 a a g b b g select_BL access For purpose of discussion, memory cellis being selected for access. This could be a read or a write access. Selected memory cellis at the cross-point of selected word lineand selected bit line. A selected memory cell means a memory cell that is selected for a memory operation such as a read or write. A selected memory cell is connected between a selected word line and a selected bit line. To select a memory cell, a select voltage (V) such as near ground is provided to the selected bit line (e.g., bit line) and an access current (I) is driven (or forced) to a selected word line (e.g., word line). A selected word line means that the word line is connected to at least one selected memory cell. The selected word line will typically be connected to one or more unselected memory cells. A selected bit line means that the bit line is connected to at least one selected memory cell. The selected bit line will typically be connected to one or more unselected memory cells.

select access select unsel_BL unsel_BL access 502 502 706 401 708 30 g a b u In one embodiment, VBI, has an adequate magnitude such that the threshold switching selectorin a selected memory cell will turn on, assuming that Iis applied to the selected word line with adequate compliance voltage relative to the BL voltage. For example, VBI, may be approximately 0V. On the other hand, V, has a magnitude such that the threshold switching selectorin an unselected memory cell will not turn on, for example Vmay be approximately 1.65V if the positive power supply is 3.3V. Access current (I) is driven through at least a portion of selected word lineafter the OTS is turned on. This access current may also flow through the selected memory celland in a portion of selected bit lineafter the OTS is turned on. Such a selected WL may, for example, be driven high by 15 μA to read orA to write by a current source with compliance voltage of, for example, 3.3V. To write the opposite polarity, the selected word line is forced, for example, with −30 μA and the selected bit line to near 3.3V.

unsel_BL unsel_WL access 708 708 708 710 710 710 710 710 710 710 706 706 706 706 706 706 706 a c d a b c d e f h a b c d e f h The other memory cells are not selected for access (i.e., are unselected memory cells). An unselected memory cell means that the memory cell is not presently selected for access (e.g., read or write). An unselected word line is connected only to unselected memory cells. An unselected bit line is connected only to unselected memory cells. Word lines and bit lines that are not selected are referred to as unselected word lines or unselected bit lines, respectively. In one embodiment, a word line or bit line may be unselected by forcing them to an unselect voltage, such as Vmid, for example 1.65V, at approximately one half the drive compliance voltage; e.g., 3.3V. An unselect voltage (V) is provided to the unselected bit lines (e.g., bit lines,,). An unselect voltage (V) such as Vmid is provided to the unselected word lines (e.g., word lines,,,,,, and). Icould flow in either direction through the selected word line (as well as the selected bit line). In one embodiment, no current other than leakage is forced through unselected word lines (e.g.,,,,,,, and).

7 FIG. 7 FIG. In the example ofthere are more word lines than bit lines in the cross-point array. In another embodiment, there are more bit lines than word lines in the cross-point array. In another embodiment, the number of bit lines equals the number of word lines in the cross-point array. In the example ofthere are twice as many word lines as bit lines in the cross-point array; however, a different ratio could be used. Thereby, different tile sizes may be realized. For example, a tile may have 1024 BL by 2048 WL, which may be composed into a module of 2048×4096 cells by center driving the WL and BL between the four tiles. In one embodiment, read is performed on a group of memory cell by, for example, selecting one memory cell in each of a number of tiles. In some embodiments, more than one memory cell from a tile may be selected for a read.

In some embodiments, a current-force approach is used to access memory cells in a cross-point memory array. A threshold switching selector may be used in series with the programmable resistance memory element. The threshold switching selector may be connected in series with the programmable resistance memory element between the word line and the bit line. Hence, any voltage across the threshold switching selector will reduce the voltage across the programmable resistance memory element. Typically, there will be some variation in the offset or hold voltage between the threshold switching selectors. A current-force approach may help to mitigate offset voltage variation between threshold switching selectors or memory element voltage from critical dimension (CD) variation to help minimize the selected cell current variation cell to cell.

8 FIG. 2 3 FIG.or 8 FIG. 802 804 806 802 804 806 220 220 228 401 401 702 502 401 702 502 502 502 select select select is a diagram of one embodiment of a system for reading a memory cell having a threshold switching selector in series with a programmable resistance memory element. The system has a current generation and delivery circuitry, capacitive isolation circuitry, and discharge circuitry. In an embodiment, the current generation and delivery circuitry, capacitive isolation circuitry, and discharge circuitryare part of the row control circuitry(see). The row control circuitrymay also include sense amplifiers, but the sense amplifier is not depicted in. One memory cellof the many memory cells in a cross-point array is depicted. The memory cellhas a programmable resistance memory elementin series with a threshold switching selector. In one embodiment, the memory cellis an MRAM cell in which the programmable resistance memory elementis a magnetoresistance memory element and the threshold switching selectoris an OTS. However, the memory cell could be a PCM cell, a ReRam cell, an FeRam cell, etc. The threshold switching selectoris not required to be an OTS. The threshold switching selectorcould instead be a Volatile Conductive Bridge (VCB), Metal-Insulator-Metal (MIM), or other material that provides a highly non-linear dependence of current on select voltage. The voltage Von the bit line (BL) is a voltage having a suitable magnitude to select the memory cell. In one embodiment, Vto the bit line is near 3.3V. In another embodiment, Vto the bit line is near 0V.

802 802 802 8 FIG. 8 FIG. read read read read The current generation and delivery circuitrycontains a number of current sources, current drivers, and associated electrical lines. The current sources may include read current sources and write current sources.shows an example in which one of a read current Iis driven to the word line (WL). In an embodiment, there is a fixed magnitude read current source of 15 μA, a fixed magnitude read current source of −15 μA, a fixed magnitude write current source of 30 μA, and a fixed magnitude write current source of −30 μA. The current generation and delivery circuitrycontains a number of current drivers and other transistors to provide the pertinent current to the selected word line. The read current Icould have a positive magnitude or negative magnitude with reference to the direction of the current arrow below Iin. Thus, the term “current source” will be used herein regardless of the direction of current flow at the output of the current source. The terms “sourcing a current” and “sinking a current” are sometimes used by those of ordinary skill in the art to differentiate between the direction of current flow. The current generation and delivery circuitrymay “source” a current or “sink” a current with respect to direction of current flow. Furthermore, a phrase such as “providing a current” or “driving a current” includes the output current Ibeing both positive (e.g., “sourcing a current”) and negative (e.g., “sinking a current”).

802 502 502 502 502 401 read In an embodiment, the current generation and delivery circuitryprovides a first write current to “set” the memory cell a second write current to “reset” the memory cell, wherein these two write currents have opposite polarities (i.e., positive and negative). During a read the current increases the voltage across the selected memory cell until the threshold switching selectorswitches on. In an embodiment, the read current has a positive polarity and charges up the selected word line (with the bit line at a lower voltage) until the threshold switching selectorswitches on. In an embodiment, the read current has a negative polarity similar to the reset or set current and lowers the selected word line voltage (with the selected bit line at a higher voltage) until the threshold switching selectorswitches on. After the threshold switching selectorswitches on, Iis driven through the memory cell.

802 401 804 401 804 401 804 401 The current generation and delivery circuitryhas a capacitance which can impact the programmable resistance memory cell. Herein, this will be referred to as the “circuit capacitance”. The capacitive isolation circuitryis able to isolate the memory cellfrom the circuit capacitance. The capacitive isolation circuitrymay also isolate the memory cellfrom the capacitance associated with a sense amplifier. In an embodiment, the capacitive isolation circuitrycontains one or more transistors that provide the read current to the selected word line. In an embodiment, these transistor(s) serve as decode transistors. In an embodiment, the memory system controls the resistance of these one or more transistors in order to provide the capacitive isolation. In an embodiment, the transistors are only weakly on (higher resistance) to provide capacitive isolation and more strongly on (lower resistance) for a default mode without the capacitive isolation. The memory cellis read in the default mode without the capacitive isolation. In an embodiment, the capacitive (cap) isolation enable signal is used to select either the capacitive isolation mode or the default mode. Note that the read current may be provided to the selected word line in either mode.

804 502 502 401 401 804 The capacitive isolation circuitrymay be operated in the capacitive isolation mode when the read current is charging the word line to turn on the threshold switching selectorand for a period time after the threshold switching selector switches on. A snapback current may occur when the threshold switching selectorswitches on and there is a rapid voltage drop across the memory cell. The snapback current is proportional to capacitance in circuitry adjacent to the memory array. Isolating the memory cellfrom this circuit capacitance reduces the snapback current. However, at some point the capacitive isolation is removed in order to read the memory cell. The resistance of the read path should be low in order to improve read accuracy. As noted above, transistors in the capacitive isolation circuitrymay be operated at a higher resistance in the capacitive isolation mode. However, for better read accuracy it is desirable to reduce the resistance of these transistors.

401 806 401 806 401 806 806 401 806 806 Removing the capacitive isolation may itself cause another type of snapback current (“circuit snapback”), which could disturb the state of the memory cell. The discharge circuitryprovides a discharge pathway to prevent this circuit snapback current from disturbing the state of the memory cell. In an embodiment, the discharge circuitryis activated during the time period in which the capacitive isolation mode is exited in order to prevent this circuit snapback current from disturbing the state of the memory cell. The discharge enable signal is used to control whether the discharge circuitryis active. The discharge circuitryis disabled prior to reading the memory cell. In an embodiment, the discharge circuitryincludes one or more capacitors that are used for charge sharing. In an embodiment, the discharge circuitryincludes one a voltage source that may provide, for example, a step voltage pulse. In an embodiment, the step voltage is a power source voltage.

9 FIG.A 9 FIG.A 8 FIG. 9 FIG.A 904 904 904 802 902 804 902 902 902 902 902 902 902 902 906 1 806 1 806 806 is a simplified schematic diagram of an embodiment of circuitry for reading a memory cell.provide some details of an embodiment of the system in. A read current sourceprovides a read current. In this example, the read current sourceis connected to a voltage V_P, which could be about 3.3V as one example. To select the bit line (BL) the bit line may be set to ground, as one example. The read current is used in this example to charge up the voltage on the selected word line. The read current sourceis within an embodiment of current generation and delivery circuitry. In this simplified diagram other elements such as current drivers are not depicted in. PMOS decode transistoris within one embodiment of capacitive isolation circuitry. The gate of PMOS decode transistoris provided with cap isolation control signal to control whether the PMOS decode transistoris in the default mode, capacitive isolation mode, or unselected. The PMOS decode transistoris selected (on) to select the word line. In other words, the PMOS decode transistoris selected (on) to connect the read current source to the selected word line. The PMOS decode transistoris unselected (off) when the word line is not selected. The magnitude of the cap isolation control signal is used to control the overdrive of the PMOS decode transistor. The PMOS decode transistoris only weakly on (high resistance) for the capacitive isolation mode. The PMOS decode transistoris more strongly on (low resistance) for the default mode used during read. The step voltage sourceand switch Sare within one embodiment of discharge circuitry. In an embodiment, Sis closed to enable the discharge circuitryand open to disable the discharge circuitry.

9 FIG.B 9 FIG.B 8 FIG. 1 2 806 2 806 806 is a simplified schematic diagram of an embodiment of circuitry for reading a memory cell.provide some details of another embodiment of the system in. The capacitor Cand switch Sare within one embodiment of discharge circuitry. In an embodiment, Sis closed to enable the discharge circuitryand open to disable the discharge circuitry.

10 FIG. 8 FIG. 1000 401 1000 502 702 1000 1000 1000 1000 1000 is a flowchart of one embodiment of a processof reading a programmable resistance memory cell. The processmay be used to read memory cells having a threshold switching selectorin series with a programmable resistance memory element. The processmay improve read accuracy (bit error rate) by preventing the memory cell from inadvertently flipping its state prior to sensing the cell. In one embodiment, processis used in a midpoint read (also referred to as a globally referenced read for “direct cell read compared to reference voltage”). In one embodiment, processis used in a midpoint read (also referred to as a globally referenced read for “direct cell read compared to reference voltage”). In one embodiment, processis used in an SRR. The processmay be performed by the system in, but is not limited thereto.

1002 802 802 220 Stepincludes providing a read current to a selected word line connected to a selected memory cell. The read current is generated by a current source in current generation and delivery circuitry. The current generation and delivery circuitrymay reside in row controlwith other circuitry such as sense amplifiers. A select voltage may be applied to a selected bit line while driving the read current to the selected word line. In one embodiment, the selected bit line is held at about 0V while a read current of about 15 μA is driven to the selected word line. In one embodiment, the selected bit line is held at about 3.3V while a read current of about −15 μA is driven to the selected word line.

1004 802 1004 804 802 1004 Stepinclude providing capacitive isolation for the selected memory cell from the circuit capacitance of the current generation and delivery circuitry. Stepmay include enabling the capacitive isolation circuitryfor the capacitive isolation mode. In an embodiment, the resistance of one or more transistors between the current source in current generation and delivery circuitryand the selected memory cell is set to a high resistance level, but with the transistor weakly on. Therefore, the read current continues to be provided to the selected word line. Stepmay also provide capacitive isolation for the selected memory cell from other row control circuitry such as a sense amplifier.

1006 806 1 Stepincludes providing a discharge path in preparation for removing the capacitive isolation. In an embodiment, the discharge circuitryis enabled. In one embodiment, a capacitor (e.g., C) is connected to a read path. In one embodiment, a voltage source (e.g., Vstep) is connected to the read path.

1008 1004 804 806 401 Stepincludes removing the capacitive isolation. Stepmay include setting the capacitive isolation circuitryto the default mode. The discharge circuitryremains enabled while the capacitive isolation is removed to prevent a potential snapback current from the removal of the capacitive isolation from disturbing the state of the memory cell.

1010 806 Stepincludes removing the discharge path. In an embodiment, the discharge circuitryis disabled.

1012 806 804 1 2 Stepincludes sensing the memory cell. The memory cell is thus sensed with the discharge circuitrydisabled and with the capacitive isolation circuitryin the default mode. Recall that in the default mode the one or more transistors that provide for the capacitive isolation have a low resistance (e.g., strongly on). In one embodiment, the sensing is for a Readof an SRR. In one embodiment, the sensing is for a Readof an SRR after the write to a particular state. In one embodiment, the sensing is for a globally referenced read.

11 11 11 11 FIGS.A,B,C, andD 11 FIG.A 11 FIG.B 11 FIG.C 11 FIG.D 11 FIG.D 11 FIG.B 1102 1 8 1 5 1112 802 4 6 1122 806 1 1 1 2 2 502 3 806 4 1132 4 6 806 5 5 806 806 7 806 8 depict timing of signals during an embodiment of read with snapback protection with capacitive isolation.shows timing for one embodiment of the read current, which is applied to the selected word line. The read current (plot) is applied to the selected word line between time tand t.shows timing for one embodiment of a capacitive isolation enable signal. The capacitive isolation enable signal is active between tand t(plot). Capacitive isolation is provided while the capacitive isolation enable signal is active. The capacitive isolation may be used to isolate the selected word line from the capacitance of the current generation and delivery circuitry.shows timing for one embodiment of a capacitive discharge signal. The capacitive discharge signal is active between tand t(plot). The discharge circuitryis enabled while the capacitive discharge signal is active. Note that the capacitive discharge signal is active during the period in which the capacitive isolation is removed.depicts voltages on the selected word line and the selected bit line. Prior to t, both the selected word line and the selected bit line are driven to Vmid by the memory system. The bit line voltage may be brought down to ground after t. The word line voltage increases between tand tdue to the read current. At tthe threshold switching selector switches on. The resistance of the threshold switching selectormay reduce rapidly when it switches on. A significant snapback current may result due to voltage change and circuit capacitance. This snapback current could potentially flip the state of the memory cell prior to read. However, in an embodiment, capacitive isolation is provided while the snapback current is present. The capacitive isolation may reduce the magnitude of the snapback current. By tthe word line voltage has settled down to a stable voltage. Therefore, the capacitive isolation may be removed. However, prior to removing the capacitive isolation the discharge circuitryis enabled at t. The regionhighlighted inindicates the time period between tand tfor which the discharge circuitryis enabled. Referring back to, the capacitive isolation is removed at t. The removal of the capacitive isolation at tcould itself create a circuit snapback current that could potentially flip the state of the memory cell. However, the discharge circuitryprovides a pathway to discharge such a circuit snapback current to thereby prevent the memory cell from inadvertently flipping its state. At to the discharge circuitrymay be disabled. At tthe memory cell may be read. Thus, the memory cell is read with the discharge circuitryand the capacitive isolation both disabled. At tthe bit line and word line voltages may be brought back to Vmid.

806 806 906 4 6 1222 906 1 4 6 12 12 FIGS.A andB 11 11 FIGS.A andB 12 FIG.A 9 FIG.A 12 FIG.B 11 FIG.D 12 FIG.B In one embodiment the discharge circuitryincludes a voltage source that is connected to the read path to provide the discharge.are timing diagrams of signals during an embodiment of read with the discharge circuitryincluding voltage source. The read current and capacitive isolation may be timed as in, respectively.shows timing of a step voltage Vstep. The step voltagemay be connected to the read path from tto t(plot). Refer back tofor an example of connecting Vstepto the read path using S.shows timing of voltages to the word line and bit line. The timings are similar to; however, inVstep is applied to the word line between tand t.

13 FIG.A 13 FIG.A 13 FIG.A 2 3 FIG., 1302 401 804 1302 802 802 1 806 1304 1304 1304 1304 401 802 804 806 1304 220 a is a schematic diagram of one embodiment of a read path. The read path includes a current source, driver transistor T1, word line decode transistors (T3P, TIP), the word line (WL), the memory cell, the bit line (BL), and bit line decode transistors (TIN, T3N). The word line decode transistors (T3P, TIP) are within one embodiment of capacitive isolation circuitry. The word line decode transistors (T3P, TIP) serve as both decoders and to provide the capacitive isolation. Therefore, the signal to their control gates is referred to as “Cap Isolation/Decode”. The current sourceand driver transistor T1 are within one embodiment of current generation and delivery circuitry. Note that current generation and delivery circuitryhas other current sources and transistors, which are not depicted in. The step voltage source and switch Sare within one embodiment of discharge circuitry.also depicts a sense amplifier (amp). The non-inverting input (+) of the sense ampis connected to node VXSP. The inverting input (−) of the sense ampis provided with a reference voltage (Vref). Note that the capacitive isolation may also be used to isolate capacitance of the sense amplifierfrom the selected memory cell. The current generation and delivery circuitry, capacitive isolation circuitry, and discharge circuitry, and sense ampmay form part of the row control(see).

1302 1304 1304 read The read path has a Vp positive power supply, such as about 3.3V. The read current sourceis connected to the power supply (Vp) and supplies Ito the memory cell. The read current may be enabled by taking Read*low to turn on transistor T1. The output of T1, which is node VXSP, also drives the non-inverting input (+) of the differential sense amp. The inverting input (−) of the differential sense ampis provided with a reference voltage (Vref). For a globally referenced read Vref is a global reference voltage. For a SRR Vref is derived from a previous sense operation by, for example, bumping voltage from Read 1 by 150 mV.

P-channel transistor T3P serves as a global WL decoder, which may be selected when the gate of T3P is low by signal Cap Isolation/Decode. P-channel transistor TIP serves as a local WL decoder, which may be selected when the gate of TIP is low by signal Cap Isolation/Decode. P-channel transistor T3P may serve as a driver to the selected WL. However, note that there may be two selection modes for TP3 and TIP: 1) normal mode (lower resistance) and 2) capacitive isolation mode (higher resistance). Thus, TP3 and TIP may be only weakly on for the capacitive isolation mode. However, for the normal mode TP3 and TIP may be on more strongly.

401 502 702 401 The memory cellis connected between the WL and the BL. The memory cell (or bit) has a threshold switching selectorand a memory element. The selected WL may be 1 of N WLs in an array. The BL may be 1 of M BLs in an array. The memory cellmay reside at a cross-point of the WL and the BL on a chip with one or more arrays. N-channel transistor TIN may serve as a local decode driver into the BL. The BL may be selected when TIN gate is high, such as when driven by a binary decoder address signal. N-channel transistor T3N may serve as a global decoder, which is selected when T3N gate is high, such as when driven by a binary decoder address signal. The output of T3N is VYS. A driver (YEN) is between VYS and a negative (i.e., negative relative to Vp) power supply (GND).

1 802 read read Operation of the read path may in one embodiment be as follows. Node VXSP, the selected WL, the selected BL and VYS may be transistor pre-charged to Vmid during a standby phase. The desired WL line (of N) may be selected by turning off the pre-charge and applying a low voltage to the gates of transistors T3P and TIP. The BL line may be selected by turning off the pre-charge and applying a high voltage to the gates of transistors TIN and T3N (the gate voltages being referred to as decode address signals). The gate of transistor YEN may be taken high to connect node VYS to GND. Imay then be turned on and connected to VXSP by taking the gate of T1 low (e.g., Read*goes low). The BL may thus be rapidly pulled to GND by its active driver upon turn-on by YEN going H. The selected WL and VXSP are ramped towards Vp by I. In an embodiment, transistors T3P and TIP are only weakly on when charging up the selected WL in order to provide capacitive isolation for the selected memory cell from the current generation and delivery circuitry.

502 502 806 702 502 502 702 702 th th read The threshold switching selectorturns on when the voltage on WL reaches an approximate voltage of V(OTS) since I×R drops from leakage are relatively low. Here, V(OTS) refers to the threshold switching voltage of the threshold switching selector, which may be but it not required to be an OTS. Then, the voltage on VXSP into the sense ampsettles back at Vfinal=Vread (final)=Voff (OTS)+Rpath×I. Here, Rpath includes WL and BL wire resistances, the address transistors (T3P, TIP, TIN, T3N) on each of the bit line and word line, and the bit line driver (YEN) to GND, as well as the resistance of the memory element itself. Here, Voff (OTS) refers to a voltage across the threshold switching selectorwhen it thresholded on. A snapback current may result due to the falling voltage on the word line when the threshold switching selectorturns on. However, the capacitive isolation reduces the magnitude of the snapback current to thereby reduce current flow through the memory elementwhen snapback current is present to reduce the probability of the memory elementfrom inadvertently flipping its state.

806 806 1 401 806 a After the voltage on the word line stabilizes the capacitive isolation may be removed. However, in preparation for removing the capacitive isolation a discharge path is provided by the discharge circuitry. In an embodiment, the step voltage Vstep is connected to node VXSP on the read path, After connecting Vstep to node VXSP, the capacitive isolation may be removed. In an embodiment, the capacitive isolation is removed by changing the voltage to the gates of transistors T3P and TIP to turn on those transistors more strongly (more overdrive) in order to reduce the resistance of transistors T3P and TIP. After the capacitive isolation is removed, the discharge circuitrymay be disabled by opening switch S. Then, the memory cellis sensed. The sense ampcompares Vfinal that is input on sense amp (+) to Vref on sense amp (−).

13 FIG.B 13 FIG.A 13 FIG.A 13 FIG.B 806 1 2 1 a a a depicts an alternative embodiment to the read path ofin which the discharge circuitryincludes a capacitor C. Operation of the read path is similar to. However, inswitch Sis used to connect capacitor Cto node VXSP to provide the discharge path.

14 FIG.A 13 FIG.A 14 FIG.A 806 1402 401 804 1402 802 802 1 806 b is a schematic diagram of one embodiment of a read path to which discharge circuitrymay be connected. The read path is analogous to the read path in, but the read current is directed away from the selected word line. The read path includes a current source, driver transistor T1, word line decode transistors (T13N, T11N), the word line (WL), the memory cell, the bit line (BL), and bit line decode transistors (T11P, T13N). The word line decode transistors (T13N, T11N) are within one embodiment of capacitive isolation circuitry. The word line decode transistors (T13N, T11N) serve as both decoders and to provide the capacitive isolation. Therefore, the signal to their control gates is referred to as “Cap Isolation/Decode”. The current sourceand driver transistor T1 are within one embodiment of current generation and delivery circuitry. Note that current generation and delivery circuitryhas other current sources and transistors, which are not depicted in. The step voltage source and switch Sare within one embodiment of discharge circuitry.

1402 502 1304 1304 read The read path has a Vp positive power supply connected to transistor YEP, such as about 3.3V. The read current sourceis connected to ground and supplies Ito the memory cell (current flows from bit line to word line when the threshold switching selectoris on). The read current may be enabled by taking Read*to low to turn on transistor T1. The output of T1, which is node VXSN, also drives the non-inverting input (+) of the differential sense amp. The inverting input (−) of the differential sense ampis provided with a reference voltage (Vref). For a globally referenced read Vref is a global reference voltage. For a SRR Vref is derived from a previous sense operation by, for example, bumping voltage from Read 1 by 150 m V.

N-channel transistor T13N serves as a global WL decoder, which may be selected when the gate of T13N is high by signal Cap Isolation/Decode. N-channel transistor T11N serves as a local WL decoder, which may be selected when the gate of T11P is high by signal Cap Isolation/Decode. N-channel transistor T13N may serve as a driver to the selected WL. However, note that there may be two selection modes for T13N and T1IN: 1) normal mode (lower resistance) and 2) capacitive isolation mode (higher resistance). Thus, T13N and T1IN may be only weakly on for the capacitive isolation mode. However, for the normal mode T13N and T11N may be on more strongly.

401 804 10 FIG. The memory cellis similar to the cell described in connection with. The BL may be selected when T11P gate is low, such as when driven by a binary decoder address signal from the from control circuit. P-channel transistor T13P may serve as a global decoder, which is selected when T13P gate is low, such as when driven by a binary decoder address signal. The output of T13P is VYS. A driver (YEP) is between VYS and a positive power supply (Vp), which may be about 3.3V.

1 802 read read Operation of the read path may in one embodiment be as follows. Node VXSP, the selected WL, the selected BL and VYS may be transistor pre-charged to Vmid during a standby phase. The desired WL line (of N) may be selected by turning off the pre-charge and applying a low voltage to the gates of transistors T13N and T11N. The BL line may be selected by turning off the pre-charge and applying a high voltage to the gates of transistors T11P and T13P. The gate of transistor YEP may be taken high to connect node VYS to GND. Imay then be turned on and connected to VXSP by taking the gate of T1 low (e.g., Read*goes low). The BL may thus be rapidly pulled to GND by its active driver upon turn-on by YEP going H. The selected WL and VXSP are ramped towards Vp by I. In an embodiment, transistors T11N and T13N are only weakly on when charging up the selected WL in order to provide capacitive isolation for the selected memory cell from the current generation and delivery circuitry.

502 502 702 702 th The threshold switching selectorturns on when the voltage on WL reaches an approximate voltage of V(OTS). A snapback current may result due to the falling voltage on the word line when the threshold switching selectorturns on. However, the capacitive isolation reduces the magnitude of the snapback current to thereby reduce current flow through the memory elementwhen snapback current is present to reduce the probability of the memory elementfrom inadvertently flipping its state.

806 1304 1 401 1304 b After the voltage on the word line stabilizes the capacitive isolation may be removed. However, in preparation for removing the capacitive isolation a discharge path is provided by the discharge circuitry. In an embodiment, the step voltage Vstep is connected to node VXSP on the read path, After connecting Vstep to node VXSP, the capacitive isolation may be removed. In an embodiment, the capacitive isolation is removed by changing the voltage to the gates of transistors T13N and T11N to turn on those transistors more strongly (more overdrive) in order to reduce the resistance of transistors T13N and T11N. After the capacitive isolation is removed, the discharge circuitrymay be disabled by opening switch S. Then, the memory cellis sensed. The sense ampcompares Vfinal that is input on sense amp (+) to Vref on sense amp (−).

14 FIG.B 14 FIG.A 14 FIG.A 14 FIG.B 806 1 2 1 b b b depicts an alternative embodiment to the read path ofin which the discharge circuitryincludes a capacitor C. Operation of the read path is similar to. However, inswitch Sis used to connect capacitor Cto node VXSP to provide the discharge path.

15 FIG. 8 FIG. 1500 401 1500 502 702 1500 1500 1000 1000 1000 is a flowchart of one embodiment of a processof reading a programmable resistance memory cell. The processmay be used to read memory cells having a threshold switching selectorin series with a programmable resistance memory element. The processmay improve read accuracy (bit error rate) by preventing the memory cell from inadvertently flipping its state prior to sensing the cell. In one embodiment, processis used in a midpoint read (also referred to as a globally referenced read for “direct cell read compared to reference voltage”). In one embodiment, processis used in a midpoint read (also referred to as a globally referenced read for “direct cell read compared to reference voltage”). In one embodiment, processis used in an SRR. The processmay be performed by the system in, but is not limited thereto.

1502 802 1504 502 1504 1504 802 13 14 FIG.A-B Stepincludes generating a read current using current generation of delivery circuitry. Stepincludes applying a first gate voltage to decode transistor(s) to thereby cause a high resistance in the decode transistor(s) and to provide the read current to a selected programmable resistance memory cell. Note that initially the threshold switching selectoris off. Stepmay include providing the Cap Isolation Decode signal to any of the WL decode transistors in, as examples. The Cap Isolation Decode signal will only weakly turn on the WL decode transistors at this time. However, the read current will be provided to the selected word line. A select voltage may be applied to a selected bit line while driving the read current to the selected word line. In one embodiment, the selected bit line is held at about 0V while a read current of about 15 μA is driven to the selected word line. In one embodiment, the selected bit line is held at about 3.3V while a read current of about −15 μA is driven to the selected word line. Stepmay provide capacitive isolation to the selected memory cell from the circuit capacitance of the current generation and delivery circuitry.

1506 806 1 1 2 2 1 21 a b a b a Sepincludes providing a discharge path in preparation for lowering the resistance of the decode transistor(s). In an embodiment, the discharge circuitryis enabled. In one embodiment, a capacitor (e.g., C, C) is connected to a read path by closing Sor S. In one embodiment, a voltage source (e.g., Vstep) is connected to the read path by closing Sor S.

1508 1504 1508 806 401 Stepincludes changing the gate voltage to the decode transistor(s) to a second voltage that lowers the resistance of the decode transistor(s). This second voltage may provide a greater overdrive than the first gate voltage of step. Stepmay remove the capacitive isolation. The discharge circuitryremains enabled while the capacitive isolation is removed to prevent a potential snapback current from the removal of the capacitive isolation from disturbing the state of the memory cell.

1510 806 1 21 2 2 1506 1510 a a b Stepincludes removing the discharge path. In an embodiment, the discharge circuitryis disabled. In an embodiment, the switch (e.g., S, S, S, S) that was closed in stepis opened in step.

1512 806 804 1 2 Stepincludes sensing the memory cell. The memory cell is thus sensed with the discharge circuitryis disabled and with the capacitive isolation circuitryin the default mode. Recall that in the default mode the one or more transistors that provide for the capacitive isolation have a low resistance (e.g., strongly on). In one embodiment, the sensing is for a Readof an SRR. In one embodiment, the sensing is for a Readof an SRR after the write to a particular state. In one embodiment, the sensing is for a globally referenced read.

In view of the foregoing, it can be seen that, according to an embodiment, an apparatus comprises an apparatus comprising a cross-point memory structure having first conductive lines, second conductive lines, and memory cells. Each memory cell is at a crosspoint of a first conductive line and a second conductive line. Each memory cell has a programmable resistance memory element in series with a threshold switching selector. The apparatus comprising current generation and delivery circuitry configured to generate a read current. The current generation and delivery circuitry has a circuit capacitance. The apparatus comprises one or more control circuits configured to communicate with the cross-point memory structure and the current generation and delivery circuitry. The one or more control circuits configured to connect the current generation and delivery circuitry to a selected first conductive line in the cross-point memory structure while providing a select voltage to a selected second conductive line to provide the read current to the selected first conductive line. A selected memory cell resides between the selected first conductive line and the selected second conductive line. The one or more control circuits configured to temporarily provide capacitive isolation of the selected first conductive line from the circuit capacitance of the current generation and delivery circuitry while providing the read current to the selected first conductive line. The one or more control circuits configured to provide a discharge path to a node between the current generation and delivery circuitry and the selected first conductive line during a period in which the one or more control circuits remove the capacitive isolation. The one or more control circuits configured to sense the selected memory cell after both the temporary capacitive isolation and the discharge path have been removed.

In a further embodiment, the one or more control circuits are configured to connect a capacitor to the node between the current generation and delivery circuitry and the selected first conductive line to provide the discharge path to the selected first conductive line.

In a further embodiment, the one or more control circuits are configured to provide a voltage step pulse to the node between the current generation and delivery circuitry and the selected first conductive line to provide the discharge path to the selected first conductive line.

In a further embodiment, the step voltage pulse comprises a power supply voltage.

In a further embodiment, the one or more control circuits are configured to: temporarily provide the capacitive isolation for the selected first conductive line from the circuit capacitance while the threshold switching selector of the selected memory cell switches on; and provide the discharge path to the node after the threshold switching selector of the selected memory cell switches on.

In a further embodiment, the programmable resistance memory element comprises a magnetoresistive element.

In a further embodiment, the threshold switching selector comprises an Ovonic Threshold Switch (OTS).

In a further embodiment, the one or more control circuits are configured to apply a first overdrive voltage to a control gate of a decode transistor between the current generation and delivery circuitry and the selected first conductive line to connect the current generation and delivery circuitry to the selected first conductive line. The first overdrive voltage causes the decode transistor to provide the capacitive isolation. The one or more control circuits are configured to change the first overdrive voltage to a second overdrive voltage applied to the control gate of the decode transistor. The second overdrive voltage turns on the decode transistor more strongly than the first overdrive voltage. The selected memory cell is sensed with the decode transistor at the second overdrive voltage. The one or more control circuits are configured to provide the discharge path to the node during a period in which the voltage to the control gate of the decode transistor is changed from the first overdrive voltage to the second overdrive voltage.

In a further embodiment, the one or more control circuits are configured to connect a capacitor to the node between the current generation and delivery circuitry and the selected first conductive line to provide the discharge path to the node during the period in which the voltage to the control gate of the decode transistor is changed from the first overdrive voltage to the second overdrive voltage.

In a further embodiment, the one or more control circuits are configured to provide a voltage step pulse to the node between the current generation and delivery circuitry and the selected first conductive line to provide the discharge path to the selected first conductive line during the period in which the voltage to the control gate of the decode transistor is changed from the first overdrive voltage to the second overdrive voltage.

In a further embodiment, the one or more control circuits are configured to cause a first resistance in a transistor between the current generation and delivery circuitry and the selected first conductive line in the cross-point memory structure to temporarily provide the capacitive isolation of the selected first conductive line from the circuit capacitance while providing the read current to the selected first conductive line. The one or more control circuits are configured to cause a second resistance in the transistor after the threshold switching selector of the selected memory cell switches on to remove the capacitive isolation. The second resistance is lower than the first resistance. The selected memory cell is sensed with the transistor at the second resistance. The one or more control circuits are configured to provide the discharge path to the selected first conductive line during a period in which the resistance of the transistor is lowered from the first resistance to the second resistance.

An embodiment includes a method for reading a programmable resistance memory cell in a cross-bar array. The method comprises generating a read current with current generation and delivery circuitry having a circuit capacitance. The method comprises applying a first overdrive voltage to a control gate of a decode transistor between the current generation and delivery circuitry and a selected first conductive line in the cross-bar array to connect the current generation and delivery circuitry to the selected first conductive line. The first overdrive voltage results in a first resistance of the decode transistor. The method comprises changing the first overdrive voltage to a second overdrive voltage applied to the control gate of the decode transistor. The second overdrive voltage results in a second resistance of the decode transistor that is lower than the first resistance. The method comprises providing a discharge path to the selected first conductive line during a period in which the voltage to the decode transistor is changed from the first overdrive voltage to the second overdrive voltage. The method comprises removing the discharge path to the selected first conductive line after changing the first overdrive voltage to the second overdrive voltage. The method comprises sensing a selected memory cell connected to the selected first conductive line after discharge path has been removed and while the second overdrive voltage is applied to the decode transistor.

An embodiment includes a memory system comprising a cross-point memory structure having first conductive lines, second conductive lines, and memory cells. Each memory cell is at a crosspoint of a first conductive line and a second conductive line. Each memory cell has a programmable resistance memory element in series with a threshold switching selector. The memory system has current generation and delivery circuitry configured to generate a read current. The current generation and delivery circuitry has a circuit capacitance. The memory system has one or more control circuits configured to communicate with the cross-point memory structure and the current generation and delivery circuitry. The one or more control circuits are configured to cause a first resistance in a transistor between the current generation and delivery circuitry and a selected first conductive line in the cross-point memory structure while providing a select voltage to a selected second conductive line to provide the read current through the transistor to the selected first conductive line. A selected memory cell resides between the selected first conductive line and the selected second conductive line. The one or more control circuits are configured to cause a second resistance in the transistor after the threshold switching selector of the selected memory cell switches on, the second resistance is lower than the first resistance. The one or more control circuits are configured to provide a discharge path for the selected first conductive line during a period in which the resistance of the transistor is lowered from the first resistance to the second resistance. The one or more control circuits are configured to remove the discharge path after lowering the resistance of the transistor to the second resistance. The one or more control circuits are configured to sense the selected memory cell after the discharge path has been removed and the transistor has the second resistance.

For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.

For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.

For purposes of this document, the term “based on” may be read as “based at least in part on.”

For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.

The terms “top” and “bottom,” “upper” and “lower” and “vertical” and “horizontal,” and forms thereof, as may be used herein are by way of example and illustrative purposes only, and are not meant to limit the description of the technology inasmuch as the referenced item can be exchanged in position and orientation. Also, as used herein, the terms “substantially” and/or “about” mean that the specified dimension or parameter may be varied within an acceptable tolerance for a given application.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.