Method and system for determining a round-trip latency of a quantum communication channel

This application is a Continuation Application of International Application No. PCT/NL2022/050709, filed Dec. 8, 2022 and published as WO 2023/106922 on Jun. 15, 2023, in English, and claims priority of Netherlands application NL2030076, filed Dec. 8, 2021, the contents of both are incorporated herein by reference in their entirety.

The present disclosure relates to a method and system for determining a round-trip latency of a communication channel in a communication system between a first device located at a first location and a second device located at a second location that is remote from the first location, wherein the communication system comprises a clock unit configured to generate clock cycles, a quantum communication network comprising such a system, and a computer program configured to execute the method.

Quantum information systems are data processing systems that use a quantum system, e.g. a qubit, as an information carrier. In conventional data processing systems the basic unit of information is bits that either have the value ‘0’ or ‘1’. In contrast, the basic unit of information in quantum information systems are qubits, wherein a qubit may be a two-state quantum mechanical system. The special property of a qubit is that it can be in either ‘0’, ‘1’, or a superposition of both states simultaneously. One example of a quantum information system wherein qubits are used is a Quantum Key Distribution (QKD) system.

QKD systems allow two or more users at different locations to securely generate cryptographic keys by at least partly making use of the special property of the qubits. The first proposal for a QKD system (BB84) was done by C. H. Bennett and G. Brassard, described in the article “Quantum cryptography: Public key distribution and coin tossing”, Proceedings of IEEE International Conference on Computers, Systems and Signal Processing, volume 175, page 8. New York, 1984. An advantage of using a QKD system is that, at least in theory, the key is even secure in case an eavesdropper is present in the system.

Often QKD systems are based on lasers and field programmable gate arrays to generate time-bin qubits. Time bin qubits may be formed by a coherent superposition of two independent temporal modes of light field. Time-bin encoding is especially suitable for single-mode optical fiber propagation and compatible with already existing fiber networks. Hence, the formation of time bin qubits in QKD systems is a practical element in the development of practical QKD implementations. QKD protocols such as the above referred BB84 protocol, the coherent one-way (COW) QKD protocol and other QKD protocols such as described in the article by Vagniluca et al, Efficient time-bin encoding for practical high-dimensional quantum key distribution, physical review applied 14, 014051 (2020), may use a train of phase coherent temporal modes by intensity modulation of the output of a continuous-wave (CW) laser and subsequent attenuation. The time bin qubits may have an early, late or vacuum state.

A QKD system may comprise sender and receiver nodes. Hereafter we shall refer to a sender node as Alice and a receiver node as Bob. In some instances, the distance between Alice and Bob is not precisely known. In these situations it is not known what the value of the round-trip latency of a signal is when the signal travels from Alice to Bob and back. The round-trip latency of the signal is important for a correct working of a QKD system and more generally to a quantum communication network, as both Alice needs to know which qubit was sent resulting in a successful qubit projection measurement. Therefore, it is an object of the present disclosure to precisely determine the round-trip latency of a communication channel.

U.S. Pat. No. 10,110,369 B2 discloses a method for determining the time of flight (TOF) or latency for a communication system, which is used for clock synchronization in a quantum channel. A quantum source device generates a photon pulse and registers the time of transmission (TOT) using an external clock source. The receiver device receives the photon pulse and logs the time of arrival (TOA) by using a local clock. The receiver modulates one or more photons of the photon pulse and returns the one or more photons to the source device via the quantum channel. The source device detects the returned photons and logs a time of return (TOR). The source device may determine the TOF for photons of the photon pulse based on the time of return (TOR) and the time of transmission (TOT). The time of flight (TOF) is determined based on calculating TOR−TOT/2. The receiver device may utilize the TOF information, the TOA information and the TOT information to generate a compensation metric for the receiver clock to synchronize with the external clock source communicatively coupled to the source device.

In a first aspect, the disclosure relates to a method for determining a round-trip latency of a communication channel in a communication system between a first device located at a first location and a second device located at a second location that is remote from the first location, wherein the communication system comprises a clock unit configured to generate clock cycles. The method may comprise setting an estimated round-trip latency value at the first location, wherein the estimated round-trip latency value is represented as a binary number, generating and sending, during a first period, a first test signal by the first device to the second device, wherein the first test signal comprises alternating first values and second values, wherein first and second values are sent at each clock cycle of the clock unit, saving by the first device each first and second value of the first test signal for at least a duration that corresponds to the estimated round-trip latency value, receiving the first test signal at the second device, sending, by the second device to the first device, upon receiving the first test signal, a validating signal that is generated by the second device and is based on the first test signal, wherein the validating signal comprises at least second values when second values from the first test signal are received, receiving the validating signal at the first device, comparing the validating signal with the first test signal sent during the first period, and determining if the estimated round-trip latency value is correct based on the comparing of the validating signal and the first test signal.

In an embodiment comparing the validating signal with the first test signal comprises determining, at a time of receiving a second value from the validating signal, if the first test signal that is sent at a time that is one estimated round-trip latency value earlier than the receiving of the second value of the validating signal comprises a first or second value, and comparing the determined first or second value of the first test signal with the second value of the validating signal.

In an embodiment saving by the first device each first and second value of the first test signal for at least a duration that corresponds to the estimated round-trip latency value comprises storing each first and second value from the first test signal in a shift register, wherein the shift register has a length that corresponds to the estimated round-trip latency value, and when the received validating signal comprises the second value, the method further comprises determining, upon registering that the received validating signal comprises the second value, if an output of the shift register is a first or second value, and comparing the determined first or second value of the output of the shift register with the second value of the validating signal.

In an embodiment determining if the estimated round-trip latency value is correct further comprises determining, based upon at least the second values of the validating signal corresponding to the sending of the second values of the first test signal, that a least significant bit of the estimated round-trip latency value is correct.

In an embodiment the method further comprises flipping the least significant bit of the estimated round-trip latency value if the least significant bit of the estimated round-trip latency value is incorrect.

In an embodiment the steps of comparing the validating signal with the first test signal is repeated for a predetermined number of times, wherein each time that during a determination step the second value of the validating signal corresponds to the second value of the first test signal represents a correct measurement, and wherein determining if the estimated round-trip latency value is correct further comprises determining a ratio corresponding to a number of correct measurements divided by the predetermined number of times, and determine that the least significant bit of the estimated round-trip latency value is correct if the ratio is above a predetermined threshold.

In an embodiment determining if the estimated round-trip latency value is correct determines if the estimated round-trip latency value is off by is a multiple of one clock cycle compared to an actual round-trip latency value.

In an embodiment the estimated round-trip latency value represents a latency measured in clock cycles.

In an embodiment the method further comprises generating and sending, during a second period, a second test signal by the first device to the second device, wherein the second test signal comprises first values and second values, wherein each second value is preceded by three first values.

In an embodiment determining if the estimated round-trip latency value is correct further comprises determining, based upon at least the second values of the validating signal corresponding to the sending of the second values of the first test signal, that a second-to-least significant bit of the estimated round-trip latency value is correct.

In an embodiment the method further comprises flipping the second-to-least significant bit if the second-to-least significant bit of the estimated round-trip latency value is incorrect.

In an embodiment determining if the estimated round-trip latency value is correct determines if the estimated round-trip latency value is off by a multiple of 2 clock cycles compared to an actual round-trip latency value.

In an embodiment the method further comprises generating and sending, during a third period, a third test signal by the first device to the second device, wherein the third test signal comprises first values and second values, wherein each second value is preceded by seven first values.

In an embodiment determining if the estimated round-trip latency value is correct further comprises determining, based upon at least the second values of the validating signal corresponding to the sending of the second values of the first test signal, that a third-to-least significant bit of the estimated round-trip latency value is correct.

In an embodiment the method further comprises flipping the third-to-least significant bit if the third-to-least significant bit of the estimated round-trip latency value is incorrect.

In an embodiment determining if the estimated round-trip latency value is correct determines if the estimated round-trip latency value is off by a multiple of 4 clock cycles compared to an actual round-trip latency value.

In an embodiment the method further comprises generating and sending for n=1 till N, during a n-th period, a n-th test signal by the first device to the second device, wherein the n-th test signal comprises first and second values, wherein each second value is preceded by two to the power n minus one times a first value, and repeating the generating and sending of the test signal wherein with each repetition the value of n is increased by one.

In an embodiment determining if the estimated round-trip latency value is correct determines if the estimated round-trip latency value is off by a multiple of two to the power n−1 clock cycles compared to an actual round-trip latency value.

In an embodiment the method further comprises stopping the repeating of the generating of the test signal based on the distance between the first device and second device and the speed of light.

In an embodiment the test signals and/or validating signals are optical signals, and wherein preferably the first and second values are early, late or vacuum time bin qubits.

In an embodiment the clock signal is a Manchester encoded clock signal, and preferably wherein the validating signal is encoded onto the clock signal.

In an embodiment the estimated round-trip latency value is at least partly set based on a distance between the first and second device divided by the speed of light.

In a further aspect the disclosure relates to a system for determining a round-trip latency between a first and a second location of a communication channel. The system may comprise a first electronic device that is positioned at the first location comprising a controller and a signal circuit, a second electronic device that is positioned at the second location that is remote from the first location comprising a controller and a signal circuit, a clock unit that is configured to generate clock cycles which are sent to the first and second electronic device, wherein the controller of the first electronic device is configured to set an estimated round-trip latency value at the first electronic device, wherein the estimated round-trip latency value is represented as a binary number, generate and sending, during a first period, a first test signal by the first electronic device to the second electronic device, wherein the first test signal comprises alternating first values and second values, wherein first and second values are sent at each clock cycle of the clock unit, saving by the first electronic device each first and second value of the first test signal for at least a duration that corresponds to the estimated round-trip latency value, receive a validating signal at the first electronic device, compare the validating signal with the first test signal sent during the first period, and determine if the estimated round-trip latency value is correct based on the comparing of the validating signal and the first test signal. The controller of the second electronic device may be configured to receive the first test signal at the second electronic device, and send, to the first electronic device, upon receiving the first test signal, a validating signal that is generated by the second electronic device and is based on the first test signal, wherein the validating signal comprises at least second values when second values from the first test signal are received.

In an embodiment comparing the validating signal with the first test signal comprises determining, at a time of receiving a second value from the validating signal, if the first test signal that is sent at a time that is one estimated round-trip latency value earlier than the receiving of the second value of the validating signal comprises a first or second value, and comparing the determined first or second value of the first test signal with the second value of the validating signal.

In an embodiment saving by the first device each first and second value of the first test signal for at least a duration that corresponds to the estimated round-trip latency value comprises storing each first and second value from the first test signal in a shift register, wherein the shift register has a length that corresponds to the estimated round-trip latency value, and when the received validating signal comprises the second value, the method further comprises determining, upon registering that the received validating signal comprises the second value, if an output of the shift register is a first or second value, and comparing the determined first or second value of the output of the shift register with the second value of the validating signal.

In an embodiment determining if the estimated round-trip latency value is correct further comprises determining, based upon at least the second values of the validating signal corresponding to the sending of the second values of the first test signal, that a least significant bit of the estimated round-trip latency value is correct.

In an embodiment the method further comprises flipping the least significant bit of the estimated round-trip latency value if the least significant bit of the estimated round-trip latency value is incorrect.

In an embodiment the steps of comparing the validating signal with the first test signal is repeated for a predetermined number of times, wherein each time that during a determination step the second value of the validating signal corresponds to the second value of the first test signal represents a correct measurement, and wherein determining if the estimated round-trip latency value is correct further comprises determining a ratio corresponding to a number of correct measurements divided by the predetermined number of times, and determine that the least significant bit of the estimated round-trip latency value is correct if the ratio is above a predetermined threshold.

In an embodiment determining if the estimated round-trip latency value is correct determines if the estimated round-trip latency value is off by is a multiple of one clock cycle compared to an actual round-trip latency value.

In an embodiment the estimated round-trip latency value represents a latency measured in clock cycles.

In an embodiment the method further comprises generating and sending, during a second period, a second test signal by the first device to the second device, wherein the second test signal comprises first values and second values, wherein each second value is preceded by three first values.

In an embodiment determining if the estimated round-trip latency value is correct further comprises determining, based upon at least the second values of the validating signal corresponding to the sending of the second values of the first test signal, that a second-to-least significant bit of the estimated round-trip latency value is correct.

In an embodiment the method further comprises flipping the second-to-least significant bit if the second-to-least significant bit of the estimated round-trip latency value is incorrect.

In an embodiment determining if the estimated round-trip latency value is correct determines if the estimated round-trip latency value is off by a multiple of 2 clock cycles compared to an actual round-trip latency value.

In an embodiment the method further comprises generating and sending, during a third period, a third test signal by the first device to the second device, wherein the third test signal comprises first values and second values, wherein each second value is preceded by seven first values.

In an embodiment determining if the estimated round-trip latency value is correct further comprises determining, based upon at least the second values of the validating signal corresponding to the sending of the second values of the first test signal, that a third-to-least significant bit of the estimated round-trip latency value is correct.

In an embodiment the method further comprises flipping the third-to-least significant bit if the third-to-least significant bit of the estimated round-trip latency value is incorrect.

In an embodiment determining if the estimated round-trip latency value is correct determines if the estimated round-trip latency value is off by a multiple of 4 clock cycles compared to an actual round-trip latency value.

In an embodiment the method further comprises generating and sending for n=1 till N, during a n-th period, a n-th test signal by the first device to the second device, wherein the n-th test signal comprises first and second values, wherein each second value is preceded by two to the power n minus one times a first value, and repeating the generating and sending of the test signal wherein with each repetition the value of n is increased by one.

In an embodiment determining if the estimated round-trip latency value is correct determines if the estimated round-trip latency value is off by a multiple of two to the power n−1 clock cycles compared to an actual round-trip latency value.

In an embodiment the method further comprises stopping the repeating of the generating of the test signal based on the distance between the first device and second device and the speed of light.

In an embodiment the test signals and/or validating signals are optical signals, and wherein preferably the first and second values are early, late or vacuum time bin qubits.

In an embodiment the clock signal is a Manchester encoded clock signal, and preferably wherein the validating signal is encoded onto the clock signal.

In an embodiment the estimated round-trip latency value is at least partly set based on a distance between the first and second device divided by the speed of light.

In a further aspect the disclosure relates to a quantum communication network comprising a system according to any one foregoing embodiments.

In a further aspect the disclosure relates to a computer program configured to for executing the method steps according to any one of the foregoing embodiments.

It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present disclosure will be determined by the appended claims.

Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Still, certain elements are defined below for the sake of clarity and ease of reference.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range and any other stated or intervening value in that stated range, is encompassed within the disclosure. The upper and lower limits of these smaller ranges may independently be included in the smaller ranges and are also encompassed within the disclosure, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure.

It is noted that, as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. It is further noted that the claims may be drafted to exclude any optional element. As such, this statement is intended to serve as antecedent basis for use of such exclusive terminology as “solely,” “only” and the like in connection with the recitation of claim elements, or use of a “negative” limitation.

As will be apparent to those of skill in the art upon reading this disclosure, each of the individual exemplifying embodiments described and illustrated herein has discrete components and features which may be readily separated from or combined with the features of any of the other several exemplifying embodiments. Any recited method can be carried out in the order of events recited or in any other order which is logically possible.

1 FIG. 100 102 110 102 114 114 115 128 128 120 124 120 120 102 108 110 depicts an example of a QKD system comprising a system determining the round-trip latency according to an embodiment of the disclosure. The systemcomprises a first qubit moduleand a receiver node. First qubit modulecomprises a laser unit, in the illustrated example a distributed feedback laser, for supplying a continuous light field. After the laser unitan isolatoris positioned for stabilising the laser light. After the isolator the laser light is split by a polarizing beam splitter PBS. A first arm coming from PBSgoes to a qubit generation devicethat receives qubit state information from a field programmable gate array FPGA. Qubit generation devicemay for example comprise various intensity modulators, phase modulators, variable optical attenuators and/or isolators to obtain the desired properties for the qubits. The qubit made by qubit generation deviceis then sent from first qubit moduleover optical fiberto receiver node.

108 139 133 110 135 129 137 102 104 The qubit that is sent over optical fiberis received at a qubit measurement device, wherein a qubit projection measurement can be performed on the qubit. These detections of the qubit projection measurement are sent to FPGAof receiver node. The result of the measurement is encoded onto a clock signal using a Manchester encoder. The clock signal of clockis used to pulse a laser unit, in the illustrated example embodied as a DFB laser, thereby creating an optical clock signal. This clock signal is sent to first and second qubit module,.

102 121 123 102 110 124 102 102 110 The optical clock signal is received by first quantum moduleat photodiodethe resulting electrical signal is decoded by Manchester decoder DE. The decoding gives an electrical clock signal that synchronizes the entire system. Next to this, the decoding gives information to the first quantum moduleon the successful projection measurement at the receiver node. This information enters the FPGAof first qubit module. Subsequently first qubit modulebacktracks what qubit info corresponds with which measurement result, as there is a delay between sending the qubit and getting the measurement result from receiver node.

2 FIG. 240 242 242 244 246 248 250 rtt shows a schematic example of the electronic hardware. At time t=0 pulse information is generated by a field programmable gate array (FPGA)from Alice. This pulse information from the FPGA is sent to the electronicsof Alice. The electronicsof Alice may be pulse generator boards to create the appropriate electrical pulses. The electrical pulses are then sent to the opticsof Alice that may comprise intensity modulators for shaping the electrical pulses and for creating decoy states. The optics form the optical pulses based on the electrical pulses that were sent from the electronics of Alice. These optical pulses travel through optical fiberto the detectorof Bob. Bob detects these optical pulses and sends detection information back to Alice. The detection information is sent back with optical pulses through optical fiber. The time of the arrival of the optical pulses at Alice is characterized as t=t(round-trip time). The optical pulses may be early, late or vacuum state time bin qubits.

3 FIG. 1 2 FIGS.and 302 310 346 350 302 310 346 350 302 310 302 302 310 340 342 344 347 310 349 310 349 351 310 351 350 343 302 shows Alicebeing remotely located from Bob. Distance D of optical fibers,between Aliceand Bobmay not be precisely known, for example because of thermal expansion or contraction of the optical fibers,. Therefore the round-trip latency of a signal traveling from Aliceto Boband back to Aliceis also unknown. Alicecan send first or second values to Bob. This can be done with the FPGA, electronicsand optics, as explained in. These first or second values may respectively be a vacuum state and an early state of a time-bin light pulse configuration. It is clear to the skilled person that any information carrier that can comprise two signals which are distinguishable is suitable for the present disclosure. It is for example possible that the first value is an early state and the second value is a late state. Furthermore, the first and second values are not limited to time-bin light pulses. It may be possible that other information carriers, such as qubits, are used to send a first and second value from Alice to Bob. In the illustrated embodiment, the first and second values are sent to detectorof Bob. The detector sends the detection information to controllerof Bob. The controllerthen sends a validating signal command to opticsof Bobthat drives opticsto send the validating signal over optical fibertowards receiverof Alice.

350 347 351 135 129 133 110 1 FIG. In an embodiment, the validating signal send over optical fibermay be a clock signal whereon the detections information of the pulses detected at detectorare encoded. For example, opticsmay be driven by Manchester encoderwhich has as its input clockand FPGAof Bobas explained in.

4 FIGS.A-C 402 452 446 410 452 454 456 454 456 402 454 456 345 345 402 454 456 402 454 456 454 456 show an example of the method according to the invention. Alicesends during a first period a first test signalthrough optical fiberto Bob. First test signalcomprises first valuesand second values, in this example illustrated as 0's and 1's respectively. The first and second signals,are repeatedly send in an alternating manner. Alicemay save each of the first and second values,in memory. Memorymay be embodied as a shift register. In particular, Alicememorizes at what specific clock cycle a first or second value,has been sent. This can be achieved by putting each first and second value in the shift register. Alicemay send the first and second values,at each clock cycle of the clock system, and memorizes for each clock cycle if she sends a first valueor a second value. The saving or memorizing of the first and second values is done for at least a duration that corresponds to the estimated round-trip latency value.

452 410 410 454 456 452 410 458 402 450 458 410 402 452 410 456 452 458 410 402 458 458 456 452 458 460 462 460 458 454 452 462 460 456 452 410 462 456 452 402 460 458 410 When first test signalarrives at Bob, Bobdetects the first and second values,of the first test signal. Bobsends back a validating signalto Alicethrough optical fiber. In an embodiment the validating signalis sent from Bobto Alicedirectly upon receiving first test signal. Every time Bobdetects a second valueof first test signal, validating signalsends back the detection information from Bobto Alice. This validating signalcan be any signal, as long as Alice is configured to recognize how the validating signalencodes a detection of the second valueof the first test signal. In the illustrated embodiment, the validating signalcomprises first valuesand second values, wherein a first valueof the validating signalcorresponds to a detection of a first valueof the first test signaland a second valueof the validating signalcorresponds to a detection of a second valueof the first test signal. It is clear for the skilled person that it is also possible for Bobto only send second valuesthat correspond to a detection of a second valueof the first test signalto Aliceand refrain from sending the first values. In an embodiment the validating signalis sent to Bobwith a Manchester encoded clock signal.

458 402 402 458 454 456 452 402 402 458 452 458 402 454 456 402 458 410 2 FIG. The validating signalarrives at Alice. Alicehas to link the detections from the validating signalto first or second values,of the first test signalthat were sent by Aliceat an earlier time. This can be done by Alicesetting an estimated round-trip latency value. The estimated round-trip latency value is a number of clock cycles of the clock unit. This estimated round-trip latency value is represented as a binary number. At the time of setting the first round-trip latency it is not known if the estimated round-trip latency value is the actual round-trip latency value as explained in. When a second value from the validating signalis received, it may be determined, upon registering that the validating signal comprises the second value, if an output of the shift register is a first or second value. As the shift register has a length that corresponds to the estimated round-trip latency value, the determined first or second value of the output of the shift register corresponds to a first or second value of the first test signalthat was sent an estimated round-trip latency value earlier than the clock cycle on which the second value of the validating signalhas been received. In this way, Alicecan identify which first or second values,which were sent by Alicecorrespond to the second values from the validating signalreceived from Bob.

462 458 456 452 340 402 462 458 454 452 340 402 340 402 462 458 454 452 402 In case the second valuesfrom the validating signalare linked to second valuesfrom the first test signal, the FPGAof Alicemay determine that the least significant bit of the estimated round-trip latency value is correct. In case the second valuesfrom the validating signalare linked to first valuesfrom the first test signal, the FPGAof Alicemay determine that the least significant bit of the estimated round-trip latency value is incorrect. If the least significant bit of the first round-trip latency is determined to be incorrect, the FGPAof Alicemay flip the least significant bit. Flipping a bit in the present invention means changing the value of a bit from either 0 to 1 or from 1 to 0. For example, if the least significant bit of the estimated round-trip latency value is 0, and the second valuesof the validating signalare linked to first valuesfrom the first test signal, the least significant bit is changed to 1. The determination of the least significant bit being correct or incorrect can be understood as Alicedetermining if the actual round-trip latency is a multiple of two clock cycles.

452 454 456 462 456 456 462 In an embodiment, Alice sends during a first period the first test signalwith alternating first and second values,, and counts the amount of times the second valuesof the validating signal are linked to a second valueof the test signal. If a ratio between the number of times that a correct link between the second values,is determined versus the number of times that an incorrect link is determined is below a lower predetermined threshold, the controller of Alice may determine that the least significant bit is incorrect and flip the least significant bit. If a ratio between the number of times that a correct link is determined versus the number of times that an incorrect link is determined is above a higher predetermined threshold, the controller of Alice may determine that the least significant bit is correct.

4 FIG.B 402 464 446 466 468 466 468 468 466 464 410 410 466 468 464 410 470 402 450 410 468 464 470 410 402 470 472 474 472 470 466 464 474 470 468 464 During a second time (), Alicemay send a second test signalthrough optical fiberthat also comprises first valuesand second values. The first and second values,are sent with each second valuebeing preceded by three first valuesrepeatedly. When second test signalarrives at Bob, Bobdetects the first and second values,of the second test signal. Bobsends back a validating signalto Alicethrough optical fiber. Every time Bobdetects a second valueof second test signal, validating signalsends back the detection information from Bobto Alice. In the illustrated embodiment, the validating signalcomprises first valuesand second values, wherein a first valueof the validating signalcorresponds to a detection of a first valueof the second test signaland a second valueof the validating signalcorresponds to a detection of a second valueof the second test signal.

402 470 466 468 464 402 402 468 464 474 470 410 402 402 Alicelinks the detections from the validating signalto first or second values,of the second test signalthat were sent by Aliceat an earlier time determining which first or second value is output from the shift register. Alicemay then check if the second valuesfrom the second test signalcorrespond to the second valuesfrom validating signalsent by Bob. Alicemay then determine if the second-to-least significant bit of the estimated round-trip latency value is correct. The determination of the least significant bit being correct or incorrect can be understood as Alicedetermining if the estimated round-trip latency is off by a multiple of two clock cycles compared to the actual round-trip latency.

4 FIG.B 402 476 446 478 480 478 480 480 478 476 410 410 478 480 476 410 482 402 450 410 480 476 482 410 402 482 484 486 484 482 478 476 486 482 480 476 During a third time (), Alicemay send a third test signalthrough optical fiberthat also comprises first valuesand second values. The first and second values,are sent with each second valuebeing preceded by seven first valuesrepeatedly. When third test signalarrives at Bob, Bobdetects the first and second values,of the third test signal. Bobsends back a validating signalto Alicethrough optical fiber. Every time Bobdetects a second valueof third test signal, validating signalsends back the detection information from Bobto Alice. In the illustrated embodiment, the validating signalcomprises first valuesand second values, wherein a first valueof the validating signalcorresponds to a detection of a first valueof the third test signaland a second valueof the validating signalcorresponds to a detection of a second valueof the third test signal.

402 482 478 480 476 402 402 480 476 486 482 410 402 402 Alicelinks the detections from the validating signalto first or second values,of the third test signalthat were sent by Aliceat an earlier time by subtracting the estimated round-trip latency value. Alicemay then check if the second valuesfrom the third test signalcorrespond to the second valuesfrom validating signalsent by Bob. Alicemay then determine if the second-to-least significant bit of the first round-trip latency is correct. The determination of the second-to-least significant bit being correct or incorrect can be understood as Alicedetermining if the estimated round-trip latency is off by a multiple of four clock cycles compared to the actual round-trip latency.

4 FIGS.A-C n th th n−1 402 410 The method according to the present disclosure further comprises repeating the steps that are disclosed in, with the difference that in each subsequent test signal the number of first values preceding the second values is increased according to the formula 2−1 first values preceding a second value for the ntest signal. In this way, the ntest signal determines if the estimated round-trip latency is off by a multiple of 2clock cycles compared to the actual round-trip latency. These steps can be repeated until a certain upper round-trip latency estimation threshold has been reached. In case the testing signal and validating signal are optical signals, the upper round-trip latency estimation threshold may be determined based on the distance between Aliceand Bobmultiplied by a certain factor, for example 10, divided by the speed of light.

5 FIG. depicts a simplified example of the method of the present invention. It is noted that this example is only for conceptual illustrative purposes, and does not necessarily correspond to a working embodiment of the invention.

590 590 552 402 558 402 552 554 556 558 560 562 558 In the following situations A, B and C the actual round-trip latency value is 3 clock cycles, which can be represented by binary number 011. In situation A, an estimated round-trip latency valueis set. The estimated round-trip latency valueis zero clock cycles and is represented as the binary number 000. First testing signalis sent by Aliceand validating signalis received by Alice. First test signalcomprises alternating first valuesand second values. Validating signalcomprises alternating first valuesand second values. The actual round-trip latency value of three clock cycles is represented by the three x's in front of validating signal.

402 402 554 556 560 562 554 556 560 562 402 554 562 554 562 556 560 402 590 a a As Aliceassumes that there is no latency, Alicewill link every first or second value,that is sent at a certain clock cycle to the incoming first or second value,at that same certain clock cycle. In other words, the estimated sent time value is equal to the received time value. The first and second values,,,that are linked to each other by Aliceare put directly above each other. For example, first valueis linked to second value. As can be seen in situation A, first valuesare linked to second valuesand second valuesare linked to first values. Therefore, Alicedetermines that the least significant bit of the estimated round-trip latency valueis incorrect, and the bit is flipped.

592 592 564 566 568 572 574 564 570 402 566 572 568 572 402 592 In situation B the estimated round-trip latency valueis one clock cycle, represented by binary number 001. The estimated round-trip latency valueof one clock cycle is represented by the one x in front of test signal. The first and second values,,,from second test signaland validating signalthat are linked to each other by Aliceare put directly above each other. As can be seen in situation B, first valuesare still linked to second valuesand second valuesare still linked to first values. Therefore, Alicedetermines that the second-to-least significant bit of the estimated round-trip latency valueis incorrect, and the bit is flipped.

594 594 576 578 580 584 586 576 582 402 578 584 580 586 402 594 In situation C the estimated round-trip latency valueis three clock cycles, represented by binary number 011. The estimated round-trip latency valueof three clock cycles is represented by three x's in front of test signal. The first and second values,,,of third test signaland validating signalthat are linked to each other by Aliceare put directly above each other. As can be seen in situation C, first valuesare linked to first valuesand second valuesare linked to first values. Therefore, Alicedetermines that the third-to-least significant bit of the estimated round-trip latency valueis correct.

Every subsequent test signal, for example with a second value being preceded by fifteen first values, will result in a correct linking of first values with first values and second values with second values. After a predetermined upper latency threshold, the method may end with sending testing signals and determine that the actual round-trip latency is three clock cycles.

6 FIG. 602 604 606 608 610 612 614 616 depicts a method according to the present disclosure. In stepa first estimated round-trip latency value is set by the first device, wherein the estimated round-trip latency value is represented as a binary number. In stepa first test signal is generated and send by the first device to the second device, during a first period, wherein the first test signal comprises alternating first values and second values, wherein first and second values are sent at each clock cycle of the clock unit. In stepa sent time value of each first and second value of the first test signal is saved by the first device. In stepthe first test signal is received at the second device. In stepa validating signal that is generated by the second device and is based on the first test signal is sent, by the second device to the first device, upon receiving the first test signal, wherein the validating signal comprises at least second values when second values from the first test signal are received. In stepthe validating signal is received at the first device at a received time value. In stepthe validating signal is compared with the first test signal sent during the first period. In stepit is determined if the estimated round-trip latency value is correct based on the comparing of the validating signal and the first test signal.

7 FIG. 712 714 718 720 722 724 726 728 depicts a further method according to the present disclosure. In stepthe validating signal is received at the first device at a received time value. In stepthe validating signal is compared with the first test signal sent during the first period. In stepit is determined if the least significant bit is correct. If the least significant bit is not correct, the least significant bit is flipped in step. After flipping the least significant bit, or after determining that the least significant is correct, the validating signal is compared with the second test signal sent during the second period in step. In stepit is determined if the second-to-least significant bit is correct. If the second-to-least significant bit is not correct, the least significant bit is flipped in step. After flipping the least significant bit, or after determining that the least significant is correct, the validating signal is compared with the third test signal sent during the second period in step.

The present disclosure is by no means limited to the above described preferred embodiments thereof. The rights sought are defined by the following claims within the scope of which many modifications can be envisaged.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.