Robust link synchronization in ethernet networks

This application claims the benefit of U.S. Provisional Patent Application No. 63/292,740, entitled “Enhancing Robustness of Link Synchronization in Automotive Ethernet at 802.3cy-Part II,” filed on Dec. 22, 2021, which is hereby incorporated herein by reference in its entirety.

The present disclosure relates generally to Ethernet communication systems, and more particularly to synchronization between network devices in an Ethernet communication system operating in a noisy environment.

Modern vehicles, such as advanced automobiles, have begun using automotive Ethernet technologies to connect components over a wired physical network within the vehicle. One important requirement for an automotive Ethernet network is a start-up time of the components of the Ethernet network. Typically, vehicle network components are required to be linked-up and operational within a certain period of time after start-up of the vehicle, for example within a hundred or several hundreds of milliseconds after start-up of the vehicle, to allow the vehicle to be fully operational within a certain time, such as within no more than two seconds, after start-up of the vehicle. A link-up process in a typical automotive application includes a synchronization stage followed by a training stage. During the synchronization stage, a device that is operating as a primary device sequentially transmits one or more synchronization signals with transmission pauses separating respective transmissions of the synchronization signals. When a device operating as a secondary device detects a synchronization signal transmitted by the primary device, the secondary device transmits a synchronization response signal to the primary device. After the primary device detects the synchronization response signal from the secondary device, the primary device stops transmission of its synchronization signals to the secondary device. Once this exchange of synchronization signals between the primary device and the secondary device is completed, the primary device initiates the training stage of the link up process by transmitting a training signal to the secondary device.

In an embodiment, a method for synchronizing a first network interface device and a second network interface device via a communication link includes: receiving, at the first network interface device, a first synchronization signal transmitted by the second network interface device, the first synchronization signal being for synchronizing the first network interface device and the second network interface device via the communication link; in response to detecting the first synchronization signal from the second network interface device, starting a timer of the first network interface device, the timer being configured to expire after transmission of the first synchronization signal by the second network interface device has ended; and in response to the timer expiring, transmitting, by the first network interface device, a synchronization response signal to the second network interface device.

In another embodiment, a communication device comprises: a first network interface device configured to communicatively couple with a second network interface device via a communication link, the first network interface device including a physical layer (PHY) processor, implemented at least partially on one or more integrated circuit (IC) chips. The PHY processor includes a timer implemented on the one or more IC chips. The one or more IC chips are configured to: receive a first synchronization signal transmitted by the second network interface device, the first synchronization signal being for synchronizing the first network interface device and the second network interface device via the communication link; in response to detecting the first synchronization signal from the second network interface device, start the timer of the first network interface device, the timer being configured to expire after transmission of the first synchronization signal by the second network interface device has ended; and in response to the timer expiring, control the first network interface device to transmit a synchronization response signal to the second network interface device.

In various embodiments described below, link establishment between a first network device (e.g., a primary device) and a second network device (e.g., a secondary device) in an Ethernet network includes the primary device transmitting a first synchronization signal to the secondary device. In response to the secondary device detecting the first synchronization signal, the secondary device transmits a second synchronization signal to the primary device. The link establishment also includes the primary device detecting the second synchronization signal from the secondary device. To avoid the secondary device starting transmission of the second synchronization signal before the primary device has completed transmitting the first synchronization signal, which may lead to the primary device failing to detect the second synchronization signal, the secondary device waits a determined time period after detecting the first synchronization signal before starting transmission of the second synchronization signal, according to some embodiments.

1 FIG. 100 100 102 104 106 102 104 102 104 is a block diagram of an example communication networkin which a first communication device (e.g., a primary device) and a second communication device (e.g., a secondary device) communicate via a communication link (e.g., an Ethernet communication link), according to an embodiment. The communication networkincludes a first network interface devicecoupled to a second network interface devicevia a communication link. In an embodiment, the first network interface deviceand the second network interface deviceare generally configured to operate according to an automotive Ethernet standard, such as an IEEE 802.3 standard. In another embodiment, the first network interface deviceand the second network interface deviceare generally configured to operate according to one or more other suitable communication protocols.

102 104 102 104 102 104 106 102 104 106 106 102 104 102 104 The first network interface deviceand the second network interface devicesare associated with electronic devices of an automotive network system, in an embodiment. As just an illustrative example, the first network interface deviceis a component of, or coupled to, a central controller (including a central processing unit) in an automobile, and the second network interface deviceis a component of or coupled to an accessory device, such as a camera or a telematics radio device, in the automobile, in an embodiment. In other embodiments, the first network interface deviceand/or the second network interface deviceare associated with other suitable electronic devices in an automobile, such as an infotainment device, a sensor device (e.g., a lidar device, a radar, an audio sensor, a video sensor, a proximity sensor, etc., a control device, etc. in the automobile. The network linkbetween the network interface deviceand the network interface devicecomprises a single twisted pair copper link, in an embodiment. In another embodiment, the network linkis a suitable link different from a single twisted pair copper link. For example, the network linkis a multi-pair copper link, an optical link, a fiber link, a radio frequency plastic waveguide link, etc., in various embodiments. In some embodiments, the first network interface deviceand the second network interface deviceare utilized in a suitable network other than an automotive network. For example, in some embodiments, the first network interface deviceand the second network interface deviceare utilized in an industrial control network or process plant network.

102 130 130 130 180 106 102 132 132 130 102 132 132 102 132 102 132 130 130 The network interface deviceincludes one or more physical layer (PHY) processors(sometimes referred to herein as “the PHY processor” for brevity). The PHY processorincludes a transceiverconfigured to transmit and receive signals over the link. The network interface devicealso includes one or more media access control (MAC) processors(sometimes referred to herein as “the MAC processor” for brevity) coupled to the PHY processor, in an embodiment. In another embodiment, the network interface deviceomits the MAC processor. For example, the MAC processoris external to the network interface device, in an embodiment. In various embodiments in which the MAC processoris external to the network interface device, the MAC processormay be co-located on a same printed circuit board (PCB) as the PHY processor, or may be located on a separated PCB from the PHY processor.

130 130 130 130 The PHY processorincludes one or more encoder devices (not shown), a scrambler device (not shown), and a modulator (not shown) for encoding, scrambling, and modulating data as part of generating a transmission signal, according to an embodiment. The PHY processoralso includes a demodulator (not shown), a de-scrambler device (not shown), and one or more decoder devices (not shown) for demodulating, de-scrambling, and decoding as part of generating the received data, according to an embodiment. In some embodiments, the PHY processing devicealso includes an analog to digital converter (hereinafter “ADC”, not shown) that converts an analog signal received via the communication medium to a digital signal. In some embodiments, the PHY processoralso includes a digital signal processor (hereinafter “DSP”, not shown) that processes the digital signal to generate a signal corresponding to modulation symbols that are then demodulated by the demodulator (not shown).

102 130 132 130 132 102 130 132 The network interface deviceis implemented using one or more integrated circuit (IC) chips configured to operate as discussed below. For example, the PHY processormay be implemented, at least partially, on a first IC chip, and the MAC processormay be implemented, at least partially, on a second IC chip. As another example, at least a portion of the PHY processorand at least a portion of the MAC processormay be implemented on a single IC chip. For instance, the network interface devicemay be implemented using a system on a chip (SoC), where the SoC includes at least a portion of the PHY processorand at least a portion of the MAC processor. In an embodiment in which various IC chip components are implemented on different IC chips, the IC chips may be packaged together to form a single network interface device.

104 150 150 150 190 106 104 152 152 150 104 152 152 104 152 104 152 150 150 The network interface deviceincludes one or more physical layer (PHY) processors(sometimes referred to herein as “the PHY processor” for brevity). The PHY processorincludes a transceiverconfigured to transmit and receive signals over the link. The network interface devicealso includes one or more media access control (MAC) processors(sometimes referred to herein as “the MAC processor” for brevity) coupled to the PHY processor, in an embodiment. In another embodiment, the network interface deviceomits the MAC processor. For example, the MAC processoris external to the network interface device, in an embodiment. In various embodiments in which the MAC processoris external to the network interface device, the MAC processormay be co-located on a same printed circuit board (PCB) as the PHY processor, or may be located on a separated PCB from the PHY processor.

150 150 150 150 The PHY processorincludes one or more encoder devices (not shown), a scrambler device (not shown), and a modulator (not shown) for encoding, scrambling, and modulating data as part of generating a transmission signal, according to an embodiment. The PHY processoralso includes a demodulator (not shown), a de-scrambler device (not shown), and one or more decoder devices (not shown) for demodulating, de-scrambling, and decoding as part of generating the received data, according to an embodiment. In some embodiments, the PHY processoralso includes an analog to digital converter (hereinafter “ADC”, not shown) that converts an analog signal received via the communication medium to a digital signal. In some embodiments, the PHY processoralso includes a digital signal processor (hereinafter “DSP”, not shown) that processes the digital signal to generate a signal corresponding to modulation symbols that are then demodulated by the demodulator (not shown).

104 150 152 150 152 104 150 152 The network interface deviceis implemented using one or more IC chips configured to operate as discussed below. For example, the PHY processormay be implemented, at least partially, on a first IC chip, and the MAC processormay be implemented, at least partially, on a second IC chip. As another example, at least a portion of the PHY processorand at least a portion of the MAC processormay be implemented on a single IC chip. For instance, the network interface devicemay be implemented using an SoC, where the SoC includes at least a portion of the PHY processorand at least a portion of the MAC processor. In an embodiment in which various IC components are implemented on different IC chips, the IC chips may be packaged together to form a single network interface device.

130 150 100 130 102 102 130 150 104 104 150 In various embodiments, a PHY processor (e.g., the PHY processor,) in the systemcan be configured either as a primary PHY processor or a secondary PHY processor. A primary PHY processor uses a free running local clock to determine the timing of transmitter operations, in an embodiment. A secondary PHY processor recovers the clock from the signal received from the primary PHY processing device and uses the received signal to determine the timing of transmitter operations. Furthermore, the primary PHY processor and the secondary PHY processor are configured to synchronize their clocks and timing of transmitter operations during a synchronization phase before entering normal data transmission phase. In various embodiments, synchronization among sensors in an automotive network ensures that inputs from a plurality of various sensors distributed through a vehicle can be combined into an accurate comprehensive representation of events impacting the vehicle. As an example, the PHY processorof the network interface device(sometimes referred to herein as “primary network interface device”) is configured as a primary PHY processor (sometimes referred to herein as “primary PHY processor”), and the PHY processorof the network interface device(sometimes referred to herein as “secondary network interface device”) is configured as a secondary PHY processor (sometimes referred to herein as “secondary PHY processor”), in an embodiment.

130 182 184 182 186 150 130 180 186 150 106 102 104 180 188 150 106 102 104 184 188 150 184 186 104 102 188 102 104 The primary PHY processorincludes a link synchronization controllerand a synchronization signal detector, in an embodiment. The link synchronization controlleris configured to generate one or more synchronization signalsto enable the secondary PHY processorto synchronize operations with the primary PHY processor, in an embodiment. The transceiveris configured to transmit the one or more synchronization signalsto the secondary PHY processorover the network linkduring a synchronization phase of link establishment between the network interface deviceand the network interface device, in an embodiment. The transceiveris also configured to receive one or more synchronization signalsfrom the secondary PHY processorover the network linkduring the synchronization phase of link establishment between the network interface deviceand the network interface device, in an embodiment. The synchronization signal detectoris configured to detect a synchronization signalreceived from the secondary PHY processor, in an embodiment. For example, in an embodiment, the synchronization signal comprises a known periodic pseudorandom sequence. In an embodiment, the synchronization signal detectoris configured to perform correlation of a received signal with the known periodic pseudorandom sequence and determine that the received signal is a synchronization signal if the correlation result is above a detection threshold. Transmission of the synchronization signalfacilitates the network interface devicediscovering the network interface deviceduring the synchronization phase of the link establishment process, and transmission of the synchronization signalfacilitates the network interface devicediscovering the network interface deviceduring the synchronization phase of the link establishment process.

182 184 182 184 In an embodiment, the link synchronization controllerand/or the synchronization signal detectoris implemented by a processor configured to execute machine readable instructions stored in a memory device (not shown) such as a RAM, a ROM, a flash memory, etc. In an embodiment, the link synchronization controllerand/or the synchronization signal detectoradditionally or alternatively includes hardware circuitry (e.g., one or more of correlation circuitry, a hardware state machine, etc.) that is configured to generate and/or detect synchronization signals such as described herein.

150 192 194 190 150 186 130 102 104 194 130 194 The secondary PHY processorincludes a link synchronization controllerand a synchronization signal detector, in an embodiment. The transceiverof the secondary PHY processoris configured to receive a synchronization signaltransmitted by the primary PHY processorduring the synchronization phase of link establishment between the network interface deviceand the network interface device. The synchronization signal detectoris configured to detect a synchronization signal received from the primary PHY processor, in an embodiment. For example, in an embodiment, the synchronization signal comprises a known periodic pseudorandom sequence. In an embodiment, the synchronization signal detectoris configured to perform correlation of a received signal with the known periodic pseudorandom sequence and determine that the received signal is a synchronization signal if the correlation result is above a detection threshold.

192 196 192 196 194 186 102 192 196 188 130 196 188 186 102 102 188 The link synchronization controllerincludes a timer. The link synchronization controlleris configured to start the timerin response to the synchronization signal detectordetecting the synchronization signalfrom the network interface device. The link synchronization controlleris configured to, in response to the timerexpiring, a synchronization signal(sometimes referred to herein as a “synchronization response signal”) to the primary PHY processor. As will be described further below, the timeris configured to measure a time period that ensures that transmission of the synchronization response signalbegins only after transmission of the synchronization signalby the network interface devicehas ended, to improve a probability that the network interface devicedetects the synchronization response signal.

192 188 130 196 188 192 150 188 150 130 188 130 106 130 150 In some embodiments, the link synchronization controlleris configured to transmit a fixed number of multiple synchronization response signalsto the primary PHY processorin response to the timerexpiring. In an embodiment, the fixed number synchronization response signalsthat the link synchronization controlleris configured to transmit is configurable and/or programmable in the secondary PHY processor. Transmission of multiple synchronization response signalsfrom the secondary PHY processorto the primary PHY processorincreases the probability of detection of a synchronization signalat the primary PHY processor, for example in the presence of transient noise on the network linkbetween the primary PHY processorand the secondary PHY processor, in at least some embodiments.

192 194 192 194 In an embodiment, the link synchronization controllerand/or the synchronization signal detectoris implemented by a processor configured to execute machine readable instructions stored in a memory device (not shown) such as a RAM, a ROM, a flash memory, etc. In an embodiment, the link synchronization controllerand/or the synchronization signal detectoradditionally or alternatively includes hardware circuitry (e.g., one or more of correlation circuitry, a hardware state machine, etc.) that is configured to generate and/or detect synchronization signals such as described herein.

2 FIG. 1 FIG. 1 FIG. 1 FIG. 200 200 102 104 100 200 100 200 100 is an example timing diagram of a synchronization signal exchange sequence, according to an embodiment. The synchronization signal exchange sequenceis performed during a synchronization phase of a link establishment process for establishing a communication link between the network interface deviceand second network interface deviceof the systemof, according to an embodiment. For case of explanation, the synchronization signal exchange sequenceis described in the context of the systemof. In other embodiments, the synchronization signal exchange sequenceis utilized in a process of establishing a communication link in systems different from the systemof.

130 102 210 150 104 106 210 186 210 150 130 210 130 210 1 FIG. The primary PHY processorof the network interface deviceinitiates the synchronization signal exchange sequence by transmitting one or more synchronization signalsto the secondary PHY processorof the network interface deviceover the link. The one or more synchronization signalscorrespond to the one or more one or more synchronization signalsof, in an embodiment. The one or more synchronization signalsare generally used to synchronize operations of the secondary PHY processorwith the primary PHY processor, in an embodiment. In an embodiment, each respective synchronization signalcomprises a pseudorandom sequence transmitted by the maser PHY processor. In another embodiment, each respective synchronization signalcomprises a suitable synchronization signal different from a pseudorandom sequence.

130 210 130 150 130 150 210 The primary PHY processoris configured to transmit the one or more synchronization signalsuntil the primary PHY processorreceives and detects a synchronization response signal from the secondary PHY processor, in an embodiment. The primary PHY processoris configured to, in response to detecting a synchronization response signal from the secondary PHY processor, stop transmission of the synchronization signalsand transition into a state for a next phase (e.g., a training phase) of the link establishment process, such as a check link state for a link check phase of the link establishment process, in an embodiment.

150 150 210 130 210 130 150 212 210 102 102 212 192 196 194 210 102 In an embodiment, the secondary PHY processoris in a signal detection wait mode until the secondary PHY processordetects a synchronization signalfrom the primary PHY processor. In response to detecting a synchronization signalfrom the primary PHY processor, the secondary PHY processorstarts a timer. The timer is configured to measure a time period that ensures that transmission of the synchronization response signalbegins only after transmission of the synchronization signalby the network interface devicehas ended, to improve a probability that the network interface devicedetects the synchronization response signal. For example, the link synchronization controllerstarts the timerin response to the synchronization signal detectordetecting the synchronization signalfrom the network interface device.

150 212 130 192 212 130 196 212 150 212 In response to the timer expiring, the secondary PHY processorinitiates transmissions of the synchronization response signalto the primary PHY processor, in an embodiment. For example, the link synchronization controllertransmits the synchronization response signalto the primary PHY processorin response to the timerexpiring. In an embodiment, the synchronization response signalcomprises a pseudorandom sequence transmitted by the secondary PHY processor. In another embodiment, each respective synchronization response signalcomprises a suitable synchronization signal different from a pseudorandom sequence.

210 104 102 212 102 104 Transmission of the synchronization signalfacilitates the network interface devicediscovering the network interface deviceduring the synchronization phase of the link establishment process, and transmission of the synchronization signalfacilitates the network interface devicediscovering the network interface deviceduring the synchronization phase of the link establishment process.

150 212 130 150 212 130 212 150 130 212 150 106 212 130 106 130 212 106 212 130 150 212 130 212 130 150 130 150 In an embodiment, the secondary PHY processortransmits multiple synchronization response signalsto the primary PHY processor. For example, the secondary PHY processoris configured to transmit a fixed (e.g., configurable and/or programmable) number of synchronization response signalsto the primary PHY processor. In an embodiment, transmission of multiple synchronization signalsfrom the secondary PHY processorto the primary PHY processorincreases probability of detection of one of the synchronization response signalstransmitted by the secondary PHY processor, for example in the presence of noise on the link. For example, if one or more initial synchronization response signalsare not detected by the primary PHY processordue, for example, to noise in the link, the primary PHY processormay detect a subsequent one of the multiple synchronization response signalsonce noise subsides on the link. Moreover, because upon detection of the synchronization response signalthe primary PHY processorenters a next phase of the link establishment procedure, and is not expecting reception of a synchronization response signal from the secondary PHY processor, transmission of additional synchronization response signalsdoes not negatively affect operation of the primary PHY processoror delay completion of link establishment, in at least some embodiments. Upon completion of transmission of the multiple synchronization response signalsto the primary PHY processor, the secondary PHY processortransitions to a next phase of link establishment, such as a training phase of link establishment. The primary PHY processorand the secondary PHY processorare then synchronized and ready to begin the next phase of link establishment, such as the training phase of link establishment, in an embodiment.

3 FIG. 3 FIG. 300 304 is a timing/state diagram illustrating a problem that may occur during a link establishment process as proposed for the IEEE 802.3cy automotive Ethernet standard, which is now in development. In particular,illustrates a state transition sequenceof a primary device and a state transition sequenceof a secondary device during a link establishment process proposed for the IEEE 802.3cy automotive Ethernet standard.

300 308 308 312 312 316 316 312 312 316 The state transition sequencebegins with the primary device being in a transmit disable state. The primary device initiates the transmit disable stateupon power-up, for example. The primary device then transitions to a transmit synchronization signal (Tx_Send_S) stateduring which the primary device transmits one or more synchronization signals (e.g., SEND_S signals) for a defined time period (e.g., proposed to be 1.25 μs±0.05 μs for the IEEE 802.3cy automotive Ethernet standard). When the Tx_Send_S stateends, the primary device transitions to a signal detect wait (SigDet_Wait) stateduring which the primary device quiets transmissions by the primary device and waits to receive a synchronization response signal from the secondary device. If the primary device does not detect a synchronization response signal from the secondary device, the primary device remains in the SigDet_Wait statefor a defined time period (e.g., proposed to be 5 μs±0.15 μs for the IEEE 802.3cy automotive Ethernet standard), and then transitions back to the Tx_Send_S state. The primary device may switch between the Tx_Send_S stateand the SigDet_Wait statemultiple times until the primary device detects a synchronization response signal from the secondary device.

316 3 FIG. 3 FIG. If during the SigDet_Wait statethe primary device detects a synchronization response signal from the secondary device, then the primary device transitions to a pause state (not shown in) to complete the synchronization procedure. The primary device then enters a link check state (not shown in) to perform a link check as part of a link establishment between the primary device and the secondary device.

3 FIG. 300 304 352 322 354 354 356 356 With continued reference to, similar to the state transition sequenceimplemented by the primary device, the state transition sequenceimplemented by the secondary device begins with the secondary device in a transmit disable state. Immediately following the transmit disable state, the secondary device enters a signal detect wait state. The secondary device remains in the signal detect wait stateuntil the secondary device receives and detects a synchronization signal from the primary device, as indicated by a signal detection signal (send_s_sigdet) generated by the secondary device. In response to send_s_sigdet indicating detection of the synchronization signal from the primary device, the secondary device transitions into a silent wait stateand remains in the silent wait stateuntil the send_s_sigdet indicates the synchronization signal from the primary device is no longer detected.

4 FIG. 4 FIG. 400 is a timing diagramillustrating a send_s_sigdet signal generated by the secondary device in connection with reception of a synchronization signal (SEND_S) from the primary device. The send_s_sigdet signal illustrated inis generated by signal detection circuitry of the secondary device, for example.

According to the IEEE 802.3ch automotive Ethernet standard, a synchronization signal such as the SEND_S signal discussed above comprises a pseudorandom sequence having a length of 255, which is transmitted 20 times. It has been proposed that the IEEE 802.3cy automotive Ethernet use the same synchronization signal as used in the IEEE 802.3ch automotive Ethernet standard.

4 FIG. In some implementations, signal detection circuitry of the secondary device includes a correlator that is configured to detect the pseudorandom sequence of the SEND_S signal. In the example of, an output of a correlator of the signal detection circuitry begins to rise after reception of the SEND_S signal by the secondary device begins, and eventually the correlator output reaches a threshold. In response to the correlator output reaching the threshold, the signal detection circuitry causes send_s_sigdet to transition from a LOW state to a HIGH state to indicate detection of the SEND_S signal. In response to the correlator output falling back below the threshold, the signal detection circuitry causes the send_s_sigdet to transition from the HIGH state back to the LOW state to indicate detection of the SEND_S signal has ended.

Suitable signal detection circuitry will take at least 363 ns to detect the SEND_S signal after transmission of the SEND_S signal begins. Thus, when the primary device transmits SEND_S signals at intervals of 6.25 μs, the time period from when the SEND_S signal transitions from LOW to HIGH until a start of a next SEND_S transition will be at most 5.887 μs.

3 FIG. In some situations and/or with some signal detection circuitry implementations, the send_s_sigdet transitions back to the LOW state earlier than illustrated in. For example, if the link is noisy and/or experiencing interference, the output of the correlator may drop below the detection threshold prior to transmission of the SEND_S signal ending. As another example, the signal detection circuitry may be designed to generate the send_s_sigdet signal to have a short pulse of a fixed duration rather than having the send_s_sigdet signal stay HIGH until the correlator output drops below the detection threshold.

5 FIG. 4 FIG. 500 is a timing diagramillustrating another scenario of a send_s_sigdet signal generated by the secondary device in connection with reception of a synchronization signal (SEND_S) from the primary device. Like, the output of the correlator of the signal detection circuitry begins to rise after reception of the SEND_S signal by the secondary device begins, and eventually the correlator output reaches a threshold. In response to the correlator output reaching the threshold, the signal detection circuitry causes send_s_sigdet to transition from a LOW state to a HIGH state to indicate detection of the SEND_S signal.

4 FIG. Unlike, however, the link between the primary device and the secondary device experiences noise and/or interference during transmission of the SEND_S signal by the primary device. As result, the correlator output drops below the detection threshold before transmission of the SEND_S signal by the primary device has ended. In response to the correlator output falling back below the threshold, the signal detection circuitry causes the send_s_sigdet to transition from the HIGH state back to the LOW state to indicate detection of the SEND_S signal has ended.

3 FIG. 356 358 358 360 Referring again to, the secondary device remains in the silent wait stateuntil the send_s_sigdet indicates the synchronization signal from the primary device is no longer detected. In response to the send_s_sigdet indicating that the synchronization signal from the primary device is no longer detected, the secondary device transitions to a Tx_Send_S state, during which the secondary device sends one or more synchronization response signals (e.g., a SEND_S signal) to the primary device for a defined time period (e.g., proposed to be 1.25 μs±0.05 μs for the IEEE 802.3cy automotive Ethernet standard). When the Tx_Send_S stateends, the secondary device transitions to a pause stateduring which the secondary device quiets transmissions by the secondary device.

3 FIG. 5 FIG. 358 312 y In the scenario illustrated in, the secondary device transitions to Tx_Send_S stateprior to the primary device finishing transmission of the SEND_S signal. For example, a scenario such as illustrated inhas occurred. Thus, the secondary device begins transmitting a synchronization response signal to the primary device before the primary device has finished transmitting the SEND_S signal while the primary is in the Tx_Send_S state. Thus, the primary device may not detect the synchronization response signal transmitted by the secondary device.

3 FIG. 3 4 FIGS.and 3 5 FIGS.- 312 To reduce the probability of the secondary device transmitting a synchronization response signal prior to the primary device ending transmission of the synchronization signal, such as in the scenario illustrated in, the secondary device sets a timer in response to detecting the synchronization signal from the primary device and does not begin transmission of the synchronization response signal until the timer expires, according to some embodiments. Because there is delay between the start of transmission of the synchronization signal by the primary device and when the secondary device first detects the synchronization signal, the timer can be set to a time value that is shorter than a maximum time duration of the synchronization signal from the primary device as specified by a communication protocol. For example, as discussed above with reference toand in the context of the proposed IEEE 802.3cy automotive Ethernet standard, suitable signal detection circuitry at the secondary device will take at least 363 ns to detect the SEND_S signal from the primary device after transmission of the SEND_S signal begins. Additionally, as discussed above with reference to, the proposed IEEE 802.3cy automotive Ethernet standard specifies that the primary device should transmit the SEND_S signal in the Tx_Send_S statefor 1.25 μs±0.05 μs (maximum time duration of 1.30 μs). Thus, the timer could be set to as little as 0.937 μs (1.30 μs-363 ns), in some embodiments corresponding to the proposed IEEE 802.3cy automotive Ethernet standard. In some embodiments, the timer is set to between 73% and 90% of the maximum duration of the synchronization signal from the primary device. In other embodiments, the timer is set to between 75% and 85% of the maximum duration of the synchronization signal from the primary device. In other embodiments, the timer is set to between 75% and 80% of the maximum duration of the synchronization signal from the primary device. In an embodiment corresponding to the proposed IEEE 802.3cy automotive Ethernet standard, the timer is set to approximately 1 μs (i.e., 1 μs±0.05 μs).

In other embodiments, the timer is set to a time value that is longer than a maximum time duration of the synchronization signal from the primary device as specified by the communication protocol. In some embodiments, the timer is set to between 105% and 200% of the maximum duration of the synchronization signal from the primary device. In other embodiments, the timer is set to between 110% and 190% of the maximum duration of the synchronization signal from the primary device. In other embodiments, the timer is set to between 120% and 180% of the maximum duration of the synchronization signal from the primary device.

In other embodiments, the timer is set to a time value that is approximately equal (e.g., within 4%) to a maximum time duration of the synchronization signal from the primary device as specified by the communication protocol.

6 FIG. 6 FIG. 3 FIG. 3 FIG. 300 is a timing/state transition diagram illustrating an example link establishment process, according to an embodiment.is similar to the timing/state diagram of, and like-numbered elements are not described again in detail for purposes of brevity. For example, the state transition sequenceof the primary device is the same as in.

3 FIG. 6 FIG. 354 608 608 608 312 312 312 312 312 312 312 Like the timing/state diagram of, the secondary device remains in the signal detect wait stateuntil the secondary device receives and detects a synchronization signal from the primary device, as indicated by a signal detection signal (send_s_sigdet) generated by the secondary device. In response to send_s_sigdet indicating detection of the synchronization signal from the primary device, the secondary device transitions into a silent wait state. In the silent wait state, the secondary device sets a timer and remains in the silent wait stateuntil the timer expires. In the embodiment illustrate in, which corresponds to the IEEE 802.3cy automotive Ethernet standard now in development, the secondary device sets the timer to approximately 1 μs (i.e., 1 μs±0.05 μs). In other embodiments, the secondary device sets the timer to another suitable time different that approximately 1 μs. For example, in some embodiments, the timer is set to between 73% and 90% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the timer is set to between 75% and 85% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the timer is set to between 75% and 80% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the timer is set to a time value that is longer than a maximum time duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In some embodiments, the timer is set to between 105% and 200% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the timer is set to between 110% and 190% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the timer is set to between 120% and 180% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state.

358 358 312 y 3 5 FIGS.and In response to the timer expiring, the secondary device transitions to a Tx_Send_S state, during which the secondary device sends one or more synchronization response signals (e.g., a SEND_S signal) to the primary device for the defined time period (e.g., proposed to be 1.25 μs±0.05 μs for the IEEE 802.3cy automotive Ethernet standard). Because the secondary device does not transition to the Tx_Send_S stateuntil the timer expires, the secondary device begins transmitting the synchronization response signals only after the primary device has ended transmission of synchronization signals (e.g., the SEND_S signal) while in the Tx_Send_S state, thus avoiding problems such as discussed with reference to.

608 360 When the Tx_Send_S stateends, the secondary device transitions to a pause state.

7 FIG. 1 FIG. 7 FIG. 1 FIG. 1 FIG. 700 130 150 700 130 150 130 150 700 is a state transition diagramillustrating example states and state transitions for operation during a synchronization procedure performed by a PHY processor, according to another embodiment. In an embodiment, the PHY processors,ofare configured to function according to the state diagram, andis generally described with reference tofor ease of explanation. In other embodiments, the PHY processors,ofare configured to function according to another suitable state diagram. Additionally, in other embodiments, a suitable PHY processing device other than the PHY processing devices,is configured to function according to the state diagram.

700 300 604 6 FIG. The state diagramgenerally corresponds to the state transitionsandillustrated in.

702 702 702 702 130 150 130 130 702 704 704 130 130 Initially, the PHY processor operates in a transmit disable state, in an embodiment. The PHY processor enters the transmit disable stateupon power-up or upon initiation of a link establishment procedure, in an embodiment. While in the transmit disable state, the PHY processor enables various modes and initiates various timers for signal synchronization, in the embodiment. For example, the PHY processor starts a break link timer and sets a transmit mode to a send all zeros (Send_Z) mode so that no transmission is performed, in an embodiment. The PHY processor also disables a synchronization link control mode and initiates a send synchronization signal counter (send_s_counter), in an embodiment. Transition from the transmit disable stateto a next state depends on whether the PHY processor is a primary PHY processor (e.g., the primary PHY processor) or a secondary PHY processor (e.g., the secondary PHY processor), in an embodiment. In a scenario in which the PHY processor is a primary PHY processor (e.g., the primary PHY processor), the primary PHY processortransitions from the transmit disable stateto a transmit synchronization signal (Tx_Send_S) state. In the transmit synchronization signal state, the primary PHY processorstarts a send signal (Send_S) timer and sets the transmit mode to send synchronization signal (Send_S) for synchronization signal transmission, in an embodiment. The primary PHY processorthus transmits the synchronization signal until expiration of the send signal timer, in an embodiment.

In an embodiment, the send signal timer measures a time duration of approximately 1.25 μs (i.e., 1.25 μs±0.05 μs; i.e., the maximum time duration is 1.30 μs). In another embodiment, the send signal timer measures a time duration of approximately 1 μs (i.e., 1 μs±0.05 μs; i.e., the maximum time duration is 1.05 μs). In other embodiments, the send signal timer measures another suitable time duration. The time duration measured by the send signal timer corresponds to the duration of the synchronization signal, in an embodiment.

130 706 706 130 130 Upon expiration of the synchronization signal send timer, the primary PHY processortransitions to a signal detection wait state. In the signal detection wait state, the primary PHY processorstarts a signal detection wait timer and sets the transmit mode to the send all zeros (Send_Z) state so that no transmission is performed by the primary PHY processor, in an embodiment.

In an embodiment, the signal detection wait timer measures a time duration of approximately 5 μs (i.e., 5 μs±0.15 μs). In another embodiment, the signal detection wait timer measures a time duration of approximately 4 μs (i.e., 4 μs±0.12 μs; i.e.). In other embodiments, the signal detection wait timer measures another suitable time duration.

706 130 706 130 150 130 708 130 130 130 130 704 704 704 704 704 704 704 With continued reference to the signal detection wait state, if, while the primary PHY processoris in the signal detection wait state, the primary PHY processordetects a synchronization response signal from the secondary PHY processor(send_s_sigdet=true), then the primary PHY processortransitions to a silent wait state. In the silent wait state, the primary PHY processorkeeps the transmit mode in the send all zeros (Send_Z) state so that no transmission is performed by the primary PHY processor. Additionally, the primary PHY processorstarts a silent_wait_timer of the primary PHY processor. In an embodiment, the silent_wait_timer is configured to measure a suitable time period such as discussed above. In some embodiments that corresponds to the IEEE 802.3cy automotive Ethernet standard now in development, the primary device sets the silent_wait_timer to approximately 1 μs (i.e., 1 μs±0.05 μs). In other embodiments, the primary device sets the silent_wait_timer to another suitable time different that approximately 1 μs. For example, in some embodiments, the silent_wait_timer is set to between 73% and 90% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the silent_wait_timer is set to between 75% and 85% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the silent_wait_timer is set to between 75% and 80% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the silent_wait_timer is set to a time value that is longer than a maximum time duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In some embodiments, the silent_wait_timer is set to between 105% and 200% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the silent_wait_timer is set to between 110% and 190% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the silent_wait_timer is set to between 120% and 180% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state.

150 130 710 710 130 In response to the silent_wait_timer expiring and no synchronization response signal from the secondary PHY processorbeing detected, the primary PHY processortransitions to a pause state, in an embodiment. Upon expiration of a signal detect wait timer in the pause state, the primary PHY processortransitions to a link good state, in an embodiment.

706 130 150 130 704 150 130 704 706 130 150 706 On the other hand, if, while in the signal detection wait state, the primary PHY processordoes not detect a synchronization response signal from the secondary PHY processor, then the primary PHY processorloops back to the synchronization transmission stateand transmits another synchronization signal to the secondary PHY processor. The primary PHY processorcontinues transitioning between the synchronization signal transmission stateand the signal detect wait stateuntil the primary PHY processordetects a synchronization response signal from the secondary PHY processorduring the signal detect wait state, in an embodiment.

702 150 150 702 706 706 150 150 150 706 150 130 130 150 708 Referring back to the transmit disable state, in a scenario in which the PHY processor is a secondary PHY processor (e.g., the secondary PHY processor), the secondary PHY processortransitions from the transmit disable stateto the signal detection wait state, in an embodiment. In the signal detection wait state, the secondary PHY processorkeeps the transmit mode in the send all zeros (Send_Z) state so that no transmission is performed by the secondary PHY processor. The secondary PHY processorremains in the signal detect wait stateuntil the secondary PHY processordetects a synchronization signal from the primary PHY processor, in an embodiment. In response to detecting a synchronization signal from the PHY processor, the secondary PHY processortransitions to the silent wait state.

708 150 150 150 150 150 150 708 130 150 706 In the silent wait state, the secondary PHY processorkeeps the transmit mode in the send all zeros (Send_Z) state so that no transmission is performed by the secondary PHY processor. Additionally, the secondary PHY processorstarts a silent_wait_timer of the secondary PHY processor. The silent_wait_timer of the secondary PHY processoris configured to measure a time period such that the secondary PHY processorremains in the silent wait stateat least until the primary PHY processorhas completed transmitting the synchronization signal that was detected while the secondary PHY processorwas in the signal detect wait state.

150 150 704 704 704 704 704 704 704 In an embodiment, the silent_wait_timer is configured to measure a suitable time period such as discussed above. In some embodiments that corresponds to the IEEE 802.3cy automotive Ethernet standard now in development, the secondary PHY processorsets the silent_wait_timer to approximately 1 μs (i.e., 1 μs±0.05 μs). In other embodiments, the secondary PHY processorsets the silent_wait_timer to another suitable time different that approximately 1 μs. For example, in some embodiments, the silent_wait_timer is set to between 73% and 90% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the silent_wait_timer is set to between 75% and 85% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the silent_wait_timer is set to between 75% and 80% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the silent_wait_timer is set to a time value that is longer than a maximum time duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In some embodiments, the silent_wait_timer is set to between 105% and 200% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the silent_wait_timer is set to between 110% and 190% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state. In other embodiments, the silent_wait_timer is set to between 120% and 180% of the maximum duration of the synchronization signal sent by the primary device during the Tx_Send_S state.

130 150 704 704 150 130 704 150 710 710 150 In response to the silent_wait_timer expiring and no synchronization signal from the primary PHY processorbeing detected, the secondary PHY processortransitions to the Tx_Send_S state, in an embodiment. In an embodiment, the Tx_Send_S stateis generally the same for the secondary PHY processoras for the primary PHY processor, in an embodiment. After transmitting the synchronization response signal during the Tx_Send_S state, the secondary PHY processortransitions to the pause state. Upon expiration of a signal detect wait timer in the pause state, the secondary PHY processortransitions to a link good state, in an embodiment.

8 FIG. 8 FIG. 6 FIG. is a timing/state transition diagram illustrating another example link establishment process, according to another embodiment.is similar to the timing/state diagram of, and like-numbered elements are not described again in detail for purposes of brevity.

800 316 812 812 816 3 6 FIGS.and In a state transition sequenceof the primary device, many of the elements are the same as in. After the silent wait state, the primary device transitions to a pause state. The primary device remains in the pause statefor approximately 5 μs and then transitions to a link_good_check state.

800 354 608 608 608 3 6 FIGS.and A state transition sequenceof the secondary device also includes elements that are the same as in. For example, the secondary device remains in the signal detect wait stateuntil the secondary device receives and detects a synchronization signal from the primary device, as indicated by a signal detection signal (send_s_sigdet) generated by the secondary device. In response to send_s_sigdet indicating detection of the synchronization signal from the primary device, the secondary device transitions into the silent wait state. In the silent wait state, the secondary device sets a timer and remains in the silent wait stateuntil the timer expires as discussed above.

854 854 312 a a x 3 5 FIGS.and In response to the timer expiring, the secondary device transitions to a Tx_Send_S state, during which the secondary device sends one or more synchronization response signals (e.g., a SEND_S signal) to the primary device for the defined time period (e.g., proposed to be 1.25 μs±0.05 μs for the IEEE 802.3cy automotive Ethernet standard). Because the secondary device does not transition to the Tx_Send_S stateuntil the timer expires, the secondary device begins transmitting the synchronization response signals only after the primary device has ended transmission of synchronization signals (e.g., the SEND_S signal) while in the Tx_Send_S state, thus avoiding problems such as discussed with reference to.

854 150 858 854 858 858 854 106 106 8 FIG. In an embodiment, upon the timer expiring, the secondary device initiates transmission of a fixed number of synchronization response signals to the primary device during a plurality of Tx_Send_S states. In embodiment, the secondary PHY processorenters a wait state(Sigdet_Wait) between transmission of consecutive synchronization response signals. In the wait state, no transmission is performed by the secondary device, in an embodiment. In an embodiment, the secondary device remains in the wait statefor a duration of a pause time period. In an embodiment, the duration of the wait time period is approximately 5 μs (5 μs±0.2 μs). In another embodiment, the secondary wait time period is of a suitable duration different from approximately 5 μs. In an embodiment, transmission of the fixed number of synchronization response signals to the primary device during the Tx_Send_S statesincreases the probability of detection of a synchronization response signal by the primary device, even in the presence of noise on the link. For example, as illustrated in, if the primary device misses detection of one or more initial synchronization response signals due, for example, to transient noise on the link, the primary device will detect a subsequent synchronization response signal, in an embodiment.

854 862 866 After the secondary device transmits the fixed number of synchronization response signals to the primary device during a plurality of Tx_Send_S states, the secondary device transitions to a pause stateand then transitions to a link_good_check state.

9 FIG. 1 FIG. 9 FIG. 1 FIG. 1 FIG. 900 130 150 900 130 150 130 150 900 is a state transition diagramillustrating example states and state transitions for operation during a synchronization procedure performed by a PHY processor, according to another embodiment. In an embodiment, the PHY processors,ofare configured to function according to the state diagram, andis generally described with reference tofor ease of explanation. In other embodiments, the PHY processors,ofare configured to function according to another suitable state diagram. Additionally, in other embodiments, a suitable PHY processing device other than the PHY processing devices,is configured to function according to the state diagram.

900 800 850 8 FIG. The state diagramgenerally corresponds to the state transitionsandillustrated in.

900 700 7 FIG. The state diagramis similar to the state diagramof, and like-numbered elements are not discussed again in detail for purposes of brevity.

902 702 902 7 FIG. Initially, the PHY processor operates in a transmit disable state, which is similar to the transmit disable stateof, in an embodiment. While in the transmit disable state, the PHY processor enables various modes and initiates various timers for signal synchronization, in the embodiment. For example, the PHY processor initiates a send synchronization signal counter (send_s_counter), in an embodiment.

902 130 150 130 130 902 904 904 130 130 Transition from the transmit disable stateto a next state depends on whether the PHY processor is a primary PHY processor (e.g., the primary PHY processor) or a secondary PHY processor (e.g., the secondary PHY processor), in an embodiment. In a scenario in which the PHY processor is a primary PHY processor (e.g., the primary PHY processor), the primary PHY processortransitions from the transmit disable stateto a transmit synchronization signal (Tx_Send_S) state. In the transmit synchronization signal state, the primary PHY processorstarts a send signal (send_s) timer and sets the transmit mode to send synchronization signal (Send_S) for synchronization signal transmission, in an embodiment. The primary PHY processorthus transmits the synchronization signal until expiration of the send signal timer, in an embodiment.

In an embodiment, the send signal timer measures a time duration of approximately 1.25 μs (i.e., 1.25 μs±0.05 μs; i.e., the maximum time duration is 1.30 μs). In another embodiment, the send signal timer measures a time duration of approximately 1 μs (i.e., 1 μs±0.05 μs; i.e., the maximum time duration is 1.05 μs). In other embodiments, the send signal timer measures another suitable time duration. The time duration measured by the send signal timer corresponds to the duration of the synchronization signal, in an embodiment.

130 906 906 130 130 Upon expiration of the synchronization signal send timer, the primary PHY processortransitions to a signal detection wait state. In the signal detection wait state, the primary PHY processorstarts a signal detection wait timer and sets the transmit mode to the send all zeros (Send_Z) state so that no transmission is performed by the primary PHY processor, in an embodiment.

In an embodiment, the signal detection wait timer measures a time duration of approximately 5 μs (i.e., 5 μs±0.15 μs). In another embodiment, the signal detection wait timer measures a time duration of approximately 4 μs (i.e., 4 μs±0.12 μs; i.e.). In other embodiments, the signal detection wait timer measures another suitable time duration.

906 130 906 130 150 130 708 With continued reference to the signal detection wait state, if, while the primary PHY processoris in the signal detection wait state, the primary PHY processordetects a synchronization response signal from the secondary PHY processor(send_s_sigdet=true), then the primary PHY processortransitions to the silent wait statediscussed above.

906 130 150 130 904 150 130 904 906 130 150 906 If, while in the signal detection wait state, the primary PHY processordoes not detect a synchronization response signal from the secondary PHY processor, then the primary PHY processorloops back to the synchronization transmission stateand transmits another synchronization signal to the secondary PHY processor. The primary PHY processorcontinues transitioning between the synchronization signal transmission stateand the signal detect wait stateuntil the primary PHY processordetects a synchronization response signal from the secondary PHY processorduring the signal detect wait state, in an embodiment.

902 150 150 150 902 906 906 150 150 150 906 150 130 130 150 708 Referring back to the transmit disable state, in a scenario in which the PHY processor is a secondary PHY processor (e.g., the secondary PHY processor), the secondary PHY processorsets a counter (send_s_counter) to zero. Additionally, the secondary PHY processortransitions from the transmit disable stateto the signal detection wait state, in an embodiment. In the signal detection wait state, the secondary PHY processorkeeps the transmit mode in the send all zeros (Send_Z) state so that no transmission is performed by the secondary PHY processor. The secondary PHY processorremains in the signal detect wait stateuntil the secondary PHY processordetects a synchronization signal from the primary PHY processor, in an embodiment. In response to detecting a synchronization signal from the PHY processor, the secondary PHY processortransitions to the silent wait state.

130 150 904 904 150 130 150 130 In response to the silent_wait_timer expiring and no synchronization signal from the primary PHY processorbeing detected, the secondary PHY processortransitions to the Tx_Send_S state, in an embodiment. In an embodiment, the Tx_Send_S stateis similar for the secondary PHY processoras for the primary PHY processorand involves sending a synchronization signal. Additionally, the secondary PHY processorincrements the send_s_counter and determines whether the send_s_counter has reached an end value (min_send_s_count) that corresponds to the transmission of a minimum number of synchronization response signals to the primary PHY device, according to an embodiment.

150 906 150 906 904 150 904 906 130 If the send_s_counter has not yet reached the end value, the secondary PHY processortransitions to the signal detection wait state. The secondary PHY processorremains in the signal detection wait stateuntil the sigdet_wait_timer expires and then returns to the Tx_Send_S state. Thus, the secondary PHY processoralternates between the Tx_Send_S stateand the signal detection wait stateand transmits the minimum number of synchronization response signals to the primary PHY device.

150 130 150 710 When the secondary PHY processordetermines that the minimum number of synchronization response signals has been transmitted to the primary PHY device, the secondary PHY processortransitions to the pause statethat was discussed above.

10 FIG. 1 FIG. 1000 1000 150 1000 is a flow diagram of an example methodfor synchronizing a first network interface device and a second network interface device that are communicatively coupled via a communication link, according to an embodiment. The methodis implemented by a secondary device, such as the secondary PHY processorof, in an embodiment. For ease of explanation, the methodis described herein in the context of the first network interface device being a secondary device (sometimes referred to herein as a “secondary network interface device”) and the second network interface device being a primary device (sometimes referred to herein as a “primary network interface device”).

1000 700 700 1000 900 900 1000 700 900 7 FIG. 9 FIG. In an embodiment, the methodis implemented by a network interface device configured to implement the state machineofand is performed in conjunction with operation of the state machine. In another embodiment, the methodis implemented by a network interface device configured to implement the state machineofand is performed in conjunction with operation of the state machine. In other embodiments, the methodis implemented by a network interface device configured to implement another suitable state machine different than the state machineand the state machine, and is performed in conjunction with operation of the other suitable state machine.

1004 104 150 102 130 210 312 704 904 2 FIG. 6 8 FIGS.and 7 FIG. 9 FIG. At block, the first network interface device receives (e.g., the secondary network interface devicereceives, the secondary PHY processorreceives, etc.) a first synchronization signal transmitted by the second network interface device (e.g., the primary network interface device, the primary PHY processor, etc.). In an embodiment, the first synchronization signal is for synchronizing the first network interface device and the second network interface device via the communication link. In various embodiments, the first network interface device receives the synchronization signalof, the synchronization signal corresponding to any of the Tx_Send_S stateof, the Tx_Send_S stateof, the Tx_Send_S stateof, etc. In other embodiments, the first network interface device receives another suitable first synchronization signal.

1008 104 150 192 196 At block, in response to the first network interface device detecting the first synchronization signal from the second network interface device, the first network interface device starts a timer of the first network interface device. For example, the network interface devicestarts (e.g., PHY processorstarts, the link synchronization controllerstarts, etc.) the timer. The timer is configured to expire after transmission of the first synchronization signal from the second network interface device ends.

In an embodiment, the timer is configured to measure a first time duration that is less than a second time duration of the first synchronization signal and takes into account a delay from when the first network interface device begins receiving the first synchronization signal and when first network interface device detects the first synchronization signal.

In an embodiment, a maximum duration of the first synchronization signal is specified by a communication protocol. In some embodiments, the timer is set to between 73% and 90% of the maximum duration of the first synchronization signal. In other embodiments, the timer is set to between 75% and 85% of the maximum duration of the first synchronization signal. In other embodiments, the timer is set to between 75% and 80% of the maximum duration of the first synchronization signal. In an embodiment corresponding to the proposed IEEE 802.3cy automotive Ethernet standard, the timer is set to approximately 1 μs (i.e., 1 μs±0.05 μs).

In other embodiments, the timer is set to a time value that is longer than the maximum time duration of the first synchronization signal. In some embodiments, the timer is set to between 105% and 200% of the maximum duration of the first synchronization signal. In other embodiments, the timer is set to between 110% and 190% of the maximum duration of the first synchronization signal. In other embodiments, the timer is set to between 120% and 180% of the maximum duration of the first synchronization signal.

1008 708 7 FIG. 9 FIG. In some embodiments, the timer started at blockcorresponds to the silent_wait_timer of state(and/or).

1012 212 358 854 704 904 2 FIG. 6 FIG. 8 FIG. 7 FIG. 9 FIG. a At block, in response to the timer expiring, the first network interface device transmits one or more synchronization response signals to the second network interface device. In various embodiments, the first network interface device transmits the synchronization response signalof, the synchronization signal corresponding to any of the Tx_Send_S stateof, the Tx_Send_S stateof, the Tx_Send_S stateof, the Tx_Send_S stateof, etc. In other embodiments, the first network interface device transmits another suitable synchronization response signal.

1016 1012 1016 1012 1012 At block, after transmission of the synchronization response signal at block, the first network interface device receives a second synchronization signal from the second network interface device. Reception of the second synchronization signal from the second network interface device at block, after transmission of the synchronization response signal at block, generally signifies that the second network interface device missed detection of the synchronization response signal transmitted at block, in an embodiment.

312 y 8 FIG. In an embodiment, the first network interface device receives a synchronization signal corresponding to the Tx_Send_S stateof, etc. In other embodiments, the first network interface device receives another suitable synchronization signal.

1020 1012 1020 1020 At block, after receiving the second synchronization signal from the second network interface device, the first network interface device transmits additional synchronization response signals to the second network interface device until a minimum number of synchronization response signals are transmitted by the first network interface device to the second network interface device. In an embodiment, blocksandcorrespond to the first network interface device transmitting a predetermined fixed number of synchronization response signals to the second network interface device, and the first network interface device continues transmission of synchronization response signals to the second network interface device at blockwithout restarting transmission of the predetermined fixed number of synchronization response signals. Continuing transmission of synchronization response signals to the second network interface device without restarting transmission of the predetermined fixed number of synchronization response signals ensures that the transmission of the predetermined fixed number of synchronization response signals is not restarted due to a false detection of a synchronization signal from the second network interface device after transmission of one or more initial synchronization signals to the second network interface device, in an embodiment.

1016 1020 In some embodiments, blocksand/orare omitted.

Embodiment 1: A method for synchronizing a first network interface device and a second network interface device via a communication link, the method comprising: receiving, at the first network interface device, a first synchronization signal transmitted by the second network interface device, the first synchronization signal being for synchronizing the first network interface device and the second network interface device via the communication link; in response to detecting the first synchronization signal from the second network interface device, starting a timer of the first network interface device, the timer being configured to expire after transmission of the first synchronization signal by the second network interface device has ended; and in response to the timer expiring, transmitting, by the first network interface device, a synchronization response signal to the second network interface device.

Embodiment 2: The method of embodiment 1, wherein: a maximum duration of the first synchronization signal is defined by a communication protocol; and the timer is configured to measure a time duration that is less than the maximum duration of the first synchronization signal.

Embodiment 3: The method of either of embodiments 1 or 2, wherein the timer is configured to take into account a delay between when reception of the first synchronization signal by the first network interface device begins and when the first network interface detects the first synchronization signal.

Embodiment 4: The method of embodiment 2, wherein the timer is configured to measure a time duration between 73% and 90% of the maximum duration of the first synchronization signal defined by the communication protocol.

Embodiment 5: The method of embodiment 4, wherein the timer is configured to measure a time duration between 75% and 85% of the maximum duration of the first synchronization signal defined by the communication protocol.

Embodiment 6: The method of embodiment 5, wherein the timer is configured to measure a time duration between 75% and 80% of the maximum duration of the first synchronization signal defined by the communication protocol.

Embodiment 7: The method of any of embodiments 2 and 4-6, wherein: the communication protocol defines the maximum duration of the first synchronization signal as 1.3 μs; and the timer is configured to measure a time duration of approximately 1 μs.

Embodiment 8: The method of any of embodiments 1-7, further comprising: after transmitting the synchronization response signal, receiving at the first network device a second synchronization signal from the second network interface device; and after receiving the second synchronization signal, transmitting, by the first network interface device, a plurality of additional synchronization response signals to the second network interface device until a minimum number of synchronization response signals are transmitted by the first network interface device to the second network interface device.

Embodiment 9: The method of embodiment 8, further comprising: initializing a send synchronization signal counter at the first network interface device; and incrementing the send synchronization signal counter for each transmission of a respective synchronization response signals to the second network interface device; wherein transmitting the plurality of additional synchronization response signals comprises transmitting additional synchronization response signals until the send synchronization signal counter reaches a fixed predetermined number corresponding to the minimum number of synchronization response signals.

Embodiment 10: The method of either of embodiments 8 or 9, wherein transmitting synchronization response signals includes pausing transmission after respective ones of synchronization response signals, among the synchronization response signals, for a duration of a pause time.

Embodiment 11: A communication device, comprising: a first network interface device configured to communicatively couple with a second network interface device via a communication link, the first network interface device comprising a physical layer (PHY) processor, implemented at least partially on one or more integrated circuit (IC) chips, the PHY processor including a timer implemented on the one or more IC chips. The one or more IC chips are configured to: receive a first synchronization signal transmitted by the second network interface device, the first synchronization signal being for synchronizing the first network interface device and the second network interface device via the communication link; in response to detecting the first synchronization signal from the second network interface device, start the timer of the first network interface device, the timer being configured to expire after transmission of the first synchronization signal by the second network interface device has ended; and in response to the timer expiring, control the first network interface device to transmit a synchronization response signal to the second network interface device.

Embodiment 12: The communication device of embodiment 11, wherein: a maximum duration of the first synchronization signal is defined by a communication protocol; and the timer is configured to measure a time duration that is less than the maximum duration of the first synchronization signal.

Embodiment 13: The communication device of either of embodiments 12 or 13, wherein the timer is configured to take into account a delay between when reception of the first synchronization signal by the first network interface device begins and when the first network interface detects the first synchronization signal.

Embodiment 14: The communication device of embodiment 12, wherein the timer is configured to measure a time duration between 73% and 90% of the maximum duration of the first synchronization signal defined by the communication protocol.

Embodiment 15: The communication device of embodiment 14, wherein the timer is configured to measure a time duration between 75% and 85% of the maximum duration of the first synchronization signal defined by the communication protocol.

Embodiment 16: The communication device of embodiment 15, wherein the timer is configured to measure a time duration between 75% and 80% of the maximum duration of the first synchronization signal defined by the communication protocol.

Embodiment 17: The communication device of any of embodiments 12 and 14-16, wherein: the communication protocol defines the maximum duration of the first synchronization signal as 1.3 μs; and the timer is configured to measure a time duration of approximately 1 μs.

Embodiment 18: The communication device of any of embodiments 11-17, wherein the one or more IC chips are further configured to: after the first network interface device transmits the synchronization response signal, receive a second synchronization signal from the second network interface device; and after receiving the second synchronization signal, control the first network interface device to transmit a plurality of additional synchronization response signals to the second network interface device until a minimum number of synchronization response signals are transmitted by the first network interface device to the second network interface device.

Embodiment 19: The communication device of embodiment 18, wherein: the PHY processor further includes a send synchronization signal counter implemented on the one or more IC chips; and the one or more IC chips are further configured to: initialize the send synchronization signal counter, increment the send synchronization signal counter for each transmission of a respective synchronization response signals to the second network interface device, and transmit the additional synchronization response signals until the send synchronization signal counter reaches a fixed predetermined number corresponding to the minimum number of synchronization response signals.

Embodiment 20: The communication device of either of embodiments 18 or 19, wherein the one or more IC chips are further configured to: pause transmission by the first network interface device after transmission of respective ones of synchronization response signals, among the synchronization response signals, for a duration of a pause time.

At least some of the various blocks, operations, and techniques described above may be implemented utilizing hardware, a processor executing firmware instructions, a processor executing software instructions, or any combination thereof. When implemented utilizing a processor executing software or firmware instructions, the software or firmware instructions may be stored in any suitable computer readable memory such as a random access memory (RAM), a read only memory (ROM), a flash memory, etc. The software or firmware instructions may include machine readable instructions that, when executed by one or more processors, cause the one or more processors to perform various acts.

When implemented in hardware, the hardware may comprise one or more of discrete components, an integrated circuit, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), etc.

While the present disclosure has been described with reference to specific examples, which are intended to be illustrative only and not to be limiting of the invention, changes, additions and/or deletions may be made to the disclosed embodiments without departing from the scope of the invention.