Memory system boot sequence with reduced latency

The present Application for Patent claims priority to U.S. Patent Application No. 63/640,777 by Heath, entitled “MEMORY SYSTEM BOOT SEQUENCE WITH REDUCED LATENCY,” filed Apr. 30, 2024, which is assigned to the assignee hereof, and which is expressly incorporated by reference in its entirety herein.

The following relates to one or more systems for memory, including memory system boot sequence with reduced latency.

Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source.

A host system and a memory system may support different data rates for transferring data between the host system and the memory system. In such examples, the host system and the memory system may negotiate a data rate (e.g., a highest data rate) supported by both systems. For example, the host system and the memory system may negotiate the data rate in response to the memory system transitioning from a first power state to a second power state (e.g., when powering on, after boot-up sequence, after exiting a sleep mode). In some examples, the negotiation between the host system and memory system may incur latency in the boot-up sequence based on increasing the data rate through a defined sequence. For example, a memory system that supports a relatively high data rate may negotiate to an initial data rate and then a next data rate before negotiating to the relatively high data rate (e.g., the highest supported data rate). Some applications (e.g., time-sensitive applications) may benefit from a faster boot-up sequence where the host system accesses data from the memory system to initialize the applications without the latency incurred from negotiating to the highest data rate.

The systems, methods, and techniques described herein may support a host system asserting a signal (e.g., a fast boot signal) to instruct a memory system to boot-up and initially communicate data at a first data rate (e.g., a relatively lower data rate) before negotiating to a higher data rate. Such a process may allow for low-latency dependent applications to be initialized quickly after the boot-up using the first data rate. The later the second data rate may be configured, after the low-latency dependent applications have completed the tasks. For example, the host system may assert the fast boot signal to a pin of the memory system, which may instruct the memory system to boot-up and initially communicate the data at a lowest supported data rate. In some examples, the host system may output the fast boot signal based on an estimated size of the data to be transferred, a dynamic measurement of the data, an application associated with the data, or any combination thereof. Based on transferring the data, the host system and the memory system may negotiate to an increased data rate (e.g., up to the highest supported data rate) as part of the boot-up sequence. By transferring the data to the host system at the first data rate before increasing to a second data rate, the memory system may enable some applications (e.g., a back-up camera feed) to initialize relatively quickly, which may reduce latency and improve the system's overall performance.

In addition to applicability in memory systems as described herein, techniques for a memory system boot sequence with reduced latency may be generally implemented to improve the performance of various electronic devices and systems (including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and gaming). Some electronic device applications, including high-performance applications such as AI, AR, VR, and gaming, may be associated with relatively high processing requirements to satisfy user expectations. As such, increasing processing capabilities of the electronic devices by decreasing response times, improving power consumption, reducing complexity, increasing data throughput or access speeds, decreasing communication times, or increasing memory capacity or density, among other performance indicators, may improve user experience or appeal. Implementing the techniques described herein may improve the performance of electronic devices by transferring data to initialize high-performance applications according to a lower data rate before negotiating to a higher data rate, which may decrease latency times, improve response times, or otherwise improve user experience, among other benefits.

Features of the disclosure are illustrated and described in the context of systems, devices, and circuits. Features of the disclosure are further illustrated and described in the context of a process flow diagram and flowcharts.

1 FIG. 100 100 105 110 100 shows an example of a systemthat supports a memory system boot sequence with reduced latency in accordance with examples as disclosed herein. The systemincludes a host systemcoupled with a memory system. The systemmay be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle, an Internet of Things (IoT) enabled device, an embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

110 110 A memory systemmay be or include any device or collection of devices, where the device or collection of devices includes at least one memory array. For example, a memory systemmay be or include a Universal Flash Storage (UFS) device, an embedded Multi-Media Controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

100 105 110 106 105 105 105 110 105 105 110 110 110 110 105 110 1 FIG. The systemmay include a host system, which may be coupled with the memory system. In some examples, this coupling may include an interface with a host system controller, which may be an example of a controller or control component configured to cause the host systemto perform various operations in accordance with examples as described herein. The host systemmay include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host systemmay include an application configured for communicating with the memory systemor a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system), a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., peripheral component interconnect express (PCIe) controller, serial advanced technology attachment (SATA) controller). The host systemmay use the memory system, for example, to write data to the memory systemand read data from the memory system. Although one memory systemis shown in, the host systemmay be coupled with any quantity of memory systems.

105 110 105 110 110 105 106 105 115 110 105 110 106 115 130 110 130 110 The host systemmay be coupled with the memory systemvia at least one physical host interface. The host systemand the memory systemmay, in some cases, be configured to communicate via a physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory systemand the host system). Examples of a physical host interface may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fiber Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., DIMM socket interface that supports DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controllerof the host systemand a memory system controllerof the memory system. In some examples, the host systemmay be coupled with the memory system(e.g., the host system controllermay be coupled with the memory system controller) via a respective physical host interface for each memory deviceincluded in the memory system, or via a respective physical host interface for each type of memory deviceincluded in the memory system.

110 115 130 130 130 130 110 130 110 130 130 110 a b 1 FIG. The memory systemmay include a memory system controllerand one or more memory devices. A memory devicemay include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although two memory devices-and-are shown in the example of, the memory systemmay include any quantity of memory devices. Further, if the memory systemincludes more than one memory device, different memory deviceswithin the memory systemmay include the same or different types of memory cells.

115 105 110 115 130 130 115 105 130 130 115 105 130 115 105 130 105 115 130 105 The memory system controllermay be coupled with and communicate with the host system(e.g., via the physical host interface) and may be an example of a controller or control component configured to cause the memory systemto perform various operations in accordance with examples as described herein. The memory system controllermay also be coupled with and communicate with memory devicesto perform operations such as reading data, writing data, erasing data, or refreshing data at a memory device—among other such operations—which may generically be referred to as access operations. In some cases, the memory system controllermay receive commands from the host systemand communicate with one or more memory devicesto execute such commands (e.g., at memory arrays within the one or more memory devices). For example, the memory system controllermay receive commands or operations from the host systemand may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices. In some cases, the memory system controllermay exchange data with the host systemand with one or more memory devices(e.g., in response to or otherwise in association with commands from the host system). For example, the memory system controllermay convert responses (e.g., data packets or other signals) associated with the memory devicesinto corresponding signals for the host system.

115 130 115 105 130 The memory system controllermay be configured for other operations associated with the memory devices. For example, the memory system controllermay execute or manage operations such as wear-leveling operations, garbage collection operations, error control operations such as error-detecting operations or error-correcting operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host systemand physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices.

115 115 115 The memory system controllermay include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations ascribed herein to the memory system controller. The memory system controllermay be or include a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

115 120 120 115 115 120 115 115 120 115 120 130 120 105 130 The memory system controllermay also include a local memory. In some cases, the local memorymay include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) executable by the memory system controllerto perform functions ascribed herein to the memory system controller. In some cases, the local memorymay additionally, or alternatively, include static random access memory (SRAM) or other memory that may be used by the memory system controllerfor internal storage or calculations, for example, related to the functions ascribed herein to the memory system controller. Additionally, or alternatively, the local memorymay serve as a cache for the memory system controller. For example, data may be stored in the local memoryif read from or written to a memory device, and the data may be available within the local memoryfor subsequent retrieval for or manipulation (e.g., updating) by the host system(e.g., with reduced latency relative to a memory device) in accordance with a cache policy.

110 115 110 115 110 105 135 130 115 115 105 135 130 115 1 FIG. Although the example of the memory systeminhas been illustrated as including the memory system controller, in some cases, a memory systemmay not include a memory system controller. For example, the memory systemmay additionally, or alternatively, rely on an external controller (e.g., implemented by the host system) or one or more local controllers, which may be internal to memory devices, respectively, to perform the functions ascribed herein to the memory system controller. In general, one or more functions ascribed herein to the memory system controllermay, in some cases, be performed instead by the host system, a local controller, or any combination thereof. In some cases, a memory devicethat is managed at least in part by a memory system controllermay be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

130 130 130 130 A memory devicemay include one or more arrays of non-volatile memory cells. For example, a memory devicemay include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magneto RAM (MRAM), NOR (e.g., NOR flash) memory, Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally, or alternatively, a memory devicemay include one or more arrays of volatile memory cells. For example, a memory devicemay include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

130 135 130 135 115 115 130 135 130 135 1 FIG. a may a b b. In some examples, a memory devicemay include (e.g., on the same die, within the same package) a local controller, which may execute operations on one or more memory cells of the respective memory device. A local controllermay operate in conjunction with a memory system controlleror may perform one or more functions ascribed herein to the memory system controller. For example, as illustrated in, a memory device-include a local controller-and a memory device-may include a local controller-

130 130 160 130 160 160 160 165 165 170 170 175 175 In some cases, a memory devicemay be or include a NAND device (e.g., NAND flash device). A memory devicemay be or include a die(e.g., a memory die). For example, in some cases, a memory devicemay be a package that includes one or more dies. A diemay, in some examples, be a piece of electronics-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each diemay include one or more planes, and each planemay include a respective set of blocks, where each blockmay include a respective set of pages, and each pagemay include a set of memory cells.

130 130 In some cases, a NAND memory devicemay include memory cells configured to each store one bit of information, which may be referred to as single level cells (SLCs). Additionally, or alternatively, a NAND memory devicemay include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLCs) if configured to each store two bits of information, as tri-level cells (TLCs) if configured to each store three bits of information, as quad-level cells (QLCs) if configured to each store four bits of information, or more generically as multiple-level memory cells. Multiple-level memory cells may provide greater density of storage relative to SLC memory cells but may, in some cases, involve narrower read or write margins or greater complexities for supporting circuitry.

165 170 165 170 170 165 170 180 170 170 170 170 170 165 165 165 165 170 170 170 170 180 170 130 130 130 170 165 170 165 170 165 165 175 165 165 a b c d a b c d a b c d a b a a b b In some cases, planesmay refer to groups of blocksand, in some cases, concurrent operations may be performed on different planes. For example, concurrent operations may be performed on memory cells within different blocksso long as the different blocksare in different planes. In some cases, an individual blockmay be referred to as a physical block, and a virtual blockmay refer to a group of blockswithin which concurrent operations may occur. For example, concurrent operations may be performed on blocks-,-,-, and-that are within planes-,-,-, and-, respectively, and blocks-,-,-, and-may be collectively referred to as a virtual block. In some cases, a virtual block may include blocksfrom different memory devices(e.g., including blocks in one or more planes of memory device-and memory device-). In some cases, the blockswithin a virtual block may have the same block address within their respective planes(e.g., block-may be “block 0” of plane-, block-may be “block 0” of plane-, and so on). In some cases, performing concurrent operations in different planesmay be subject to one or more restrictions, such as concurrent operations being performed on memory cells within different pagesthat have the same page address within their respective planes(e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes).

170 175 175 In some cases, a blockmay include memory cells organized into rows (pages) and columns (e.g., strings, not shown). For example, memory cells in the same pagemay share (e.g., be coupled with) a common word line, and memory cells in the same string may share (e.g., be coupled with) a common digit line (which may alternatively be referred to as a bit line).

175 170 175 170 175 For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first level of granularity (e.g., at a page level of granularity, or portion thereof) but may be erased at a second level of granularity (e.g., at a block level of granularity). That is, a pagemay be the smallest unit of memory (e.g., set of memory cells) that may be independently programmed or read (e.g., programed or read concurrently as part of a single program or read operation), and a blockmay be the smallest unit of memory (e.g., set of memory cells) that may be independently erased (e.g., erased concurrently as part of a single erase operation). Further, in some cases, NAND memory cells may be erased before they can be re-written with new data. Thus, for example, a used pagemay, in some cases, not be updated until the entire blockthat includes the pagehas been erased.

110 115 135 In some cases, a memory systemmay utilize a memory system controllerto provide a managed memory system that may include, for example, one or more memory arrays and related circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller). An example of a managed memory system is a managed NAND (MNAND) system.

105 110 105 110 105 110 105 110 110 105 110 110 105 A host systemand a memory systemmay support different data rates for transferring data between the host systemand the memory system. In such examples, the host systemand the memory systemmay negotiate a data rate (e.g., a highest data rate) supported by both systems. For example, the host systemand the memory systemmay negotiate the data rate in response to the memory systemtransitioning from a first power state to a second power state (e.g., when powering on, after boot-up sequence, after exiting a sleep mode). In some examples, the negotiation between the host systemand the memory systemmay incur latency based on increasing the data rate through a defined sequence. For example, a memory systemthat supports a relatively high data rate may negotiate to an initial data rate and then a next data rate before negotiating to the relatively high data rate (e.g., the highest supported data rate). Some applications (e.g., time-sensitive applications) may benefit from the host systemaccessing data from the memory system to initialize the applications without the latency incurred from negotiating to the highest data rate.

105 110 105 110 110 105 105 110 105 110 110 As described herein, a host systemmay assert a signal (e.g., a fast boot signal) to instruct a memory systemto communicate data at a first data rate (e.g., a relatively lower data rate) before negotiating to a higher data rate. For example, the host systemmay assert the fast boot signal to a pin of the memory system, which may instruct the memory systemto communicate the data at a lowest supported data rate. In some examples, the host systemmay output the fast boot signal based on an estimated size of the data to be transferred, a dynamic measurement of the data, an application associated with the data, or any combination thereof. Based on transferring the data, the host systemand the memory systemmay negotiate to an increased data rate (e.g., up to the highest supported data rate). By transferring the data to the host systemat the first data rate before increasing to a second data rate, the memory systemmay enable some applications (e.g., a back-up camera feed) to initialize relatively quickly, which may reduce latency and improve the overall performance of the memory system.

2 FIG. 1 FIG. 1 FIG. 200 200 100 200 210 205 205 205 200 100 210 205 110 105 shows an example of a systemthat supports a memory system boot sequence with reduced latency in accordance with examples as disclosed herein. The systemmay be an example of a systemas described with reference to, or aspects thereof. The systemmay include a memory systemconfigured to store data received from the host systemand to send data to the host system, if requested by the host systemusing access commands (e.g., read commands or write commands). The systemmay implement aspects of the systemas described with reference to. For example, the memory systemand the host systemmay be examples of the memory systemand the host system, respectively.

210 240 210 205 205 240 240 1 FIG. The memory systemmay include one or more memory devicesto store data transferred between the memory systemand the host system(e.g., in response to receiving access commands from the host system). The memory devicesmay include one or more memory devices as described with reference to. For example, the memory devicesmay include NAND memory, PCM, self-selecting memory, 3D cross point or other chalcogenide-based memories, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM, among other examples.

210 230 240 230 240 240 230 240 210 230 230 240 230 135 1 FIG. The memory systemmay include a storage controllerfor controlling the passing of data directly to and from the memory devices(e.g., for storing data, for retrieving data, for determining memory locations in which to store data and from which to retrieve data). The storage controllermay communicate with memory devicesdirectly or via a bus (not shown), which may include using a protocol specific to each type of memory device. In some cases, a single storage controllermay be used to control multiple memory devicesof the same or different types. In some cases, the memory systemmay include multiple storage controllers(e.g., a different storage controllerfor each type of memory device). In some cases, a storage controllermay implement aspects of a local controlleras described with reference to.

210 220 205 225 205 240 220 225 230 205 240 250 The memory systemmay include an interface(e.g., a peripheral component interface (PCI) or a peripheral component express interface (PCIe)) for communication with the host system, and a bufferfor temporary storage of data being transferred between the host systemand the memory devices. The interface, buffer, and storage controllermay support transferring data between the host systemand the memory devices(e.g., as shown by a data path), and may be collectively referred to as data path components.

225 225 225 225 225 Using the bufferto temporarily store data during transfers may allow data to be buffered while commands are being processed, which may reduce latency between commands and may support arbitrary data sizes associated with commands. This may also allow bursts of commands to be handled, and the buffered data may be stored, or transmitted, or both (e.g., after a burst has stopped). The buffermay include relatively fast memory (e.g., some types of volatile memory, such as SRAM or DRAM), or hardware accelerators, or both to allow fast storage and retrieval of data to and from the buffer. The buffermay include data path switching components for bi-directional data transfer between the bufferand other components.

260 265 270 205 240 210 210 235 250 235 245 235 205 245 215 205 240 235 210 In some cases, one or more queues (e.g., a command queue, a buffer queue, a storage queue) may be used to control the processing of access commands and the movement of corresponding data. Data transferred between the host systemand the memory devicesmay be conveyed along a different path in the memory systemthan non-data information (e.g., commands, status information). For example, the system components in the memory systemmay communicate with each other using a bus, while the data may use the data paththrough the data path components instead of the bus. In some examples, a pinmay be separate from a busthat delivers data. For example, the signal output by the host systemto the pinmay be conveyed along the non-data path. The memory system controllermay control how and if data is transferred between the host systemand the memory devicesby communicating with the data path components over the bus(e.g., using a protocol specific to the memory system).

215 240 205 205 240 215 225 205 205 215 225 After a determination that an access command has been received, the memory system controllermay execute the access command. For a read command, this may include obtaining data from one or more memory devicesand transmitting the data to the host system. For a write command, this may include receiving data from the host systemand moving the data to one or more memory devices. In either case, the memory system controllermay use the bufferfor, among other things, temporary storage of the data being received from or sent to the host system. To process a write command received from the host system, the memory system controllermay determine if the bufferhas sufficient available space to store the data associated with the command.

265 225 265 225 260 265 215 265 225 265 205 In some cases, a buffer queuemay be used to control a flow of commands associated with data stored in the buffer, including write commands. The buffer queuemay include the access commands associated with data currently stored in the buffer. In some cases, the commands in the command queuemay be moved to the buffer queueby the memory system controllerand may remain in the buffer queuewhile the associated data is stored in the buffer. Using the buffer queue, multiple access commands may be received sequentially from the host systemand at least portions of the access commands may be processed concurrently.

225 215 220 205 220 205 220 225 250 220 225 265 225 220 215 235 225 If the bufferhas sufficient space to store the write data, the memory system controllermay cause the interfaceto transmit an indication of availability to the host system(e.g., a “ready to transfer” indication), which may be performed in accordance with a protocol (e.g., a UFS protocol, an eMMC protocol). As the interfacereceives the data associated with the write command from the host system, the interfacemay transfer the data to the bufferfor temporary storage using the data path. In some cases, the interfacemay obtain (e.g., from the buffer, from the buffer queue) the location within the bufferto store the data. The interfacemay indicate to the memory system controller(e.g., via the bus) if the data transfer to the bufferhas been completed.

225 220 225 240 230 230 215 235 240 270 215 235 265 270 270 230 225 265 270 225 230 240 After the write data has been stored in the bufferby the interface, the data may be transferred out of the bufferand stored in a memory device, which may involve operations of the storage controller. The storage controllermay indicate to the memory system controller(e.g., via the bus) that the data transfer to one or more memory deviceshas been completed. In some cases, a storage queuemay support a transfer of write data. For example, the memory system controllermay push (e.g., via the bus) write commands from the buffer queueto the storage queuefor processing. The storage queuemay include entries for each access command. In some cases, the storage controllermay obtain (e.g., from the buffer, from the buffer queue, from the storage queue) the location within the bufferfrom which to obtain the data. The storage controllermay manage the locations within the memory devicesto store the data (e.g., performing wear-leveling, performing garbage collection).

205 215 225 215 225 265 230 215 235 225 To process a read command received from the host system, the memory system controllermay determine if the bufferhas sufficient available space to store the data associated with the command. For example, the memory system controllermay determine (e.g., via firmware, via controller firmware), an amount of space within the bufferthat may be available to store data associated with the read command. In some cases, the buffer queuemay support buffer storage of data associated with read commands in a similar manner as discussed with respect to write commands. The storage controllermay indicate to the memory system controller(e.g., via the bus) when the data transfer to the bufferhas been completed.

270 215 270 230 225 270 240 In some cases, the storage queuemay be used to aid with the transfer of read data. For example, the memory system controllermay push the read command to the storage queuefor processing. In some cases, the storage controllermay obtain (e.g., from the buffer, from the storage queue) the location within one or more memory devicesfrom which to retrieve the data.

225 230 225 205 215 220 225 250 205 220 260 215 235 205 After the data has been stored in the bufferby the storage controller, the data may be transferred from the bufferand sent to the host system. For example, the memory system controllermay cause the interfaceto retrieve the data from the bufferusing the data pathand transmit the data to the host system(e.g., according to a protocol, such as a UFS protocol or an eMMC protocol). For example, the interfacemay process the command from the command queueand may indicate to the memory system controller(e.g., via the bus) that the data transmission to the host systemhas been completed.

215 260 215 225 225 265 265 215 225 265 The memory system controllermay execute received commands according to an order (e.g., a first-in-first-out order, according to the order of the command queue). For each command, the memory system controllermay cause data corresponding to the command to be moved into and out of the buffer, as discussed herein. As the data is moved into and stored within the buffer, the command may remain in the buffer queue. A command may be removed from the buffer queue(e.g., by the memory system controller) if the processing of the command has been completed (e.g., if data corresponding to the access command has been transferred out of the buffer). If a command is removed from the buffer queue, the address previously storing the data associated with that command may be available to store data associated with a new command.

215 240 215 205 240 230 215 215 230 230 In some examples, the memory system controllermay be configured for operations associated with one or more memory devices. For example, the memory system controllermay execute or manage operations such as wear-leveling operations, garbage collection operations, error control operations such as error-detecting operations or error-correcting operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., LBAs) associated with commands from the host systemand physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices. In some cases, the storage controllermay be configured to perform one or more of the described operations in conjunction with or instead of the memory system controller. In some cases, the memory system controllermay perform the functions of the storage controllerand the storage controllermay be omitted.

205 210 210 205 210 205 210 220 210 205 205 210 210 240 205 In some examples, the host systemand the memory systemmay support different data rates for transferring data. For example, a memory systemmay support one data rate and the host systemmay support another data rate higher than the data rate supported by the memory system. Based on the different data rates, the host systemand the memory systemmay negotiate their link (e.g., the connection through the interface) to a data rate supported by both systems. That is, as used herein “negotiating” or “negotiating a data rate” may refer to any process or operation where the memory systemand the host systemexchange, or otherwise indicate, capability information (e.g., a supported data rate), determine a data rate supported by each system based on the capability information, and communicate data according to the data rate. In some examples, the host systemand the memory systemnegotiate the data rate to the highest rate that each system supports. For example, a memory systemthat supports a data rate of 6 Gb/s (e.g., based on a supported data rate of one or more memory devices) may start communicating data with the host systemat a data rate of 1.5 Gb/s before negotiating up (e.g., increasing the data rate) to 6 Gb/s.

205 210 210 205 210 210 The negotiation to higher data rates may be based on a sequence known (e.g., predefined or standardized) to the host systemand the memory system. For example, a memory systemthat supports multiple data rates (e.g., Gen1, Gen2, Gen4, etc.) may begin communications at an initial data rate (e.g., Gen1), may increase the communication speed to a next data rate (e.g., Gen2), and may finally increase to a highest data rate (e.g., Gen4). In some examples, the host systemand the memory systemmay negotiate the data rate based on the memory systemtransitioning from a lower power state to a higher power state (e.g., power-on or exiting a sleep mode).

210 205 210 210 205 210 205 210 In some examples, the negotiations to higher data rates may increase latency and a time-to-ready (TTR) of the memory system. For example, the host systemmay negotiate with the memory systemto the highest supported data rate by default, as communicating data with the memory systemat a highest data rate may be desirable. However, negotiating between the host systemand the memory systemup to the highest supported data rate may degrade performance because the host systemmay wait longer to perform access operations with the memory systemwhile the data rate is negotiated.

205 210 205 210 205 210 210 In some examples, the host systemmay benefit from refraining to negotiate to a higher data rate after the memory systemtransitions to a higher power state. For example, the host systemmay provide data (e.g., high priority data) from the memory systemto one or more time-sensitive applications before the host systemand memory systemincrease the communication speed to a highest data rate. Accordingly, valuable time may be saved such that the memory systemmay be able to perform time-sensitive functions before incurring the additional latency associated with negotiating to a highest data rate.

210 205 210 In some examples, the one or more time-sensitive applications may be initialized when the memory systemtransitions power states. In some instances, the time-sensitive applications may be associated with relatively high priority data. Such time-sensitive applications may be or may include automotive applications such as a back-up camera feed, infotainment systems, parking sensors, and the like. The techniques described herein may support functions associated with such time-sensitive applications being performed before the host systemand memory systemincrease the communication speed to a highest data rate, which may allow for the time-sensitive application functions to be performed relatively quickly.

205 245 220 210 205 205 210 210 210 210 205 205 210 3 FIG. The host systemmay output a signal (e.g., a hardware signal) to the pinat the interfaceto instruct the memory systemto negotiate a data rate lower than a highest supported data rate (e.g., the lowest supported data rate between both systems). The host systemmay either set the pin to a first value to negotiate the link at the lower data rate to transfer the high priority data (e.g., perform fast boot), or the host systemmay set the pin to a second value to negotiate the link to the higher data rate (e.g., perform a normal boot). As described further with reference to, the memory systemmay receive the signal based on one or more applications, a size of the high priority data, or any combination thereof. In some examples, the memory systemmay receive the signal after transitioning from a relatively low power state (e.g., the memory systemis off or in a sleep mode) to a higher power state. The memory systemand the host systemmay negotiate to a higher data rate after the host systemreceives the high priority data. For example, based on transmitting the high priority data (e.g., and initializing one or more applications), the memory systemmay perform one or more access operations according to a highest data rate supported by both systems.

3 FIG. 1 2 FIGS.and 300 300 shows an example of a process flow diagramthat supports a memory system boot sequence with reduced latency in accordance with examples as disclosed herein. The process flow diagrammay be implemented by aspects of a memory system and a host system as described with reference to.

An example of a system that may use the fast boot-up techniques described herein may be an automotive application. Many vehicles are equipped with memory systems that support other components of the vehicle (e.g., back-up cameras, infotainment centers, and/or advanced driver assistance systems (ADAS)). After starting a vehicle, some users of the vehicle desire some functionality to be initialized soon after starting the car. For example, some drivers of a vehicle may start a vehicle and soon thereafter being backing up the vehicle (e.g., down a driveway or out of a parking stall). The boot-up sequency of the memory system in the vehicle may contribute to the delay in initializing the back-up camera of the vehicle. To reduce the delay in initializing some systems (e.g., the back-up camera in a vehicle), the memory system may include these techniques to perform a fast boot-up sequence. In this sequence, the memory system may initially begin communicating data at a slower speed to transfer data so that some applications (e.g., the back-up camera of the vehicle) may begin operating with a shorter delay. Then sometime later, the memory system may negotiate a faster speed to transfer data after the low-latency applications have been initialized.

305 310 205 210 2 FIG. At, a memory system may enter a low power state (e.g., power off or enter a sleep mode). In some examples, at, a host system (e.g., the host system) may determine whether to output a signal (e.g., a fast boot signal). The fast boot signal may instruct the memory system to communicate a quantity of data according to a first rate. For example, the fast boot signal may instruct the memory system to communicate the data according to a data rate lower (e.g., a lowest supported data rate) than a highest data rate supported by both the memory system and the host system, as described further with reference to. In some examples, the data may be associated with a first priority level (e.g., the data is relatively high priority data). For example, the memory system (e.g., the memory system) may transfer data associated with the first priority level to initialize one or more applications, such as a backup camera, various sensors (e.g., monitoring sensors), infotainment system, or the like.

In some examples, the host system may determine to output the fast boot signal to the memory system. For example, the host system may default to assert the fast boot signal or not (e.g., to boot normally). Additionally, or alternatively, the host system may output the signal based on one or more conditions. For example, one or more applications (e.g., time-sensitive applications such as a back-up camera feed, parking sensors, or the like) may initialize sooner based on the memory system communicating the high priority data according to the lower data rate with the host system. The memory system may receive the signal based on the one or more applications (e.g., the host system may determine the one or more applications may benefit from the fast boot signal and output the signal to the memory system).

215 In some examples, the memory system may receive the signal based on an estimated quantity of the data, a quantity of the data, or any combination thereof. For example, the host system, the memory system (e.g., the memory system controller), or both, may determine that the quantity of the data satisfies a first threshold value. Additionally, or alternatively, the host system, the memory system, or both, may determine an estimated quantity of data satisfies a second threshold value (e.g., equal to or different than the first threshold value).

In some examples, the threshold values (e.g., the first threshold, the second threshold, or both) may correspond to a duration for the memory system to communicate a quantity of data less than or equal to a duration for the host system and the memory system to negotiate the highest data rate (e.g., the memory system may receive the signal if communicating the high priority data is relatively faster than negotiating up to the highest data rate). In other examples, the threshold values may correspond to a quantity of data associated with initializing an application. For example, an application may initialize based on a variable quantity of data, and the host system, the memory system, or both, may estimate the quantity of data to initialize the application. The memory system may receive the fast boot signal based on the quantity of data satisfying the first threshold or the estimated quantity of data satisfying the second threshold.

315 245 320 325 2 FIG. Atthe host system may assert the fast boot signal to a pin (e.g., the pinas described with reference to). At, the memory system may negotiate a data rate lower (e.g., a lowest supported data rate) than a highest data rate supported by both the memory system and the host system based on receiving the signal from the pin. For example, the memory system may sample the fast boot signal and negotiate the slowest link speed for relatively quick access (e.g., compared to performing the negotiation to the highest data rate) with the host system on power up. At, the host system may perform one or more access operations to communicate the quantity of data according to the lower data rate. For example, the host system may read or write to the memory system at the slowest supported data rate.

330 335 At, the host system and the memory system may increase the data rate to a data rate higher than the lower data rate based on communicating the quantity of data. At, the memory system may perform access operations (e.g., read or write) at increased data rate (e.g., the highest data rate). In some examples, data communicated according to the increased data rate may be associated with the second priority level lower than the first priority level of the quantity of data communicated according to the lower data rate.

340 335 In some examples, at, the host system may determine to not output the fast boot signal (e.g., based on one or more applications that are not time-sensitive). In such examples, the host system and the memory system may negotiate to the data rate higher than the lower data rate (e.g., the highest supported data rate) without the memory system first booting to the lower data rate. The memory system and the host system may continue to, in which the memory system may perform access operations (e.g., read or write) at the higher data rate. By transferring the data to the host system at the lower data rate before increasing to the higher data rate, the memory system may enable some applications (e.g., a back-up camera feed) to initialize relatively quickly, which may reduce latency and improve the overall performance of the memory system.

4 FIG. 1 3 FIGS.through 400 420 420 420 420 425 430 435 440 445 450 455 460 shows a block diagramof a memory systemthat supports a memory system boot sequence with reduced latency in accordance with examples as disclosed herein. The memory systemmay be an example of aspects of a memory system as described with reference to. The memory system, or various components thereof, may be an example of means for performing various aspects of memory system boot sequence with reduced latency as described herein. For example, the memory systemmay include a boot-up component, a boot-up type indication component, a data communication component, a data rate component, a data quantity component, a pin component, an interface component, an access command component, or any combination thereof. Each of these components, or components of subcomponents thereof (e.g., one or more processors, one or more memories), may communicate, directly or indirectly, with one another (e.g., via one or more buses).

425 430 435 440 The boot-up componentmay be configured as or otherwise support a means for initiating a boot-up sequence to transition the memory system from a first power state to a second power state. The boot-up type indication componentmay be configured as or otherwise support a means for receiving, from a host system based on initiating the boot-up sequence, first signaling to indicate that the boot-up sequence is a first type of sequence associated with lower latency. The data communication componentmay be configured as or otherwise support a means for communicating first data with the host system according to a first data rate based on receiving the first signaling. The data rate componentmay be configured as or otherwise support a means for increasing a rate for communicating with the host system from the first data rate to a second data rate after communicating the first data, where the first data rate is slower than the second data rate for communicating with the host system.

435 In some examples, the data communication componentmay be configured as or otherwise support a means for communicating second data with the host system according to the second data rate based on increasing the rate for communicating with the host system from the first data rate to the second data rate. In some examples, the first data is associated with a first priority level and the second data is associated with a second priority level different from the first priority level.

440 435 In some examples, the data rate componentmay be configured as or otherwise support a means for increasing the rate for communicating with the host system from the second data rate to a third data rate. In some examples, the data communication componentmay be configured as or otherwise support a means for communicating third data with the host system according to the third data rate based on increasing the rate for communicating with the host system from the second data rate to the third data rate, where the third data rate is faster than the first data rate and the second data rate for communicating with the host system.

445 In some examples, the data quantity componentmay be configured as or otherwise support a means for determining that a quantity of the first data satisfies a threshold value based on initiating the boot-up sequence, where receiving the first signaling is based on determining that the quantity of the first data satisfies the threshold value. In some examples, the memory system is configured to boot-up using a second type of sequence associated with a higher latency than the first type of sequence. In some examples, the first signaling is received via a first pin of the memory system. In some examples, the first data is communicated with the host system via an interface different from the first pin.

460 In some examples, to support communicating the first data with the host system, the access command componentmay be configured as or otherwise support a means for receiving one or more read commands, transmitting one or more write commands, or both.

In some examples, the first data rate is associated with a slowest data rate for communicating with the host system. In some examples, communicating the first data according to the first data rate is based on an application associated with the first data. In some examples, the first power state is associated with a lower power state than the second power state.

420 420 In some examples, the described functionality of the memory system, or various components thereof, may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the memory system, or various components thereof, may be implemented at least in part by instructions (e.g., stored in memory, non-transitory computer-readable medium) executable by such at least one processor.

5 FIG. 1 4 FIGS.through 500 500 500 shows a flowchart illustrating a methodthat supports a memory system boot sequence with reduced latency in accordance with examples as disclosed herein. The operations of methodmay be implemented by a memory system or its components as described herein. For example, the operations of methodmay be performed by a memory system as described with reference to. In some examples, a memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the memory system may perform aspects of the described functions using special-purpose hardware.

505 505 425 315 340 4 FIG. 3 FIG. At, the method may include initiating a boot-up sequence to transition the memory system from a first power state to a second power state. In some examples, aspects of the operations ofmay be performed by a boot-up componentas described with reference to, as well as the operations described atandin.

510 510 430 315 245 4 FIG. 3 FIG. 2 FIG. At, the method may include receiving, from a host system based on initiating the boot-up sequence, first signaling to indicate that the boot-up sequence is a first type of sequence associated with lower latency. In some examples, aspects of the operations ofmay be performed by a boot-up type indication componentas described with reference toand described with reference to the operation described atinand the pinin.

515 515 435 325 4 FIG. 3 FIG. At, the method may include communicating first data with the host system according to a first data rate based on receiving the first signaling. In some examples, aspects of the operations ofmay be performed by a data communication componentas described with reference to, as well as the operation described atin.

520 520 440 330 4 FIG. 3 FIG. At, the method may include increasing a rate for communicating with the host system from the first data rate to a second data rate after communicating the first data, where the first data rate is slower than the second data rate for communicating with the host system. In some examples, aspects of the operations ofmay be performed by a data rate componentas described with reference to, as well as the operation described atin.

500 In some examples, an apparatus as described herein may perform a method or methods, such as the method. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor), or any combination thereof for performing the following aspects of the present disclosure:

Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for initiating a boot-up sequence to transition the memory system from a first power state to a second power state; receiving, from a host system based on initiating the boot-up sequence, first signaling to indicate that the boot-up sequence is a first type of sequence associated with lower latency; communicating first data with the host system according to a first data rate based on receiving the first signaling; and increasing a rate for communicating with the host system from the first data rate to a second data rate after communicating the first data, where the first data rate is slower than the second data rate for communicating with the host system.

Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for communicating second data with the host system according to the second data rate based on increasing the rate for communicating with the host system from the first data rate to the second data rate.

Aspect 3: The method, apparatus, or non-transitory computer-readable medium of aspect 2, where the first data is associated with a first priority level and the second data is associated with a second priority level different from the first priority level.

Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 3, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for increasing the rate for communicating with the host system from the second data rate to a third data rate and communicating third data with the host system according to the third data rate based on increasing the rate for communicating with the host system from the second data rate to the third data rate, where the third data rate is faster than the first data rate and the second data rate for communicating with the host system.

Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining that a quantity of the first data satisfies a threshold value based on initiating the boot-up sequence, where receiving the first signaling is based on determining that the quantity of the first data satisfies the threshold value.

Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 5, where the memory system is configured to boot-up using a second type of sequence associated with a higher latency than the first type of sequence.

Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 6, where the first signaling is received via a first pin of the memory system and the first data is communicated with the host system via an interface different from the first pin.

Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 7, where communicating the first data with the host system includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving one or more read commands, transmitting one or more write commands, or both.

Aspect 9: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 8, where the first data rate is associated with a slowest data rate for communicating with the host system.

Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 9, where communicating the first data according to the first data rate is based on an application associated with the first data.

Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 10, where the first power state is associated with a lower power state than the second power state.

It should be noted that the described techniques include possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or symbols of signaling that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.

The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.

The term “coupling” (e.g., “electrically coupling”) may refer to a condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components over a conductive path to a closed-circuit relationship between components in which signals are capable of being communicated between components over the conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow.

The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other if the switch is open. If a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.

The terms “if,” “when,” “based on,” or “based at least in part on” may be used interchangeably. In some examples, if the terms “if,” “when,” “based on,” or “based at least in part on” are used to describe a conditional action, a conditional process, or connection between portions of a process, the terms may be interchangeable.

The term “in response to” may refer to one condition or action occurring at least partially, if not fully, as a result of a previous condition or action. For example, a first condition or action may be performed, and a second condition or action may at least partially occur as a result of the previous condition or action occurring (whether directly after or after one or more other intermediate conditions or actions occurring after the first condition or action).

Additionally, the terms “directly in response to” or “in direct response to” may refer to one condition or action occurring as a direct result of a previous condition or action. In some examples, a first condition or action may be performed, and a second condition or action may occur directly as a result of the previous condition or action occurring independent of whether other conditions or actions occur. In some examples, a first condition or action may be performed, and a second condition or action may occur directly as a result of the previous condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action or a limited quantity of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Any condition or action described herein as being performed “based on,” “based at least in part on,” or “in response to” some other step, action, event, or condition may additionally, or alternatively, (e.g., in an alternative example), be performed “in direct response to” or “directly in response to” such other condition or action unless otherwise specified.

The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A switching component or a transistor discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” if a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” if a voltage less than the transistor's threshold voltage is applied to the transistor gate.

The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to provide an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a hyphen and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted over as one or more instructions (e.g., code) on a computer-readable medium. Due to the nature of software, functions described herein can be implemented using software executed by a processing system, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

Illustrative blocks and modules described herein may be implemented or performed with one or more processors, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic device, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other types of processors. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

As used herein, including in the claims, the article “a” before a noun is open-ended and understood to refer to “at least one” of those nouns or “one or more” of those nouns. Thus, the terms “a,” “at least one,” “one or more,” “at least one of one or more” may be interchangeable. For example, if a claim recites “a component” that performs one or more functions, each of the individual functions may be performed by a single component or by any combination of multiple components. Thus, the term “a component” having characteristics or performing functions may refer to “at least one of one or more components” having a particular characteristic or performing a particular function. Subsequent reference to a component introduced with the article “a” using the terms “the” or “said” may refer to any or all of the one or more components. For example, a component introduced with the article “a” may be understood to mean “one or more components,” and referring to “the component” subsequently in the claims may be understood to be equivalent to referring to “at least one of the one or more components.” Similarly, subsequent reference to a component introduced as “one or more components” using the terms “the” or “said” may refer to any or all of the one or more components. For example, referring to “the one or more components” subsequently in the claims may be understood to be equivalent to referring to “at least one of the one or more components.”

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium, or combination of multiple media, which can be accessed by a computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium or combination of media that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer, or one or more processors.

The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.