Display device and driving method thereof

This application claims priority to Chinese Patent Application No. 202411951418.0, filed on Dec. 26, 2024. The disclosure of the aforementioned application is incorporated herein by reference in its entirety.

The present disclosure relates to the field of display technologies, and in particular, to a display device and a driving method thereof.

As an advanced display driving technology, the tri-gate driving technology can be used to reduce a number of display driving circuit boards, thereby reducing the costs of chips.

However, in the tri-gate driving technology, since each pixel unit needs to be controlled by three gate signals to turn on in sequence, the scanning time of each row of subpixels is short, which causes a problem that a large current in a clock signal line connected to a gate driving circuit cannot be released quickly during an electrostatic test. It is easy to accidentally trigger the overcurrent protection of the display device, causing a black screen and making it impossible to complete the electrostatic test.

Embodiments of the present disclosure provide a display device with a first working mode, including a display panel including a signal line; and a driving circuit board electrically connected to the display panel. In the first working mode, the driving circuit board is configured to perform an overcurrent protection on the display panel when a current in the signal line is greater than a preset current during at least two consecutive frames.

Embodiments of the present disclosure also provide a driving method of a display device, including: acquiring, by a driving circuit board, a current in a signal line of a display panel; in a first working mode, determining, by the driving circuit board, whether the current in the signal line is greater than a preset current during at least two consecutive frames; and if yes, performing, by the driving circuit board, an overcurrent protection on the display panel.

Technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present disclosure.

In the description of the present disclosure, the terms “first”, “second”, etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating a number of indicated technical features. Thus, features defined as “first” and “second” may explicitly or implicitly include one or more of the described features. In addition, it should be noted that the accompanying drawings only provide structures that are closely related to the present disclosure and omit some details that are not closely related to the present disclosure. The purpose is to simplify the drawings and make the present disclosure points clear at a glance, rather than to illustrate that an actual device is exactly the same as the drawings, and is not intended to be a limitation of the actual device.

Reference herein to “embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the present disclosure. The appearances of this phrase at various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.

The present disclosure provides a display device, which includes, but is not limited to, the following embodiments and combinations of the following embodiments.

1 FIG. 100 10 20 30 10 30 10 20 In some embodiments, as illustrated in, a display devicehas a first working mode and includes: a display panelincluding a signal line; and a driving circuit boardelectrically connected to the display panel. In the first working mode, the driving circuit boardis configured to perform overcurrent protection on the display panelwhen a current in the signal lineis greater than a preset current during at least two consecutive frames.

100 10 10 1 1 40 301 50 50 10 1 FIG. 1 FIG. The display deviceis, but is not limited to, an organic self-luminous display device, an inorganic self-luminous direct display device, or a liquid crystal display device. As illustrated in, that a plurality of subpixels P in a display area A of the display panelare arranged in an array of n rows and m columns is taken as an example here, where n and m are both positive integers. Correspondingly, the display panelcan also include a plurality of data lines (DLto DLm), a plurality of gate lines (GLto GLn), a plurality of pixel circuitscorresponding to the plurality of subpixels P, a source driverelectrically connected to the plurality of data lines, and a gate driverelectrically connected to the plurality of gate lines. The gate drivermay be a gate driving circuit located on a substrate of the display panelor a chip provided independently of the substrate (only illustrates the former case condition as an example).

40 1 40 40 40 1 40 40 40 gate gate data Specifically, each subpixel P is electrically connected to a corresponding one of the pixel circuits, and each gate line (each of GLto GLn) is electrically connected to the plurality of pixel circuitscorresponding to the plurality of subpixels P located in a corresponding row to output a corresponding gate signal Sthereto. In each frame, the gate signal Sincludes a gate pulse configured to control the corresponding plurality of pixel circuitsto turn on, and the plurality of rows of pixel circuitsare turned on sequentially under the control of a plurality of gate pulses of the plurality of gate signals. Each data line (each of DLto DLm) is connected to the plurality of pixel circuitscorresponding to the plurality of subpixels P located in a corresponding column to output corresponding data signals Sthereto. A plurality of data signals corresponding to the plurality of columns of subpixels P are configured as follows: when the pixel circuitsin each row are turned on, the plurality of data signals data transmit a plurality of effective data voltages corresponding to the subpixels P in the same row. In this way, when the pixel circuitsin each row are turned on, the plurality of subpixels P in the same row are driven to emit light by the plurality of effective data voltages corresponding thereto respectively. By analogy, the plurality of rows of subpixels P finally emits light to display an image of this frame.

301 30 302 301 50 303 301 50 302 40 40 303 201 303 30 10 302 301 50 301 50 data gate Furthermore, in addition to the above-mentioned source driver, the driving circuit boardof this embodiment may also include a timing controllerelectrically connected to the source driverand the gate driver, and a power managerelectrically connected to the source driver, the gate driver, the timing controller, and the plurality of pixel circuits. The plurality of pixel circuitsare electrically connected to the power managerthrough a plurality of power signal lines. The power managercan supply power to the driving circuit boardand the display panel. The timing controllercan generate a grayscale signal and a corresponding first control signal that act on the source driver, and can also generate a corresponding second control signal that acts on the gate driver. Then, the source drivergenerates the plurality of data signals Sin response to the grayscale signal Sg and the first control signal, and the gate drivergenerates the plurality of gate signals Sin response to the second control signal.

20 10 1 1 201 In conjunction with the above discussion, the signal lineof the display panelmay include at least one of the plurality of gate lines (GLto GLn), the plurality of data lines (DLto DLm), and the plurality of power signal lines.

100 20 10 10 20 10 100 20 10 10 It should be noted that in order to avoid the damage to the display devicedue to an excessive current caused by a short circuit or other faults of the signal lineof the display panel, it is generally possible to control whether to enable the overcurrent protection of the display panelby detecting whether the current in the signal lineis greater than a preset current during one frame, so as to cut off or limit the current supplied for the display panel. However, when an electrostatic discharge capability of the display deviceis tested, due to charge accumulation, the current in the signal lineof the display panelis also relatively large, causing the existing overcurrent protection to be accidentally triggered, resulting in a black screen of the display panel, and thus the test of the electrostatic discharge capability could not be completed

20 30 10 20 20 20 It can be understood that the charge accumulated due to the test of electrostatic discharge capability can be released in a starting period of each frame to reduce the current (unlike the charge accumulation caused by a short circuit or other faults of the signal linewhich does not have a release path and results in a continuous excessive current), that is, a risk of excessive current caused by the test of electrostatic discharge capability is generally concentrated between a starting time of a current frame and a starting time of a next frame. In this embodiment, the driving circuit boardis configured to enable the overcurrent protection of the display panelin the first working mode on a condition that the current in the signal lineis greater than the preset current during at least two consecutive frames, that is, the overcurrent protection is enabled when it is detected that the current in the signal lineis greater than the preset current during at least two consecutive frames. Thus, the overcurrent protection is not enabled when a large current in the signal lineis detected within only one frame, preventing accidental triggering of the overcurrent protection during the test of electrostatic discharge capability, which would otherwise interrupt the test of electrostatic discharge capability, and improving the reliability of the test of electrostatic discharge capability.

1 FIG. 2 FIG. 100 30 10 20 30 304 30 10 304 20 304 30 10 20 304 30 10 20 In some embodiments, as illustrated in,, and Table 1, the display devicefurther has a second working mode. In the second working mode, the driving circuit boardis configured to enable the overcurrent protection of the display panelon a condition that the current in the signal lineis greater than the preset current during one frame. Specifically, the driving circuit boardincludes a register, and the driving circuit boardis configured to perform the overcurrent protection on the display panelaccording to the information stored in the registerand the current in the signal line. In the second working mode, the information stored in the registerincludes first information, and the driving circuit boardis configured to perform the overcurrent protection on the display panelwhen the current in the signal lineis greater than the preset current during one frame; in the first working mode, the information stored in the registerincludes second information, and the driving circuit boardis configured to perform the overcurrent protection on the display panelwhen the current in the signal lineis greater than the preset current during at least two consecutive frames.

304 304 30 10 20 304 30 10 20 Based on the above discussion, it can be seen that the information stored in the registerincludes the first information (for example, “000” in Table 1) or the second information (for example, one of these seven types of information “001” . . . “111” in Table 1). When the information stored in the registerincludes the first information, the driving circuit boardis configured to enable the overcurrent protection of the display panelwhen the current in the signal lineis greater than the preset current during one frame; and when the information stored in the registerincludes the second information, the driving circuit boardis configured to enable the overcurrent protection of the display panelwhen the current in the signal lineis greater than the preset current during at least two consecutive frames.

100 20 20 Based on the above discussion, it can be seen that when the display deviceis not in the process of testing the electrostatic discharge capability, if the current in the signal lineis too large due to a short circuit or other fault, it is generally necessary to control whether to enable the overcurrent protection by detecting whether the current in the signal lineis greater than the preset current during one frame.

304 30 30 304 20 100 20 10 20 It can be understood that this embodiment sets the information stored in the registerof the driving circuit boardto include the first information or the second information, so that the driving circuit boarddetermines “a number of detected frames” that is required for the overcurrent protection based on the information stored in the register. The overcurrent protection is enabled when it is detected that the current in the signal lineis greater than the preset current in the corresponding “detected frames”. In this way, different overcurrent protection mechanisms can be set in different scenarios, which reduces a risk of damage to the display devicecaused by overcurrent due to a short circuit or other faults in the signal lineof the display panel, and reduces a risk that the signal lineinterrupts the test of electrostatic discharge capability due to accidental triggering of the overcurrent protection caused by accumulation of static electricity.

304 0 1 2 As illustrated in Table 1, for example: the information stored in the registercan at least include three bits of data from low to high: Bit, Bit, and Bit. Each bit can be 0 or 1, and different values of the three bits of data can be combined into eight types of information “000”, “001” . . . “111”. If each bit of data corresponds to a binary number, then when the value corresponding to the information is decimal i, the corresponding “number of detected frames” can be (i+1), where i is any integer from 0 to 7.

20 20 20 Specifically, combined with the above definitions of “first information” and “second information”, it can be seen that: “first information” is “000”, and the corresponding “number of detected frames” is 1 frame, that is, the overcurrent protection is enabled when detecting the current in the signal lineis greater than the preset current during one frame, and an application scenario at this time may not be the test of electrostatic discharge capability, that is, it is applied to detect whether the signal linehas an overcurrent due to a short circuit or other faults; and “second information” is one of these seven types of information “001” . . . “111”, the corresponding “number of detected frames” is greater than or equal to 2 frames, that is, the overcurrent protection is only enabled when it is detected that the current in the signal lineis greater than the preset current during at least two consecutive frames, and an application scenario at this time may be a test of electrostatic discharge capability.

TABLE 1 Bit2 Bit1 Bit0 Number of detected frames 0 0 0 1 frame  0 0 1 2 frames 0 1 0 3 frames 0 1 1 4 frames 1 0 0 5 frames 1 0 1 6 frames 1 1 0 7 frames 1 1 1 8 frames

304 30 10 20 304 30 10 20 Referring to the above discussion about Table 1, it can be seen that the second information is at least a first sub-information (for example, “001” in Table 1) or a second sub-information (for example, “010” in Table 1). When the information stored in the registerincludes the first sub-information, the driving circuit boardis configured to enable the overcurrent protection of the display panelon a condition that the current in the signal lineis greater than the preset current during two consecutive frames. When the information stored in the registerincludes the second sub-information, the driving circuit boardis configured to enable the overcurrent protection of the display panelon a condition that the current in the signal lineis greater than the preset current during at least three consecutive frames.

20 20 20 It can be understood that when the application scenario is the test of electrostatic release capability, this embodiment is further refined into a plurality of sub-scenarios for testing electrostatic release capability. The difference between the sub-scenarios is that different amounts of electrostatic charges accumulated in the signal lineduring the test of electrostatic discharge capacity. It can be considered that the more the amount of accumulated electrostatic charges, the more frames it takes for the accumulated electrostatic charges to be released until the signal linehas no overcurrent, and in other words, the more frames the overcurrent in the signal linewill last. At this time, in order to avoid enabling the overcurrent protection and interrupting the test of electrostatic discharge capability, it is necessary to set the “number of detected frames” required to enable the overcurrent protection to be larger, that is, the second information is the sub-information corresponding to the decimal number with the larger value.

30 20 It can be seen that in this embodiment, by setting the second information to be a variety of sub-information, the driving circuit boardcan enable the overcurrent protection when the current in the signal lineis greater than the preset current during different numbers of consecutive frames, which is suitable for the test of electrostatic discharge capability under different amounts of accumulated electrostatic charges, further improving the reliability of the test of electrostatic discharge capability.

1 FIG. 2 FIG. 304 30 10 20 Of course, in other embodiments, as illustrated in,, and Table 1, when the information stored in the registerincludes the second information, the driving circuit boardis configured to enable the overcurrent protection of the display panelwhen the current in the signal lineis greater than the preset current during two consecutive frames.

30 304 20 Comparing with the above discussion about Table 1, when the application scenario is the test of electrostatic discharge capability, in this embodiment it can be considered that whether the second information corresponds to only one decimal value or corresponds to a plurality of above decimal values, the driving circuit boardis configured as follows: when the information stored in the registerincludes the second information and the corresponding “number of detected frames” is two frames, that is, on a condition that the application scenario is the test of electrostatic discharge capability, the overcurrent protection is enabled only when detecting that the current in the signal lineis greater than the preset current during two consecutive frames.

20 20 20 100 20 It can be seen that compared with the embodiment in Table 1, in this embodiment, it can be considered that a large current in the signal lineduring the test of electrostatic discharge capability can be converted into a small current through electrostatic discharge within one frame. The embodiment avoids the need to enable the overcurrent protection only when the current in the signal lineis detected to be greater than the preset current during at least three consecutive frames, that is, the overcurrent protection is enabled only when the current in the signal lineis detected to be greater than the preset current during two consecutive frames, which can reduce a risk of damage to the display devicecaused by overcurrent due to a short circuit or other faults of the signal lineduring the test of electrostatic discharge capability.

1 FIG. 3 FIG. 3 FIG. 3 FIG. 30 20 0 20 1 2 30 20 0 20 ck In some embodiments, as illustrated into, the driving circuit boardis configured to determine whether the current in the signal lineis greater than the preset current Iin one frame by determining whether an absolute value of the current (for example, a corresponding signal is a current signal Iin) in the signal lineis greater than the preset current in two periods spaced apart (for example, two ones of four periods tand four periods tin) within the frame; and/or, the driving circuit boardis configured to determine whether the current in the signal lineis greater than the preset current Iin one frame by determining whether the case that the absolute value of the current of the signal lineis greater than the preset current in the frame persists for at least a preset duration.

20 0 20 0 20 0 20 0 20 0 It can be understood that this embodiment further illustrates that within one frame, it is necessary to determine whether the absolute value of the current in the signal lineis greater than the preset current Iin the two periods spaced apart, and/or determine whether the absolute value of the current in the signal linecontinues to be greater than the preset current Iduring a preset duration, so as to determine whether the current in the signal lineis greater than the preset current Iin one frame, thereby improving the reliability of determining whether the current in the signal lineis greater than the preset current Iin the frame, and avoiding accidentally triggering the overcurrent protection due to the absolute value of the current in the signal linebeing greater than the preset current Iin an instant.

1 FIG. 3 FIG. 10 1 50 202 1 2 12 20 202 30 10 202 0 gate gate In some embodiments, as illustrated into, the display panelincludes: the above-mentioned plurality of subpixels P; the above-mentioned plurality of gate lines (GLto GLn); the above-mentioned gate driving circuit (may be the gate driver) electrically connected to the plurality of gate lines and configured to transmit the above-mentioned corresponding gate signals Sto the corresponding plurality of subpixels P through the gate lines; and a plurality of clock signal lineselectrically connected to the gate driving circuit and respectively configured to transmit a plurality of clock signals (for example, CK, CKto CK). The plurality of clock signals are configured for the gate driving circuit to generate the plurality of gate signals S. The signal lineincludes at least one of the clock signal lines. The driving circuit boardis at least configured to enable the overcurrent protection of display panelwhen a current in at least one of the clock signal linesis greater than the preset current Iduring at least two consecutive frames.

30 302 1 2 10 301 50 306 303 302 202 The driving circuit boardincludes: the above-mentioned timing controllerconfigured to generate clock source signals (including, but not limited to, a first clock source signal CLKand a second clock source signal CLKand configured to drive the display panelto display images (through the source driverand the gate driver); and a level converter(for example, included in the power manager) electrically connected to the timing controllerand the plurality of clock signal linesand configured to generate the plurality of clock signals in response to the clock source signals.

1 FIG. 2 FIG. 305 303 306 302 1 2 306 306 1 2 12 1 2 202 gate Specifically, as illustrated inand, a voltage generatorincluded in the power managercan provide a high-voltage signal VGH and a low-voltage signal VGL with different amplitudes to the level converter, and the timing controllercan provide a first clock source signal CLKand a second clock source signal CLK(both clock signals) with a phase difference therebetween to the level converter. The convertercan generate the plurality of clock signals (for example, CK, CKto CK) based on the phases of the first clock source signal CLKand the second clock source signal CLKand the amplitudes of the high-voltage signal VGH and the low-voltage signal VGL, and the plurality of clock signals are transmitted to the gate driving circuit respectively through the plurality of clock signal lines. Each stage of gate driving unit of the gate driving circuit generates a corresponding one of the gate signal Sin response to at least two of the clock signals.

304 306 10 202 0 306 306 303 The registermay be included in the level converter. An execution subject of the above-mentioned “enabling the overcurrent protection of the display panelwhen the current in the clock signal lineis greater than the preset current Iduring at least two consecutive frames” may be the level converter. The level convertermay also be set independently from the power manager.

202 30 202 100 It can be understood that this embodiment considers that the current in the clock signal lineis easily large and causes overcurrent. Therefore, the object of the current detected by the driving circuit boardmay be a current in the clock signal line, which can greatly reduce the risk of damage to the display devicedue to overcurrent.

20 202 306 202 When the signal linehaving the current to be detected includes at least one of the clock signal lines, enabling the overcurrent protection may at least include controlling the level converterto no longer output the corresponding clock signal, so that the corresponding clock signal linebecomes to have a high resistance state, thereby reducing the corresponding current.

1 2 1 1 2 1 1 1 2 2 2 30 306 20 0 1 1 2 2 0 3 FIG. ck Based on the above discussion, it can be seen that since the first clock source signal CLKand the second clock source signal CLKare both clock signals, as illustrated in, an amplitude of the clock signal (is a voltage signal, shown as CK) accordingly generated alternates between a first potential Vpand a second potential Vpwithin one frame. The current signal Icorresponding to the current in the clock signal line includes a first sub-current signal I/I′ corresponding to the first potential Vpand a second sub-current signal I/I′ corresponding to the second potential Vp. During one frame, the driving circuit board(the level converterincluded therein) is configured to determine whether the current in the signal lineis greater than the preset current Iduring the frame by determining whether an absolute value of a potential of at least one first sub-current signal I/I′ when it is stable and/or an absolute value of a potential of at least one second sub-current signal I/I′ when it is stable is greater than the preset current I.

3 FIG. 1 1 1 1 1 2 202 1 gate ck Specifically, as illustrated in, after the high-voltage signal VGH reaches a certain proportion (for example, 80%) of its maximum value and lasts for a first time period T(for example, 130 ms), it is considered to be stable. After that, an appearance of a first frame start pulse spof a frame start signal STV indicates the beginning of a first frame F, and the amplitude of the clock signal CKalternates between the first potential Vpand the second potential Vp, so that the corresponding gate driving unit generates the corresponding gate signal S. An amplitude of the corresponding current signal Itransmitted in the clock signal linedrops sharply and rises sharply respectively on a rising edge and a falling edge of the clock signal CK.

1 2 1 1 0 1 1 2 2 2 0 2 ck ck ck ck On the rising edge of the clock signal CK, after a second time period T(for example, 4 μs), the amplitude of the current signal Ii.e., an absolute value (i.e., the potential of the first sub-current signal I/I′ when it is stable) of the current signal Imay be greater than, less than, or equal to the preset current Ipersisting for a duration such as 2 μs (i.e., during the corresponding period t). In the same way, on the falling edge of the clock signal CK, after the second time period T(for example, 4 μs), the amplitude of the current signal I, i.e., an absolute value (i.e., the potential of the second sub-current signal I/I′ when it is stable) of the current signal Imay be greater than, less than, or equal to the preset current Ipersisting for a duration such as 2 μs (i.e., during the corresponding period t).

20 0 1 1 2 2 0 1 1 2 2 20 0 1 1 2 2 0 Specifically, this embodiment determines whether the current in the signal lineis greater than or equal to the preset current Iduring a frame by determining whether at least one of the absolute values of the potential of the first sub-current signal I/I′ when it is stable and the potential of the second sub-current signal I/I′ when it is stable is greater than the preset current I. Since a number of the first sub-current signals I/I′ in one frame and a number of the second sub-current signals I/I′ are the same, it can be actually determined whether the current in the signal lineis greater than the preset current Iduring this frame by determining whether the absolute values of the potentials of j consecutive first sub-current signals I/I′ when they are stable and/or the absolute values of the potentials of j consecutive second sub-current signals I/I′ when they are stable are greater than the preset current I, where j is a positive integer.

1 1 2 2 0 1 2 0 0 1 2 0 0 ck ck ck ck 3 FIG. For example, when j=4, it means to determine whether the absolute values of the potentials of four consecutive first sub-current signals I/I′ when they are stable and/or the absolute values of the potentials of four second sub-current signals I/I′ when they are stable are all greater than the preset current I. For example, the current signal Iinincludes four consecutive first sub-current signals Iand four consecutive second sub-current signals I. Since the absolute values of the potentials of the eight sub-current signals when they are stable are all less than the preset current I, the current signal Iis considered to be less than the preset current Iduring this frame. For another example, the current signal Iincludes four consecutive first sub-current signals I′ and four consecutive second sub-current signals I′. Since the absolute values of the potentials of the eight sub-current signals when they are stable are all greater than the preset current I, the current signal Iis considered to be greater than the preset current Iduring this frame.

ck ck 202 0 1 1 1 2 2 0 20 0 It can be seen that in this embodiment, on the premise of determining whether the current signal Iof the clock signal lineis greater than the preset current Iduring at least two consecutive frames, considering that the clock signal CKis a clock signal, the determination is performed based on value relationships between the absolute values of the potentials of the sub-current signals I/I′ and the second sub-current signals I/I′ of the corresponding current signal Iwhen they are stable and the preset current I, thereby further improving the reliability of determining “whether the current in the signal lineis greater than or equal to the preset current Iduring the frame(s)”.

3 FIG. 10 202 1 0 1 1 2 only illustrates that the overcurrent protection of the display panelis enabled when the current in the clock signal lineconfigured for transmitting the clock signal CKis greater than the preset current Iduring consecutive k frames (for example, from the first frame Fto a k-th frame Fk), where k is a positive integer greater than 1. In practical applications, values of k, j, a time duration of the period t, a time duration of the period t, etc. are not limited.

1 FIG. 4 FIG. 1 2 3 1 2 3 1 1 2 3 10 1 2 3 301 301 50 In some embodiments, as illustrated inand, the plurality of subpixels P include a plurality of first subpixels P, a plurality of second subpixels P, and a plurality of third subpixels P. The first subpixel P, the second subpixel P, and the third subpixel Phave different colors. Each of the gate lines (each of GLto GLn) is connected to a corresponding plurality of first subpixels P, a corresponding plurality of second subpixels P, or a corresponding plurality of third subpixels P. That is to say, the display panelin this embodiment has a three-gate structure. Specifically, each gate line is connected to a plurality of subpixels P of the same color. At this time, three subpixels P in one pixel unit (including one first subpixel P, one second subpixel P, and one third subpixel P) originally connected to one same gate line T need to be electrically connected three gate lines, respectively, thereby reducing a number of output terminals of the source driveror a number of source drivers, but the number of gate lines will be tripled, resulting in that a time period for the gate driverto scan each row of subpixels P is shortened to one-third of the original time.

gate 20 It can be understood that this embodiment further limits the application scenario of the above overcurrent protection mechanism to the tri-gate architecture. Since a duration of the gate signal Sin the tri-gate architecture is short after its gate pulse in one frame, the charges accumulated during the test of electrostatic discharge capability cannot be fully released, resulting in a greater risk of large current in the signal linewithin this frame. Therefore, the above-mentioned overcurrent protection mechanism has a greater benefit in improving the reliability of the test of electrostatic discharge capability.

1 FIG. 2 FIG. 10 40 50 40 201 40 20 201 30 10 201 In some embodiments, as illustrated inand, the display panelincludes: the above-mentioned plurality of subpixels P; the above-mentioned plurality of pixel circuitseach electrically connected to corresponding subpixels P; a gate driving circuit (i.e. the above-mentioned gate driver) electrically connected to the plurality of pixel circuits; and the above-mentioned plurality of power signal lineseach electrically connected to the gate driving circuit and at least one of the plurality of pixel circuits. The signal lineincludes at least one power signal line. The driving circuit boardis at least configured to enable the overcurrent protection of the display panelwhen the current in the at least one power signal lineis greater than the preset current during at least two consecutive frames.

40 303 201 10 303 201 201 30 10 201 100 Based on the above discussion, it can be seen that the plurality of pixel circuitsare electrically connected to the power managerthrough the plurality of power signal lines. Of course, the gate driving circuit in the display panelis also electrically connected to the power managerthrough the plurality of power signal lines. Considering that the power signal linealso has the risk of overcurrent when it is short-circuited or during the test of electrostatic discharge capability, in this embodiment, the driving circuit boardis further configured to control whether to enable the overcurrent protection of the display panelbased on whether the current in the power signal lineis greater than the preset current during at least two consecutive frames. This further reduces the risk of damage to the display devicecaused by overcurrent and reduces the risk of interrupting the test of electrostatic discharge capability.

5 FIG. In order to better explain the above display device, the present disclosure also provides a driving method of the display device. As illustrated in, the driving method may include, but is not limited to, the following steps and a combination of the following steps.

1 Step S, in which the driving circuit board acquires the current in the signal line of the display panel.

2 Step S, in which, in the first working mode, the driving circuit board determines whether the current in the signal line is greater than the preset current during at least two consecutive frames.

If yes, executing:

3 Step S, in which the driving circuit board performs overcurrent protection on the display panel.

20 202 1 306 30 20 201 1 305 302 30 Based on the above discussion, it can be seen that when the signal linehaving the current to be detected includes the clock signal line, an execution subject in step Smay specifically include the level converterincluded in the driving circuit board. Of course, when the signal linehaving the current to be detected includes the power signal line, the execution subject in step Smay specifically include the voltage generatoror the timing controllerincluded in the driving circuit board.

20 Regarding how to determine whether the current in the signal lineis greater than the preset current during at least two consecutive frames, reference may be made to the relevant discussion above.

The display device and the driving method of provided by the embodiments of the present disclosure are introduced in detail above. Specific examples are used in this paper to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand technical solutions and their core ideas of the present disclosure. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not make the essence of the corresponding technical solutions to be deviated from the scope of the technical solution in each embodiment of the present disclosure.