Display device and electronic device including the same

The present application claims priority to and the benefit of Korean Patent Application No. 10-2024-0044878, filed on Apr. 2, 2024, and to the benefit of Korean Patent Application No. 10-2024-0189713, filed on Dec. 18, 2024, in the Korean Intellectual Property Office, the entire disclosures of each of which are incorporated herein by reference.

Aspects of some embodiments of the present disclosure generally relate to a display device and an electronic device including the display device.

With the development of information technologies, the importance of a display device which provides a connection medium between a user and information increases. Accordingly, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly used.

A display device generally has a structure in which a gate driver is located at a side of a pixel unit. Due to a gate line delay, a variation in gate signal may occur as approaching an end of a gate line, and accordingly, display quality may be deteriorated.

The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art.

Aspects of some embodiments include a display device for dividing a gate line according to a distance between a gate driver and a pixel and an electronic device including the display device so as to reduce a gate line delay.

According to some embodiments of the present disclosure, a display device includes: a display panel including a first block and a second block, the display panel having a plurality of pixels; and a first gate driver configured to a gate signal to the first block and the second block, wherein the first gate driver provides the gate signal to a first sub-gate line connected to the first block through a first buffer and a first slew rate controller, and provides the gate signal to a second sub-gate line connected to the second block through a second buffer, and wherein the first block is closer to the first gate driver than the second block.

According to some embodiments, the first slew rate controller may control a slew rate of the first sub-gate line such that the slew rate of the first sub-gate line and a slew rate of the second sub-gate line are the same.

According to some embodiments, numbers of inverters included in the first buffer and the second buffer are the same.

According to some embodiments, a number of inverters included in the first buffer may be smaller than a number of inverters included in the second buffer.

According to some embodiments, a pixel most distant from the first gate driver in the first block and a pixel closest to the first gate driver in the second block may have the same resistor-capacitor delay value.

According to some embodiments, the display device may further include a dummy gate line in the second block to have the same pattern shape as pixels of the first block.

According to some embodiments, the dummy gate line may extend in a direction distant from the first gate driver at a scan start point of the second block.

According to some embodiments, the dummy gate line may extend with a margin at the scan start point of the second block.

According to some embodiments, the second sub-gate line and the dummy gate line may be formed in the same metal layer.

According to some embodiments, a scan start point of the first sub-gate line in the second block may be a middle point of the second block.

According to some embodiments, a scan start point of the first sub-gate line in the second block may be a pixel closest to the first gate driver in the second block.

According to some embodiments, a scan start point of the first sub-gate line in the second block may be a pixel most distant from the first gate driver in the second block.

According to some embodiments, the display panel may further include a third block and a fourth block. According to some embodiments, the display device may further include a second gate driver configured to provide the gate signal to the third block and the fourth block. According to some embodiments, the second gate driver may provide the gate signal to a third sub-gate line connected to the third block through a third buffer and a second slew rate controller, and provide the gate signal to a fourth sub-gate line connected to the fourth block through a fourth buffer. According to some embodiments, the third block may be closer to the first gate driver than the fourth block.

According to some embodiments of the present disclosure, a display device includes: a display panel including a first block and a second block, the display panel having a plurality of pixels; and a first gate driver configured to provide a gate signal to the first block and the second block, wherein the first gate driver provides the gate signal to a first sub-gate line connected to the first block through a first buffer, and provides the gate signal to a second sub-gate line connected to the second block through a second buffer, and wherein the first block is closer to the first gate driver than the second block.

According to some embodiments, a number of inverters included in the first buffer may be smaller than a number of inverters included in the second buffer.

According to some embodiments, the first buffer may control a slew rate of the first sub-gate line such that the slew rate of the first sub-gate line and a slew rate of the second sub-gate line are the same.

According to some embodiments, the first gate driver may provide the gate signal to the first sub-gate line through the first buffer and a slew rate controller. According to some embodiments, a number of inverters included in the first buffer may be equal to a number of inverters included in the second buffer.

According to some embodiments, a pixel most distant from the first gate driver in the first block and a pixel closest to the first gate driver in the second block may have the same resistor-capacitor delay value.

According to some embodiments, the display device may further include a dummy gate line in the second block to have the same pattern shape as pixels of the first block.

According to some embodiments, the dummy gate line may extend in a direction distant from the first gate driver at a scan start point of the second block.

In accordance with an aspect of the present disclosure, there is provided an electronic device including: a processor, and a display device configured to display an image in response to control of the processor, wherein the display device includes: a display panel including a first block and a second block, the display panel having a plurality of pixels therein, and a first gate driver configured to provide a gate signal to the first block and the second block, wherein the first gate driver: provides the gate signal to a first sub-gate line connected to the first block through a first buffer and a first slew rate controller, and provides the gate signal to a second sub-gate line connected to the second block through a second buffer, and wherein the first block is closer to the first gate driver than the second block.

Hereinafter, aspects of some embodiments of the present disclosure are described in detail with reference to the accompanying drawings so that those skilled in the art may easily practice the present disclosure. Embodiments according to the present disclosure may be implemented in various different forms and is not limited to the disclosed embodiments described in the present specification.

Certain components that are irrelevant to enabling a person having ordinary skill in the art to understand the invention may be omitted to more clearly describe aspects of some embodiments of the present disclosure, and the same or similar constituent elements will be designated by the same reference numerals throughout the specification. Therefore, the same reference numerals may be used in different drawings to identify the same or similar elements.

In description, the expression “equal” may mean “substantially equal.” That is, this may mean equality to a degree to which those skilled in the art can understand the equality. Other expressions may be expressions in which “substantially’ is omitted.

Some embodiments are described in the accompanying drawings in relation to functional blocks, units, and/or modules. Those skilled in the art will understand that these blocks, units, and/or modules are physically implemented by logic circuits, individual components, microprocessors, hard wire circuits, memory elements, line connection, and other electronic circuits. This may be formed by using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units, and/or modules implemented by microprocessors or other similar hardware, the units, and/or modules are programmed and controlled by using software, to perform various functions discussed in the present disclosure, and may be selectively driven by firmware and/or software. In addition, each block, each unit, and/or each module may be implemented by dedicated hardware or by a combination dedicated hardware to perform some functions of the block, the unit, and/or the module and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions of the block, the unit, and/or the module. In some embodiments, the blocks, the units, and/or the modules may be physically separated into two or more individual blocks, two or more individual units, and/or two or more individual modules without departing from the scope of the present disclosure. Also, in some embodiments, the blocks, the units, and/or the modules may be physically separated into more complex blocks, more complex units, and/or more complex modules without departing from the scope of the present disclosure.

The term “connection” between two components may include both electrical connection and physical connection, but embodiments according to the present disclosure are not limited thereto. For example, the term “connection” used based on circuit diagrams may mean electrical connection, and the term “connection” used based on sectional and plan views may mean physical connection.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a “first” element discussed below could also be termed a “second” element without departing from the teachings of the present disclosure.

Meanwhile, the present disclosure is not limited to embodiments disclosed below, and may be implemented in various forms. Each embodiment disclosed below may be independently embodied or be combined with at least another embodiment prior to being embodied.

1 FIG. is a block diagram illustrating aspects of a display device according to some embodiments.

1 FIG. 100 110 120 130 140 150 Referring to, the display devicemay include a display panel, a gate driver, a data driver, a voltage generator, and a controller.

110 120 1 130 1 The display panelmay include sub-pixels SP. The sub-pixels SP may be connected to the gate driverthrough first to mth gate lines GLto GLm. The sub-pixels SP may be connected to the data driverthrough first to nth data lines DLto DLn.

1 FIG. Each of the sub-pixels SP may include at least one light emitting element configured to generate light. Accordingly, each of the sub-pixels SP may generate light of a specific color such as red, green, blue, cyan, magenta or yellow. Two or more sub-pixels among the sub-pixels SP may constitute one pixel PX. For example, three sub-pixels SP may constitute one pixel PX as shown in.

120 1 120 1 The gate drivermay be connected to the sub-pixels SP arranged in a row direction through the first to mth gate lines GLto GLm. The gate drivermay output gate signals to the first to mth gate lines GLto GLm in response to a gate control signal GCS. According to some embodiments, the gate control signal GCS may include a start signal indicating a start of each frame, a horizontal synchronization signal for outputting gate signals in synchronization with timings at which data signals are applied, and the like.

1 120 1 150 According to some embodiments, first to mth light emitting control lines ELto ELm connected to the sub-pixels SP in the row direction may be further provided. The gate drivermay include an emission control driver configured to control the first to mth emission control lines ELto ELm, and the emission control driver may operate under the control of the controller.

120 110 120 110 110 120 110 The gate drivermay be located at one side of the display panel. However, embodiments according to the present disclosure are not limited thereto. For example, the gate drivermay be divided into two or more drivers which are physically and/or logically divided, and these drivers may be located at one side of the display paneland the other side of the display panel, which is opposite to the one side. As such, in some embodiments, the gate drivermay be arranged in various forms at the periphery of the display panel.

130 1 130 150 130 The data drivermay be connected to the sub-pixels SP arranged in a column direction through the first to nth data lines DLto DLn. The data drivermay receive image data DATA and a data control signal DCS from the controller. The data drivermay operate in response to the data control signal DCS. According to some embodiments, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

130 1 140 1 1 110 The data drivermay apply data signals having grayscale voltages corresponding to the image data DATA to the first to nth data lines DLto DLn by using voltages from the voltage generator. When a gate signal is applied to each of the first to mth gate lines GLto GLm, data signals corresponding to the image data DATA may be applied to the data line DLto DLm. Accordingly, corresponding sub-pixels SP may generate light corresponding to the data signals. Accordingly, an image may be displayed on the display panel.

120 130 According to some embodiments, the gate driverand the data drivermay include complementary metal-oxide semiconductor (CMOS) circuit elements.

140 150 140 100 140 100 The voltage generatormay operate in response to a voltage control signal VCS from the controller. The voltage generatormay be configured to generate a plurality of voltages and provide the generated voltages to components of the display device. For example, the voltage generatormay be configured to generate a plurality of voltages by receiving an input voltage from the outside of the display device, adjusting the received voltage, and regulating the adjusted voltage.

140 100 The voltage generatormay generate a first power voltage VDD and a second power voltage VSS, and the generated first and second power voltages VDD and VSS may be provided to the sub-pixels SP. The first power voltage VDD may have a relatively high voltage level, and the second power voltage VSS may have a voltage level lower than the voltage level of the first power voltage VDD. According to some embodiments, the first power voltage VDD or the second power voltage VSS may be provided by an external device of the display device.

140 140 1 140 Besides, the voltage generatormay generate various voltages. For example, the voltage generatormay generate an initialization voltage applied to the sub-pixels SP. For example, a reference voltage (e.g., a set or predetermined reference voltage) may be applied to the first to nth data lines DLto DLn in a sensing operation for sensing electrical characteristics of transistors and/or light emitting elements of the sub-pixels SP, and the voltage generatormay generate the reference voltage.

150 100 150 150 The controllermay control overall operations of the display device. The controllermay receive, from the outside, input image data IMG and a control signal CTRL for controlling display thereof. The controllermay provide the gate control signal GCS, the data control signal DCS, and the voltage control signal VCS in response to the control signal CTRL.

150 100 110 150 The controllermay convert the input image data IMG to be suitable for the display deviceor the display panel, thereby outputting the image data DATA. According to some embodiments, the controllermay align the input image data IMG to be suitable for the sub-pixels SP in units of rows, thereby outputting the image data DATA.

130 140 150 130 140 150 130 140 150 130 140 150 1 FIG. Two or more components among the data driver, the voltage generator, and the controllermay be mounted on one integrated circuit. As shown in, the data driver, the voltage generator, and the controllermay be included in a driver integrated circuit DIC. The data driver, the voltage generator, and the controllermay be components functionally divided in one driver integrated circuit DIC. According to some embodiments, at least one of the data driver, the voltage generator, or the controllermay be provided as a component distinguished from the driver integrated circuit DIC.

100 160 160 160 110 The display devicemay include at least one temperature sensor. The temperature sensormay be configured to sense a temperature at the periphery thereof and generate temperature data TEP indicating the sensed temperature. According to some embodiments, the temperature sensormay be arranged to be adjacent to the display paneland/or the driver integrated circuit DIC.

150 100 150 100 150 130 140 The controllermay control various operations of the display devicein response to the temperature data TEP. According to some embodiments, the controllermay adjust the luminance of an image output from the display panelin response to the temperature data TEP. For example, the controllermay control components such as the data driverand/or the voltage generator, thereby adjusting data signals and the first and second power voltages VDD and VSS.

2 FIG. 1 FIG. 2 FIG. 1 FIG. is a block diagram illustrating aspects of any one of the sub-pixels shown inaccording to some embodiments. In, a sub-pixel SPij arranged on an ith row (i is an integer greater than or equal to 1 and smaller than or equal to m) and a jth column (j is an integer greater than or equal to 1 and smaller than or equal to n) among the sub-pixels SP shown inis illustrated.

2 FIG. Referring to, the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

1 FIG. 1 FIG. The light emitting element LD may be connected between a first power voltage node VDDN and a second power voltage node VSSN. The first power voltage node VDDN may be a node transferring the first power voltage VDD shown in, and the second power voltage node VSSN may be a node transferring the second power voltage VSS shown in.

An anode electrode AE of the light emitting element LD may be connected to the first power voltage node VDDN through the sub-pixel circuit SPC, and a cathode electrode CE of the light emitting element LD may be connected to the second power voltage node VSSN. For example, the anode electrode AE of the light emitting element LD may be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

1 1 1 1 FIG. 1 FIG. 1 FIG. The sub-pixel circuit SPC may be connected to an ith gate line GLi among the first to mth gate lines GLto GLm shown in, an ith emission control line ELi among the first to mth emission control lines ELto ELm shown in, and a jth data line DLj among the first to nth data lines DLto DLn shown in. The sub-pixel circuit SPC may be configured to control the light emitting element LD according to signals received through these signal lines.

The sub-pixel circuit SPC may operate in response to a gate signal received through the ith gate line GLi. The ith gate line GLi may include one or more sub-gate lines. According to some embodiments, when the ith gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to gate signals received through the corresponding sub-gate lines.

The sub-pixel circuit SPC may operate in response to an emission control signal received through the ith emission control line ELi. According to some embodiments, the ith emission control line ELi may include one or more sub-emission control lines. When the ith emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to emission control signals receives through the corresponding emission control lines.

The sub-pixel circuit SPC may receive a data signal through the jth data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the sub-gate lines. The sub-pixel circuit SPC may control a current flowing from the first power voltage node VDDN to the second power voltage node VSSN through the light emitting element LD according to the stored voltage in response to the emission control signal received through the ith emission control line ELi. Accordingly, the light emitting element LD may generate light with a luminance corresponding to the data signal.

3 FIG. 1 FIG. is a diagram illustrating aspects of the connection relationship between the gate driver and the pixels shown inaccording to some embodiments.

3 FIG. 110 120 Referring to, the pixels of the display panelmay be connected to separate gate lines according to distances from the gate driver.

110 120 1 The display panelmay be divided into a first block NA and a second block FA. The first block NA and the second block FA may be sequentially arranged in a direction distant from the gate driver(a first direction DR).

120 1 As the distances from the gate driverto the pixels located in the first block NA and the second block FA increase, the resistance and parasitic capacitance of the first to mth gate lines GLto GLm may increase. Accordingly, a time for which a voltage of the gate signal is changed to a desired voltage level may be increased by a resistor-capacitor (RC) delay, and slew rates of the first block NA and the second block FA may be different from each other.

110 120 110 As the first block NA and the second block FA have the different slew rates, the image quality of the display panelmay be degraded. By adjusting the slew rate based on the distance between the gate driverand a pixel, the image quality of the display panelmay be improved.

120 100 1 To adjust the slew rate based on the distance between the gate driverand the pixel, the display devicemay include a plurality of buffers BF and a slew rate controller SL. Each of the plurality of buffers BF may be connected to each of the first to mth gate lines GLto GLm. Each of the plurality of buffers BF may adjust an output time of the gate signal.

1 The slew rate controller SL may control the slew rate of first sub-gate lines NLto NLm such that the slew rate of the first block NA may be equal to the slew rate of the second block FA. The slew rate controller SL may compensate for a RC delay of the first block NA which is smaller than the second block FA. The slew rate controller SL may decrease the slew rate of the first block NA. Accordingly, the slew rate between the first block NA and the second block FA may be constant.

1 120 1 1 120 2 The first sub-gate lines NLto NLm may receive a gate signal from the gate driverthrough the first buffer BFand the slew rate controller SL. Second sub-gate lines FLto FLm may receive a gate signal from the gate driverthrough the second buffer BF.

1 1 The pixels located in the first block NA may be connected to the first sub-gate lines NLto NLm, and the pixels located in the second block FA may be connected to the second sub-gate lines FLto FLm.

1 1 120 1 120 1 For example, based on the first direction DR, pixels between a pixel FPclosest to the gate driveramong the pixels located in the first block NA and a pixel LPfarthest from the gate driveramong the pixels located in the first block NA may be connected to the first sub-gate lines NLto NLm.

1 2 120 2 120 1 1 Further, based on the first direction DR, pixels from a pixel FPclosest to the gate driveramong the pixels located in the second block FA to a pixel LPfarthest from the gate driveramong the pixels located in the second block FA may be connected to the second sub-gate lines FLto FLm. Due to the wiring design structure, the second sub-gate lines FLto FLm may overlap with the first block NA, but may not be connected to the pixels located in the first block NA.

1 1 1 1 The first sub-gate lines NLto NLm and the second sub-gate lines FLto FLm may be located in the same metal layer. Also, however, the first sub gate lines NLto NLm and the second sub gate lines FLto FLm may be located in different metal layers.

1 2 1 2 In embodiments, ranges of the first block NA and the second block FA may be determined such that no luminance difference may occur between the pixel LPof the first block NA and the pixel FPof the second block FA. More specifically, the ranges of the first block NA and the second block FA may be determined such that the pixel LPof the first block NA and the pixel FPof the second block FA may have the same RC delay.

1 1 1 120 Dummy gate lines DMLto DMLm may be located in the second block FA. For example, at points where the second sub-gate lines FLto FLm are first connected to the pixels of the second block FA, the dummy gate lines DMLto DMLm may extend in a direction distant from the gate driver.

1 1 In embodiments, the dummy gate lines DMLto DMLm may be placed with a margin at the points where the second sub-gate lines FLto FLm are first connected to the pixels of the second block FA.

1 1 1 As the dummy gate lines DMLto DMLm are arranged in the second block FA, the pixels arranged in the second block FA may be connected to the first sub-gate lines NLto NLm and have the same pattern phenomenon as the pixels arranged in the first block NA where the second sub-gate lines FLto FLm are arranged.

1 1 1 The dummy gate lines DMLto DMLm and the second sub-gate lines FLto FLm may be located on the same metal layer. According to embodiments, both ends of the dummy gate lines DMLto DMLm may be floated, connected to a ground node, or connected to an arbitrary bias.

4 FIG. 3 FIG. is a diagram illustrating an example of the slew rate controller SL shown in.

4 FIG. 4 FIG. 3 FIG. 110 120 110 120 Referring to, the slew rate controller SL may include a resistor R and a capacitor C. The display paneland the gate driveras shown inare similar to the display paneland the gate driveras shown. Therefore, a redundant description thereof is omitted.

1 1 1 1 a The resistor R may be connected between the first buffer BFand the first node Nlocated on first sub-gate lines NLto NLma. The capacitor C may be connected between the first node Nand a ground node GND to which ground power is applied. However, the present disclosure is not limited thereto. The slew rate controller SL may include a plurality of resistors and a plurality of capacitors.

The resistor R may include silicide or non-silicide. The capacitor C may be configured as a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, or a metal-oxide-semiconductor (MOS) capacitor.

5 FIG. 3 FIG. is a circuit diagram illustrating aspects of the buffer shown inaccording to some embodiments.

5 FIG. 1 1 Referring to, the first buffer BFmay include a plurality of inverters INVto INVK. Here, K may be an integer greater than or equal to 1.

1 1 2 1 2 1 2 Each of the plurality of inverters INVto INVK may include a first transistor Mand a second transistor M, which are connected in series. For example, the first transistor Mmay be a PMOS transistor, and the second transistor Mmay be an NMOS transistor. The first transistor Mand the second transistor Mmay be connected to a first power voltage node VDDN and a second power voltage node VSSN.

1 1 1 a An input terminal of each of the plurality of inverters INVto INVK may be connected to the first gate line GL, and an output terminal of each of the plurality of inverters INVto INVK may be connected to the slew rate controller SL.

1 2 1 1 2 5 FIG. 4 FIG. 3 FIG. Although the first buffer BFis illustrated in, the second buffer BFshown inmay have the same structure as the first buffer BF. Referring to, numbers of inverters included in the first buffer BFand the second buffer BFmay be the same.

1 2 1 2 1 2 However, according to some embodiments, a number of inverters included in the first buffer BFmay be smaller than a number of inverters included in the second buffer BF. A size of the slew rate controller SL when the number of inverters included in the first buffer BFmay be smaller than the number of inverters included in the second buffer BFmay be smaller than a size of the slew rate controller SL when the numbers of inverters included in the first buffer BFand the second buffer BFmay be the same.

In embodiments, the size of the slew rate controller SL may be adjusted by controlling the size of the resistor and the capacitor included in the slew rate controller SL.

6 FIG. 1 FIG. is a diagram illustrating aspects of the connection relationship between the gate driver and the pixels shown inaccording to some embodiments.

6 FIG. 6 FIG. 3 FIG. 110 120 110 120 Referring to, the pixels of the display panelmay be connected to separate gate lines according to distances from the gate driver. The connection relationship between the pixels of the display paneland the gate driveras shown inmay be similar to that shown in. Accordingly, redundant descriptions thereof are omitted.

1 120 1 1 120 2 The first sub-gate lines NLto NLm may receive a gate signal from the gate driverthrough the first buffer BF. The second sub-gate lines FLto FLm may receive a gate signal from the gate driverthrough the second buffer BF.

5 FIG. 1 2 1 1 1 1 Referring to, the number of inverters included in the first buffer BFmay be smaller than the number of inverters included in the second buffer BF. The first buffer BFmay adjust the slew rates of the first sub-gate lines NLto NLm such that the slew rates of the first sub-gate lines NLto NLm may be equal to the slew rates of the second sub-gate lines FLto FLm.

7 FIG. 1 FIG. is a diagram illustrating aspects of the connection relationship between a gate driver and pixels shown inaccording to some embodiments.

7 FIG. 7 FIG. 3 FIG. 110 120 110 120 Referring to, the pixels of the display panelmay be connected to separate gate lines according to distances from the gate driver. The connection relationship between the pixels of the display paneland the gate driverinmay be similar to that shown in. Accordingly, a redundant description thereof is omitted.

1 120 1 1 120 2 The first sub-gate lines NLto NLm may receive a gate signal from the gate driverthrough the first buffer BF. The second sub-gate lines FLto FLm may receive a gate signal from the gate driverthrough the second buffer BF.

3 7 FIGS.and 1 Referring to, the second sub-gate lines FLto FLm may have different arrangements

3 FIG. 3 FIG. 1 1 2 2 In, the points at which the second sub-gate lines FLto FLm are first connected to the pixels of the second block FA may be the center point of the second block FA. That is, in, a scan start point of the second block FA may be the center point of the second block FA. Through the second sub-gate lines FLto FLm, the second block FA may be scanned starting from the center point of the second block FA to the pixel FPand the pixel LP.

7 FIG. 7 FIG. 1 2 120 1 2 1 2 2 In, the points at which the second sub-gate lines FLto FLm are first connected to the pixels of the second block FA may be the pixel FP, which is the closest pixel to the gate driveramong the pixels located in the second block FA, relative to the first direction DR. In other words, in, the scan start point of the second block FA may be the pixel FP. The second sub-gate lines FLto FLm may be scanned starting from the pixel FPto the pixel LP.

1 2 1 2 In embodiments, the number of inverters included in each of the first buffer BFand the second buffer BFmay be adjusted. The number of inverters included in the first buffer BFmay be adjusted so as to be less than the number of inverters included in the second buffer BF, thereby reducing the size of the slew rate controller SL or omitting the slew rate controller SL.

8 FIG. 7 FIG. is an enlarged diagram of the second block FA shown in.

8 FIG. 2 2 1 1 Referring to, the connection relationship of the pixels FPand LP, the second sub-gate lines FL, and the dummy gate line DMLincluded in the second block FA are shown.

2 2 11 12 13 Each of the pixels FPand LPmay include three sub-pixels SP, SP, and SP.

11 2 1 11 2 13 2 The scan start point of the second block FA may be the first sub-pixel SPof the pixel FP. The second sub-gate line FLmay be scanned starting from the first sub-pixel SPof the pixel FPto the third sub-pixel SPof the pixel LP.

1 1 120 11 2 1 The dummy gate line DMLmay extend in a direction (DR) distant from the gate driverfrom the first sub-pixel SPof the pixel FPwhere the second sub-gate line FLis first connected to the pixels of the second block FA.

1 1 In embodiments, the dummy gate line DMLmay be arranged with a margin at the point where the dummy gate line DMLis first connected to the pixels of the second block FA.

8 FIG. 1 11 2 12 2 Referring to, the dummy gate line DMLmay extend from the first sub-pixel SPof the pixel FPto the second sub-pixel SPof the pixel FPwith a margin.

9 FIG. 1 FIG. is a diagram illustrating aspects of the connection relationship between a gate driver and pixels shown inaccording to some embodiments.

9 FIG. 9 FIG. 3 FIG. 110 120 110 120 Referring to, the pixels of the display panelmay be connected to separate gate lines according to distances from the gate driver. The connection relationship between the pixels of the display paneland the gate driverinmay be similar to that shown in. Accordingly, a redundant description thereof is omitted.

1 120 1 1 120 2 The first sub-gate lines NLto NLm may receive a gate signal from the gate driverthrough the first buffer BFand the slew rate controller SL. The second sub-gate lines FLto FLm may receive a gate signal from the gate driverthrough the second buffer BF.

3 9 FIGS.and 1 Referring to, the second sub-gate lines FLto FLm may have different arrangements

9 FIG. 9 FIG. 1 2 120 1 2 1 2 2 In, the points at which the second sub-gate lines FLto FLm are first connected to the pixels of the second block FA may be the pixel LP, which is the farthest pixel from the gate driveramong the pixels located in the second block FA, relative to the first direction DR. In other words, in, the scan start point of the second block FA may be the pixel LP. The second sub-gate lines FLto FLm may be scanned starting with the pixel LPto the pixel FP.

3 7 FIGS.and 9 FIG. Unlike the embodiments shown in, the embodiments disclosed inmay not include the dummy gate lines.

1 2 1 2 In embodiments, the number of inverters included in the first buffer BFand the second buffer BFmay be adjusted. The number of inverters included in the first buffer BFmay be adjusted so as to be less than the number of inverters included in the second buffer BF, thereby reducing the size of the slew rate controller SL or omitting the slew rate controller SL.

10 FIG. 1 FIG. 120 is a diagram illustrating aspects of the gate driverincluded in the display device shown inaccording to some embodiments.

10 FIG. 120 121 122 Referring to, the gate drivermay include a first gate driverand a second gate driver. For simplification of the drawing, some components that are not necessary to enable a person having ordinary skill in the art to make, use, and understand embodiments according to the present disclosure may be omitted so as to clarify the description of the present disclosure.

121 110 122 110 121 122 110 The first gate drivermay be located at a first side of the display panel. The second gate drivermay be located at a second side of the display panel. According to some embodiments, the first and second gate driversandmay be arranged to be spaced apart from each other with the display panelinterposed therebetween.

121 1 1 121 1 a ma b A gate signal generated by the first gate drivermay be provided to some pixels through first to mth gate lines GLto GL, and a gate signal generated by the second gate drivermay be provided to some pixels through first to mth gate lines GLto GLmb.

1 1 1 1 1 a ma b a b Each of the first to mth gate lines GLto GLand each of the first to mth gate lines GLto GLmb may be connected to the same pixel row. For example, the first gate line GLand the first gate line GLmay be connected to a first pixel row. The mth gate line GLma and the mth gate line GLmb may be connected to an mth pixel row.

100 1 1 1 a ma b In addition, the display devicemay include a plurality of buffers BF. The plurality of buffers BF may be connected to the first to mth gate lines GLto GLand the first to mth gate lines GLto GLmb, respectively. Each of the plurality of buffers BF may adjust an output time of the gate signal.

110 1 121 1 122 The display panelmay be divided into a first block NAa, a second block FAa, a third block NAb, and a fourth block FAb. The first block NAa, the second block FAa, the fourth block FAb, and the third block Nab may be sequentially arranged in a direction (e.g., a first direction DR) distant from the first gate driver. The third block NAb, the fourth block FAb, the second block FAa, and the first block NAa may be sequentially arranged in a direction (e.g., the opposite direction of the first direction DR) distant from the second gate driver.

121 122 According to some embodiments, a pixel located in the first block NAa and the second block FAa may receive the gate signal from the first gate driver. A pixel located in the third block NAb and the fourth block FAb may receive the gate signal from the second gate driver.

121 1 a As a distance from the first gate driverto the pixel located in the first block NAa and the second block FAa increases, resistances and parasitic capacitances of the first to mth gate lines GLto GLma may increase. Accordingly, a time for which a voltage of the gate signal is changed to a desired voltage level may be increased by a resistor-capacitor (RC) delay, and slew rates of the first block NAa and the second block FAa may be different from each other.

122 1 b Similarly, as a distance from the second gate driverto the pixel located in the third block NAb and the fourth block FAb increases, resistances and parasitic capacitances of the first to mth gate lines GLto GLmb may increase. Accordingly, a time for which a voltage of the gate signal is changed to a desired voltage level may be increased by an RC delay, and slew rates of the third block NAb and the fourth block FAb may be different from each other.

110 121 122 110 11 15 FIGS.to As slew rates of the first block NAa, the second block FAa, the third block NAb, and the fourth block FAb are different from one another, the image quality of the display panelmay be deteriorated. As slew rates are controlled according to distances between the first and second gate driversandand a pixel, the image quality of the display panelcan be relatively improved. This will be described in detail later with reference to.

11 FIG. 10 FIG. is a diagram illustrating aspects of the connection relationship between the first and second gate drivers and the pixels shown inaccording to some embodiments.

11 FIG. 121 122 Referring to, a separate gate line may be connected according to distances from the first and second gate driversand.

1 1 a a Pixels located in the first block NAa may be connected to first sub-gate lines NLto NLma, and pixels located in the second block FAa may be connected to second sub-gate lines FLto FLma.

1 1 121 1 121 1 a For example, with respect to the first direction DR, pixels from a pixel FPclosest to the first gate driveramong the pixels located in the first block NAa to a pixel LPmost distant from the first gate driveramong the pixels located in the first block NAa may be connected to the first sub-gate lines NLto NLma.

1 2 121 2 121 1 1 a a In addition, with respect to the first direction DR, pixels from a pixel FPclosest to the first gate driveramong the pixels located in the second block FAa to a pixel LPmost distant from the first gate driveramong the pixels located in the second block FAa may be connected to the second sub-gate lines FLto FLma. Because of a line design structure, the second sub-gate lines FLto FLma overlap with the first block NAa, but may not be connected to the pixels located in the first block NAa.

1 121 1 1 121 2 a a The first sub-gate lines NLto NLma may receive the gate signal from the first gate driverthrough a first buffer BFand a slew rate controller SL. The second sub-gate lines FLto FLma may receive the gate signal from the first gate driverthrough a second buffer BF.

1 a The slew rate controller SL may control slew rates of the first sub-gate lines NLto NLma such that a slew rate of the first block NAa is equal to a slew rate of the second block FAa. The slew rate controller SL may compensate for a resistor-capacitor (RC) delay of the first block NAa, which is smaller than an RC delay of the second block FAa. The slew rate controller SL may decrease the slew rate of the first block NAa. Accordingly, the slew rates of the first block NAa and the second block FAa may become constant.

1 1 b b Similarly, pixels located in the third block NAb may be connected to first sub-gate lines NLto NLmb, and pixels located in the fourth block FAb may be connected to second sub-gate lines FLto FLmb.

1 122 1 1 122 2 b b The first sub-gate lines NLto NLmb may receive the gate signal from the second gate driverthrough a first buffer BFand a slew rate controller SL. The second sub-gate lines FLto FLmb may receive the gate signal from the second driverthrough a second buffer BF.

1 b The slew rate controller SL may control slew rates of the first sub-gate lines NLto NLmb such that a slew rate of the third block NAb is equal to a slew rate of the fourth block FAb. The slew rate controller SL may compensate for an RC delay of the third block NAb, which is smaller than an RC delay of the fourth block FAb. The slew rate controller SL may decrease the slew rate of the third block NAb. Accordingly, the slew rates of the third block NAb and the fourth block FAb may become constant.

1 1 1 1 1 1 1 1 a b a b a b a b The first sub-gate lines NLto NLma and NLto NLmb and the second sub-gate lines FLto FLma and FLto FLmb may be located in the same metal layer. Also, the first sub-gate lines NLto NLma and NLto NLmb and the second sub-gate lines FLto FLma and FLto FLmb may be located on different metal layers.

1 2 1 2 According to some embodiments, ranges of the first block NAa and the second block FAa may be determined such that no luminance different occurs between the pixel LPof the first block NAa and the pixel FPof the second block FAa. For example, the pixel LPof the first block NAa and the pixel FPof the second block FAa may have the same RC delay.

3 4 3 4 3 4 Similarly, ranges of the third block NAb and the fourth block FAb may be determined such that no luminance different occurs between a pixel LPof the third block NAb and a pixel FPof the fourth block FAb. For example, the pixel LPof the third block NAb and the pixel FPof the fourth block FAb may have the same RC delay. That is, slew rates of the gate signal provided to the pixel LPof the third block NAb and the pixel FPof the fourth block FAb may be the same.

1 1 2 4 Dummy gate lines DMLto DMLm may be located in the second block FAa and the fourth block FAb. For example, the dummy gate lines DMLto DMLm may be located in the pixel LPof the second block FAa and a pixel LPof the fourth block FAb.

1 1 121 1 1 122 a b At points at which the second sub-gate lines FLto FLma are connected to the pixels of the second block FAa for the first time, the dummy gate lines DMLto DMLm may extend in a direction distant from the first gate driver. Alternatively, at points at which the second sub-gate lines FLto FLmb are connected to the pixels of the fourth block FAb for the first time, the dummy gate lines DMLto DMLm may extend in a direction distant from the second gate driver.

1 1 1 a b According to some embodiments, the dummy gate lines DMLto DMLm may be arranged with a margin at the points at which the second sub-gate lines FLto FLma and FLto FLmb are connected to the pixels of the second block FAa and the fourth block FAb for the first time.

1 1 1 1 1 a b a b As the dummy gate lines DMLto DMLm are located in the second block FAa and the fourth block FAb, the pixels of the second block FAa and the fourth block FAb may have the same pattern shape as the pixels located in the first block NAa and the third block NAb, which are connected to the first sub-gate lines NLto NLma and NLto NLmb and have the second sub-gate lines FLto FLma and FLto FLmb located therein.

1 1 1 1 a b The dummy gate lines DMLto DMLm and the second sub-gate lines FLto FLma and FLto FLmb may be located in the same metal layer. According to some embodiments, both ends of the dummy gate lines DMLto DMLm may be floated, be connected to a ground node, or be connected to an arbitrary bias.

12 FIG. 10 FIG. is a diagram illustrating aspects of the connection relationship between the first and second gate drivers and the pixels shown inaccording to some embodiments.

12 FIG. 12 FIG. 11 FIG. 110 121 122 110 121 122 Referring to, a separate gate line may be connected to pixels of the display panelaccording to distances from the first and second gate driversand. A connection relationship of the pixels of the display paneland the first and second gate driversand, shown in, may be similar to the connection relationship shown in. Therefore, some overlapping descriptions may be omitted.

1 121 1 1 121 2 a a First sub-gate lines NLto NLma may receive the gate signal from the first gate driverthrough a first buffer BF. Second sub-gate lines FLto FLma may receive the gate signal from the first gate driverthrough a second buffer BF.

5 12 FIGS.and 1 2 1 1 1 1 a a a Referring to, a number of inverters included in the first buffer BFmay be smaller than a number of inverters included in the second buffer BF. The first buffer BFmay control a slew rate of the first sub-gate lines NLto NLma such that the slew rate of the first sub-gate lines NLto NLma is equal to a slew rate of the second sub-gate lines FLto FLma.

13 FIG. 10 FIG. is a diagram illustrating aspects of the connection relationship between the first and second gate drivers and the pixels shown inaccording to some embodiments.

13 FIG. 13 FIG. 11 FIG. 110 121 122 110 121 122 Referring to, a separate gate line may be connected to pixels of the display panelaccording to distances from the first and second gate driversand. A connection relationship of the pixels of the display paneland the first and second gate driversand, shown in, may be similar to the connection relationship shown in. Therefore, some overlapping descriptions may be omitted.

1 121 1 1 121 2 a a First sub-gate lines NLto NLma may receive the gate signal from the first gate driverthrough a first buffer BFand a slew rate controller SL. Second sub-gate lines FLto FLma may receive the gate signal from the first gate driverthrough a second buffer BF.

11 13 FIGS.and 4 FIG. 8 FIG. 1 1 a a Referring to, the arrangement form of the second sub-gate lines FLto FLma shown inand an arrangement form of the second sub-gate lines FLto FLma shown inmay be different from each other.

11 FIG. 11 FIG. 1 1 2 2 a a In, each of the points at which the second sub-gate lines FLto FLma are connected to the pixels of the second block FAa for the first time may be a middle point of the second block FAa. That is, in, a scan start point of the second block FAa may be a middle point of the second block FAa. Through the second sub-gate lines FLto FLma, pixels may be scanned up to a pixel FPand a pixel LP, starting with the middle point of the second block FAa.

13 FIG. 13 FIG. 1 2 121 1 2 1 2 2 a a In, each of points at which the second sub-gate lines FLto FLma are connected to the pixels of the second block FAa for the first time may be a pixel FPclosest to the first gate driveramong the pixels located in the second block FAa with respect to the first direction DR. That is, in, a scan start point of the second block FAa may be the pixel FP. Through the second sub-gate lines FLto FLma, pixels may be scanned up to a pixel LP, starting with a pixel FP.

1 2 1 2 According to some embodiments, numbers of inverters included in the first buffer BFand the second buffer BFmay be adjusted. A number of inverters included in the first buffer BFmay be adjusted to be smaller than a number of inverters included in the second buffer BF, thereby decreasing the size of the slew rate controller SL or omitting the slew rate controller SL.

14 FIG. 13 FIG. is an enlarged view of the second block FAa and the fourth block FAb shown in.

14 FIG. 2 2 4 4 1 1 1 a b Referring to, a connection relationship of pixels FP, LP, LP, and FP, second sub-gate lines FLand FL, and a dummy gate line DML, which are included in the second block FAa and the fourth block FAb, is illustrated.

2 2 4 4 11 12 13 Each of the pixels FP, LP, LP, and FPmay include three sub-pixels SP, SP, and SP.

11 2 1 13 2 11 2 a A scan start point of the second block FAa may be a first sub-pixel SPof the pixel FP. Through the second sub-gate line FL, pixels may be scanned up to a third sub-pixel SPof the pixel LP, starting with the first sub-pixel SPof the pixel FP.

11 4 1 13 4 11 4 b Similarly, a scan start point of the fourth block FAb may be a first sub-pixel SPof the pixel FP. Through the second sub-gate line FL, pixels may be scanned up to a third sub-pixel SPof the pixel LP, starting with the first sub-pixel SPof the pixel FP.

11 4 1 1 1 121 11 4 1 1 1 122 a b In the first sub-pixel SPof the pixel FPto which the second sub-gate line FLis connected among the pixels of the second block FAa for the first time, the dummy gate line DMLmay extend in the direction (e.g., the first direction DR) distant from the first gate driver. Alternatively, in the first sub-pixel SPof the pixel FPto which the second sub-gate line FLis connected among the pixels of the fourth block FAb for the first time, the dummy gate line DMLmay extend in a direction (e.g., the opposite direction of the first direction DR) distant from the second gate driver.

1 1 1 12 11 2 1 12 11 4 a 14 FIG. According to some embodiments, the dummy gate line DMLmay be arranged with a margin at points at which the second sub-gate line FLis connected to the pixels of the second block FAa for the first time. Referring to, the dummy gate line DMLmay extend from a second sub-pixel SPhaving a margin in the first sub-pixel SPof the pixel FP. Similarly, the dummy gate line DMLmay extend from a second sub-pixel SPhaving a margin in the first sub-pixel SPof the pixel FP.

15 FIG. 10 FIG. is a diagram illustrating aspects of the connection relationship between the first and second gate drivers and the pixels shown inaccording to some embodiments.

15 FIG. 15 FIG. 11 FIG. 110 121 122 110 121 122 Referring to, a separate gate line may be connected to pixels of the display panelaccording to distances from the first and second gate driversand. A connection relationship of the pixels of the display paneland the first and second gate driversand, shown in, may be similar to the connection relationship shown in. Therefore, some overlapping descriptions may be omitted.

1 121 1 1 121 2 a a First sub-gate lines NLto NLma may receive the gate signal from the first gate driverthrough a first buffer BFand a slew rate controller SL. Second sub-gate lines FLto FLma may receive the gate signal from the first gate driverthrough a second buffer BF.

11 15 FIGS.and 4 FIG. 10 FIG. 1 1 a a Referring to, the arrangement form of the second sub-gate lines FLto FLma shown inand an arrangement form of the second sub-gate lines FLto FLma shown inmay be different from each other.

15 FIG. 15 FIG. 1 2 121 2 1 2 2 a a In, each of points at which the second sub-gate lines FLto FLma are connected to the pixels of the second block FAa for the first time may be a pixel LPmost distant from the first gate driveramong the pixels located in the second block FAa with respect to the first direction. That is, in, a scan start point of the second block FAa may be the pixel LP. Through the second sub-gate lines FLto FLma, pixels may be scanned up to a pixel FP, starting with the pixel LP.

15 FIG. 10 FIG. 1 4 122 1 4 1 4 4 b b Similarly, in, each of points at which the second sub-gate lines FLto FLmb are connected to the pixels of the second block FAa for the first time may be a pixel LPmost distant from the second gate driveramong the pixels located in the fourth block FAb with respect to the opposite direction of the first direction DR. That is, in, a scan start point of the fourth block FAb may be the pixel LP. Through the second sub-gate lines FLto FLmb, pixels may be scanned up to a pixel FP, starting with the pixel LP.

11 13 FIGS.and 15 FIG. Unlike the embodiments shown in, the embodiments shown inmay not include the dummy gate line.

1 2 1 2 According to some embodiments, numbers of inverters included in the first buffer BFand the second buffer BFmay be adjusted. A number of inverters included in the first buffer BFmay be adjusted to be smaller than a number of inverters included in the second buffer BF, thereby decreasing the size of the slew rate controller SL or omitting the slew rate controller SL.

16 FIG. is a block diagram illustrating aspects of a display system according to some embodiments.

16 FIG. 1000 1100 1210 1220 Referring to, a display systemmay include a processorand one or more display devicesand.

1100 1100 1100 1000 1000 The processormay perform various tasks and various calculations. In embodiments, the processormay include an Application Processor (AP), a Graphics Processing Unit (GPU), a microprocessor, a Central Processing Unit (CPU), and the like. The processormay be connected to other components of the display systemthrough a bus system to control the components of the display system.

16 FIG. 1000 1210 1220 1100 1210 1 1220 2 In, it is illustrated that the display systemincludes first and second display devicesand. The processormay be connected to the first display devicethrough a first channel CH, and be connected to the second display devicethrough a second channel CH.

1 1100 1 1 1210 1210 1 1 1210 100 1 1 1 FIG. 1 FIG. Through the first channel CH, the processormay transmit first image data IMGand a first control signal CTRLto the first display device. The first display devicemay display an image, based on the first image data IMGand the first control signal CTRL. The first display devicemay be configured identically to the display devicedescribed with reference to. The first image data IMGand the first control signal CTRLmay be provided as the input image data IMG and the control signal CTRL, which are shown in, respectively.

2 1100 2 2 1220 1220 2 2 1220 100 2 2 1 FIG. 1 FIG. Through the second channel CH, the processormay transmit second image data IMGand a second control signal CTRLto the second display device. The second display devicemay display an image, based on the second image data IMGand the second control signal CTRL. The second display devicemay be configured identically to the display devicedescribed with reference to. The second image data IMGand the second control signal CTRLmay be provided as the input image data IMG and the control signal CTRL, which are shown in, respectively.

1000 1000 The display systemmay include a computing system for providing an image display function, such as a portable computer, a mobile phone, a smartphone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, or an ultra mobile computer (UMPC). Also, the display systemmay include at least one of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, or an augmented reality (AR) device.

17 FIG. 16 FIG. is a perspective view illustrating an application example of the display system shown in.

17 FIG. 16 FIG. 1000 2000 2000 Referring to, the display systemshown inmay be applied to a head mounted display device. The head mounted display devicemay be a wearable electronic device which can be worn on a head of a user.

2000 2100 2200 2100 2200 2100 2000 2100 The head mounted display devicemay include a head mounting bandand a display device accommodating case. The head mounting bandmay be connected to the display device accommodating case. The head mounting bandmay include a horizontal band and/or a vertical band, used to fix the head mounted display deviceto the head of the user. The horizontal band may be configured to surround a side portion of the head of the user, and the vertical band may be configured to surround an upper portion of the head of the user. However, embodiments are not limited thereto. For example, the head mounting bandmay be implemented in the form of a glasses frame, a helmet or the like.

2200 1210 1220 2200 1100 16 FIG. 16 FIG. The display device accommodating casemay accommodate the first and second display devicesandshown in. The display device accommodating casemay further accommodate the processorshown in.

18 FIG. 17 FIG. is a view illustrating a head mounted display device shown in, which is worn by a user.

18 FIG. 1 1210 2 1220 2000 2000 Referring to, a first display panel DPof the first display deviceand a second display panel DPof the second display devicemay be located in the head mounted display device. The head mounted display devicemay further include one or more lenses LLNS and RLNS.

2200 1 2200 2 In the display device accommodating case, a right-eye lens RLNS may be located between the first display panel DPand a right eye of the user. In the display device accommodating case, a left-eye lens LLNS may be located between the second display panel DPand a left eye of the user.

1 1 1 An image output from the first display panel DPmay be viewed by the right eye of the user through the right-eye lens RLNS. The right-eye lens RLNS may refract light emitted from the first display panel DPto face the right eye of the user. The right-eye lens RLNS may perform an optical function for adjusting a viewing distance between the first display panel DPand the right eye of the user.

2 2 2 An image output from the second display panel DPmay be viewed by the left eye of the user through the left-eye lens LLNS. The left-eye lens LLNS may refract light emitted from the second display panel DPto face the left eye of the user. The left-eye lens LLNS may perform an optical function for adjusting a viewing distance between the second display panel DPand the left eye of the user.

According to some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped section. According to some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-areas having different optical characteristics. Each display panel may output images respectively corresponding to the sub-areas of the multi-channel lens, and the output images may be viewed by the user while respectively passing through corresponding sub-areas.

In the display device and the electronic device including the display device according to some embodiments of the present disclosure, a gate line may be divided according to a distance between a gate driver and a pixel, so that a gate line delay can be relatively reduced, and display quality can be relatively improved.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the following claims, and their equivalents.