Switching power supply, controller therefor and improvements thereof

This application claims priority of U.S. Ser. No. 63/459,453, filed Apr. 14, 2023, and U.S. Ser. No. 63/528,621, filed Jul. 24, 2023. The entire contents of the aforementioned applications are hereby incorporated by reference.

The present invention relates to the field of switching power supplies.

An off-line power supply receives power from an alternating-current (AC) source and provides a voltage-regulated, direct-current (DC) output that can be used to power a load. An exemplary off-line power supply includes a power factor correction (PFC) stage and a DC-to-DC converter stage. The PFC stage receives the AC input signal, performs rectification and maintains current drawn from the AC source substantially in phase with the AC voltage so that the power supply appears as a resistive load to the AC source. The DC-to-DC converter stage receives the rectified output of the PFC stage and generates the voltage-regulated, DC output which can be used to power the load. The rectified output of the PFC stage is typically at higher voltage and is more loosely regulated than the output of the DC-to-DC stage.

It is desired to provide an improved switching power supply.

The present invention is directed toward a switching power supply and improvements thereof. In accordance with an embodiment, a switching power supply comprises a first power supply stage configured to receive an AC input voltage and to generate a DC output voltage. The DC output voltage of the first power supply stage is set to a first target level during a first load condition and, otherwise, the output voltage is set to a second target level, the second target level being higher than the first target level. A level of power provided to a second power supply stage by the first power supply stage may be monitored to determine whether the switching power supply is operating in accordance with the first load condition or the second load condition. Adjusting the output voltage of the first power supply stage tends to maintain a switching frequency of the second power supply stage at or near a resonant frequency of the second power supply stage.

In accordance with another embodiment, a controller for switching power supply is provided, The controller comprises a power factor correction controller configured to control a power factor correction circuit arrangement to generate a regulated DC output voltage for provision to a resonant switching converter. The resonant switching converter has a resonant switching frequency. A level of the regulated DC output voltage is adjusted according to a level of power provided to the switching power converter in order to maintain a switching frequency of the resonant switching converter at or near the resonant frequency. A detector circuit arrangement is coupled to the power factor correction controller and configured to detect a level of power drawn by the switching power converter in order to adjust the level of the regulated DC output.

These and other embodiments are described herein.

The present invention is directed towards an improved switching power supply. In accordance with an embodiment, a switching power supply includes at least a first power supply stage, for example, a power factor correction (PFC) stage. The switching power supply may include a second power supply stage, for example, a DC-to-DC converter stage. The first power supply stage is configured to receive an AC voltage as input and to generate a DC output voltage. The second power supply stage receives the DC output voltage of the first power supply stage and generates a further DC output voltage. The DC output voltage of the first power supply stage is set to a first target level during a first load condition and, otherwise the output voltage is set to a second target level. The second target level is higher than the first target level.

The first and second target levels for the DC output voltage of the first power supply stage are dependent upon a level of power drawn by the switching power supply. For example, an error signal is representative of a difference between a current target level for the output voltage of first power supply stage and a monitored level of the output voltage of the first power supply stage. This error signal can be monitored to determine whether the switching power supply is operating in accordance with the first load condition or the second load condition.

The second power supply stage comprises a resonant circuit having a resonant frequency. The first target level causes switching in the second power supply stage to occur at or near the resonant frequency when the level of power reaches a first expected level during the first load condition. The second target level causes switching in the second power supply stage to occur at or near the resonant frequency when the level of power reaches a second expected level during the second load condition. For example, a load coupled to the switching power supply may draw approximately 1000 watts under certain operating conditions (e.g., the first load condition) and may also draw approximately 2000 watts under other operating conditions (e.g., the second load condition). When the load is drawing approximately 1000 watts, the DC output voltage of the first power supply stage is set to a first target level, e.g., 380 volts. To maximize efficiency, the second power supply stage can be configured such that its resonant frequency corresponds to the switching frequency required to regulate its output voltage when the DC output voltage of the first power supply stage is set to 380 volts and the load is drawing 1000 watts. For example, the output voltage of the second power supply stage may be regulated at 12.0 volts DC. However, if the load changes such that it begins drawing 2000 watts, the switching frequency of the second power supply stage will need to change in order to increase the power provided to load while maintaining its output voltage at its regulated level (e.g., at 12.0 volts DC). As a result of this change in switching frequency, efficiency will be reduced. To avoid this, the DC output voltage of the first power supply stage is adjusted (e.g., from 380 volts to 400 volts) when the load changes from 1000 watts to 2000 watts. As a result, the switching frequency can be maintained at or near the resonant frequency which tends to result in improved efficiency.

As described above, the DC output voltage of the first power supply stage has two levels, the first target level (e.g., 380 volts) and the second target level (e.g., 400 volts). In this case, the load power is compared to a threshold to determine which of the two levels should be selected. This two level solution is most effective when the load power also tends to mostly have two levels (e.g., 1000 watts and 2000 watts). In accordance with a further embodiment, the DC output voltage of the first power supply stage may have more than two levels. In this case, the load power may be compared to multiple thresholds in order to determine which target level for the DC output voltage should be selected. In another embodiment, the target level for the DC output voltage may be adjusted over a continuous range of target levels based on the detected load power. In this case, rather than employ one or more thresholds, the target level for the DC output voltage may be continuously adjusted based on monitored changes in the load power thereby increasing efficiency when load power consumption is variable.

1 FIG. 1 FIG. 100 102 102 102 100 102 AC DC illustrates a block schematic diagram of a two-stage, off-line power supplyin accordance with an embodiment of the present invention. As shown in, a first power supply stagehas an input coupled to alternating-current (AC) source V. The first power supply stagecan be a power factor correction (PFC) stage. The PFC stageperforms rectification on the AC input signal and maintains current drawn from the AC source substantially in phase with the AC voltage so that the power supplyappears as a resistive load to the AC source. The PFC stagegenerates a loosely regulated output voltage, V.

DC DC O DC O DC O 102 104 104 104 104 102 104 The output voltage Vof the PFC stagecan be provided as input to a second power supply stage. The second power supply stagecan be a DC-to-DC converter stage. Using the input V, the DC-to-DC converter stagegenerates a voltage-regulated, DC output, V, which can be used to power a load. The level of Vis preferably at a higher voltage and can be more loosely regulated than the output Vof the DC-to-DC converter stage. A target level of the output, V, of the PFC stagemay be, for example, approximately 380 volts DC, while the voltage-regulated output Vof the DC-to-DC converter stagemay be, for example, approximately 12.0 volts DC.

2 FIG. 102 110 110 AC AC 1 2 2 O 1 O illustrates a schematic circuit diagram of a power factor correction (PFC) stagein accordance with an embodiment of the present invention. An alternating-current (AC) input source Vis coupled across input terminals of a bridge rectifier. A rectified input voltage signal Vrect is formed at a first output terminal of the rectifierand is coupled to a first terminal of a main PFC inductor Li and to a first terminal of a resistor R. A second terminal of the inductor Li is coupled to a first terminal of a transistor switch Mand to a first terminal of a transistor switch M. A second terminal of the switch Mis coupled to a first terminal of an output capacitor C. A second terminal of the switch Mand a second terminal of the capacitor Care coupled to a ground node.

AC AC 112 112 110 112 102 112 A second terminal of the resistor Ris coupled to a voltage sensing input of a PFC controller. An input voltage sensing signal IAC, which is representative of the instantaneous rectified input voltage Vrect, flows through the resistor Rand is received by the controller. A second output terminal of the bridge rectifieris coupled to a current sensing input of the controllerand to a first terminal of a resistor Rsense. A second terminal of the resistor Rsense is coupled to the ground node. A current sensing signal Isense, which is representative of the instantaneous current input to the power factor correction stage, is formed across the resistor Rsense and is received by the controller.

A DC B B A B FB A B FB DC A resistor Rhas a first terminal coupled to the output voltage Vand a second terminal coupled to a first terminal of resistor R. A second terminal of the resistor Rmay be coupled a ground node. The resistors Rand Rform a voltage divider. An output voltage sensing signal Vis formed at the node between the resistors Rand R. The signal Vis representative of the output voltage V.

112 112 1 2 DC AC FB 1 2 The PFC controllergenerates a signal PFC OUT which controls the opening and closing of the switches Mand Mso as to regulate the intermediate output voltage Vwhile maintaining the input current in phase with the input voltage V. To accomplish this, the controlleruses the signal V, as well as the input voltage sensing signal IAC and the input current sensing signal Isense. The switches Mand Mare generally operated such that when one is opened, the other is closed.

3 FIG. 3 FIG. 112 112 114 FB 1 2 DC REF1 REF2 1 1 EAO DC EAO illustrates a block schematic diagram of the PFC controllerin more detail in accordance with an embodiment of the present invention. Within the controller, the signal Vis coupled to a first input terminal of a transconductance error amplifier GM. A second input of the error amplifier GMis coupled to a reference voltage that is representative of a desired level for the output voltage V. This reference voltage may be a fixed value VOr V, depending upon the output level of a comparator CMP. An output of the error amplifier GMforms a signal V, which is an error signal that is representative of a difference between the actual level of the output voltage Vand a desired level for the output voltage. As shown in, the error signal Vis formed across a compensation circuit.

REF1 DC REF2 DC DC REF1 REF2 1 In an embodiment, the level of the reference voltage Vcorresponds to a target level of approximately 380 volts DC for the PFC output V, while the level of the reference voltage Vcorresponds to a target level of approximately 400 volts DC for the PFC output V. It will be apparent that different levels for the PFC output Vcan be selected, for example, by changing the values of the reference voltage levels Vand Vapplied to the error amplifier GM.

1 EAO EAO 3 1 EAO 3 1 3 102 In an embodiment, the comparator CMPdetermines whether the PFC circuitis operating under a first load condition or a second load conditions (i.e. loading conditions other than the first load condition) according to the level of the error signal V. For example, when the level of the error signal Vis less than a voltage reference VREF, this indicates the first load condition; in this case, the output of the comparator CMPmay be a logic low voltage. If the level of the error signal Vexceeds VREF, this indicates the second load condition; in this case, the output of the comparator CMPmay be a logic high voltage. In an embodiment, the voltage reference VREFmay be set to 1.0 volts.

1 REF1 REF2 1 DC 102 The output of the comparator CMPdetermines whether the reference voltage Vor the reference voltage Vis applied to the error amplifier GM. Thus, the level at which Vis regulated by the PFC stagecan be different depending upon the loading.

DC DC 1 1 REF1 REF2 1 EAO 3 1 Changing from a first target level for the output Vto a second target level, and vice versa, can result in a sudden change in the target level for the output V. In an embodiment, once the output of the comparator CMPis changed, the reference voltage applied to the error amplifier GMis preferably not changed again (i.e. from Vto Vand vice versa) at least until the actual output voltage approaches the new target level. This can be accomplished, for example, by avoiding changing the target level again for a predetermined time period after a change or by avoiding changing the target level again until the error signal falls below a threshold after a change. Such a delay can help to prevent unstable operation. Such a delay can be implemented, for example, by a timer circuit within the comparator CMPwhich prevents its output from changing for a predetermined time after each change or by requiring Vto fall below or rise above VREFby a hysteresis margin after each change in output of the comparator CMP.

1 EAO 1 EAO 1 As described above, the DC output voltage of the first power supply stage has two levels, the first target level (e.g., 380 volts) and the second target level (e.g., 400 volts). Alternatively, the reference voltage applied to the second input of the error amplifier GMcan have multiple levels or can be a variable value dependent upon, for example, the level of the error signal V. Employing multiple levels can be accomplished, for example, by replacing the comparator CMPwith an analog-to-digital converter that is configured to convert the level of Vto a digital value where the digital value is used to select the reference voltage level from among a plurality of reference voltage levels for coupling to the second input of the error amplifier GM.

116 116 102 EAO RMS RMS RMS AC RMS AC A gain modulation blockreceives the error signal Vas well as the signal IAC for generating a modulated error signal Imul. The gain modulation blockcan, optionally, also receive the signal V. The signal Vis representative of the level of the AC line voltage and can be used to inhibit switching in the PFC stage, by gradually pulling down the level of the signal Imul, for example, if the AC line voltage is too low for an extended period (i.e. under “brown out” conditions). The signal Vcan be generated, for example, by applying the signal IAC, which represents an instantaneous value of the input voltage V, to a filter that generates signal Vby averaging value of IAC over at least one cycle of the AC input voltage V.

116 2 1 1 2 2 2 The output of the gain modulation blockis coupled to a first input terminal of a transconductance amplifier GMand to a first terminal of a resistor Rmul. A second terminal of the resistor Rmulis coupled to receive the signal Isense. A first terminal of a resistor Rmulis coupled to a second input terminal of the amplifier GM. A second terminal of a resistor Rmulis coupled to a ground node.

2 EAO 2 EAO EAO EAO 2 2 118 120 120 122 An output of the amplifier GMis coupled to a compensation circuit. A signal Iis formed at the output of the amplifier GM. The signal Iis representative of the error signal Vas well as the input voltage and input current to the PFC stage. The signal Iis coupled to a first input of a comparator CMP. An output of a ramp generatorforms a ramp signal PFC RAMP which is coupled to a second terminal of the comparator CMP. An RTCT node of the ramp generatoris coupled to an RTCT timing networkwhich sets the frequency of the ramp signal.

EAO 1 2 2 EAO DC FB REF1 REF2 1 2 116 116 The signal Ifunctions to implement a first feedback loop which equalizes the signals IAC and ISENSE in order to maintain the input voltage Vrect in phase with the input current IAC. This first feedback loop includes the signals IAC and ISENSE, as well as the gain modulation block, resistors Rmuland Rmul, and transconductance amplifier GM. As a result, the PFC converter appears to the AC input source as a resistive (i.e. non-reactive) load. The signal Ialso functions to implement a second feedback loop which regulates the output voltage Vat its desired level. This second feedback loop includes the signals Vand V(or V) as well as the gain modulation blockand transconductance amplifiers GMand GM

2 1 2 124 102 100 102 1 2 FIGS.- 1 FIG. 3 FIG. An output of the comparator CMPis coupled to driver/logic blockwhich includes driver and logic circuit elements for forming the PFC switching signal PFC OUT. The signal PFC OUT controls the transistor switches Mand Mof the PFC stage() of the switching power supply(). It will be apparent that the PFC function and control of switching in the PFC stageas shown incan be accomplished in other ways and by employing different circuit arrangements.

4 FIG. 1 FIG. 4 FIG. 1 FIG. 106 106 104 106 102 108 108 3 4 DC 3 3 4 4 3 4 3 4 3 4 3 4 DC 3 4 illustrates a schematic diagram of a resonant switching converterin accordance with an embodiment of the present invention. The resonant switching convertermay be, for example, included in the DC-to-DC converterof. Referring to, the converterincludes a half-bridge switching inverter that includes a pair of series-connected transistor switches Mand M. A power source, such as the output Vgenerated by the PFC stage(), is coupled to a first terminal of the transistor switch M. A second terminal of the transistor switch Mis coupled to a first terminal of a transistor switch Mto form an intermediate node. The second terminal of the transistor switch Mis coupled to a ground node. Control terminals of each of the transistor switches Mand Mare coupled to a controller. The controllercontrols opening and closing of the pair of transistor switches Mand M. The switches Mand Mare generally operated such that when one is opened, the other is closed. When the switch Mis closed and the switch Mis open, the intermediate node is coupled to V. This raises a voltage, VIN, at the intermediate node. When the switch Mis open and the switch Mis closed, the intermediate node is coupled to ground. This lowers the voltage, VIN, at the intermediate node.

4 FIG. r r r r r r 1 1 1 5 1 6 5 6 5 6 5 6 3 4 108 108 Energy storage elements are coupled to the intermediate node. Particularly, as shown in, a first terminal of an inductor Lis coupled to the intermediate node. A second terminal of the inductor Lis coupled to a first terminal of a capacitor C. The energy storage elements, Land C, form a series resonant tank. The resonant tank is charged with energy by raising and lowering the voltage VIN at the intermediate node. A second terminal of the capacitor Cis coupled to a first terminal of a primary winding of a transformer T. A second terminal of the primary winding of the transformer Tis coupled to a ground node. A first terminal of a secondary winding of the transformer Tis coupled to a first terminal of a transistor switch M. A second terminal of the secondary winding of the transformer Tis coupled to a first terminal of a transistor switch M. A second terminal of the transistor switch Mand a second terminal of the transistor switch Mare coupled to a ground node. Control terminals of each of the transistor switches Mand Mare coupled to the controller. The controllercontrols opening and closing of the transistor switches Mand Msynchronously with transistor switches Mand M.

1 1 1 O 1 1 O O 110 128 130 A center tap of the secondary winding of the transformer Tis coupled to a first terminal of a capacitor C. A second terminal of the capacitor Cis coupled to a ground node. An output voltage, V, is formed across the capacitor C. A loadmay be coupled across the capacitor Cto receive the output voltage V. The output voltage V, or a voltage that is representative of the output voltage, is fed back to the controllervia a feedback path.

3 4 5 6 O O DC O 128 128 128 130 108 128 4 FIG. Adjusting the switching frequency of the transistor switches M, M, Mand Madjusts impedance of the resonant tank and, therefore, adjusts the amount of power delivered to the load. More particularly, decreasing the switching frequency tends to increase the power delivered to the load. Increasing the switching frequency tends to reduce the power delivered to the load. By monitoring the level of the output voltage Vvia a feedback path, the controllercan adjust the switching frequency to maintain the output voltage Vconstant despite changes in the power requirements of the loadand despite changes in the level of the input V. This is referred to as frequency modulation or FM modulation. In an embodiment, the output voltage Vis regulated at a level of 12.0 volts DC, however, it will be apparent that some other output voltage level can be selected. Whileshows a half-bridge switching inverter, it can be replaced with a full-bridge switching inverter or with some other DC-to-DC converter topology.

5 FIG. 5 FIG. 4 FIG. 5 FIG. 5 FIG. r r 1 DC illustrates a graph showing a relationship between switching frequency and gain for a resonant DC-to-DC converter stage in accordance with an embodiment of the present invention. The resonant frequency for the DC-to-DC converter is shown inas Fr. The value of Fr is dependent upon the values of the main resonant components of the resonant DC-to-DC converter which include the values of the inductor L, the capacitor Cand the inductance of the primary winding of the transformer T(). The gain of the converter is related to a ratio of the converter input voltage (i.e. the PFC output V) and the converter output voltage. The maximum gain as shown inis 1.0.also shows a series of gain vs. frequency curves, each of which depicts a particular load level. Maximum efficiency for the resonant DC-to-DC converter occurs when the switching frequency is at or near the resonant frequency and, more particularly, when the switching frequency is in the range of Fr to 1.2 times Fr and when the switching duty cycle is approximately 50%. It is therefore desired to maintain the operating point within the range of Fr to 1.2 times Fr and duty cycle is approximately 50%. As load power increases, current levels within the resonant converter increase as do parasitic losses due to increased current. Accordingly, the gain vs. frequency curves show that gain falls off with increasing switch frequency more dramatically as the load increases. It is therefore desirable to increase converter input voltage at higher load power levels in order to maintain maximum efficiency.

6 FIG. 6 FIG. 3 FIG. 3 6 FIGS.and 6 FIG. 3 FIG. 6 FIG. REF2 REF1 1 REF1 REF2 1 ADD ADD ADD DC REF1 DC ADD DC ADD EAO illustrates a block schematic diagram of an alternative embodiment of a controller for a power factor correction stage and detector in accordance with an embodiment of the present invention.shares many of the same components and functions as are depicted indiscussed above. Therefore, only differences betweenare discussed here. Specifically, in, the reference voltage Vis omitted while the reference voltage Vremains coupled to the second input of the transconductance amplifier GM. Rather than select between the reference voltages Vand Vas in, the output of the comparator CMPselectively activates a current source I. The current source Imay have a value of approximately 3 uA (microamps). Activating the current source Ihas the effect of increasing the target level for the PFC output V. In an embodiment, the level of the reference voltage Vcorresponds to a first target level (e.g., 380 volts DC) for the PFC output V, while activating the current source Icorresponds to a second target level (e.g. 400 volts DC) for the PFC output V. As described above in connection with, the DC output voltage of the first power supply stage has two levels, the first target level (e.g., 380 volts) and the second target level (e.g., 400 volts). Alternatively, the current source Ican be a variable value dependent upon, for example, the level of the error signal V. In this case, the target level for the DC output voltage may be adjusted over a continuous range of target levels based on the detected load power.

7 FIG. 7 FIG. 3 FIG. 3 7 FIGS.and 7 FIG. 3 FIG. 7 FIG. REF2 REF1 1 REF1 REF2 1 ADD 1 1 1 DC REF1 DC 1 DC ADD EAO illustrates a block schematic diagram of an alternative embodiment of a controller for a power factor correction stage and detector in accordance with an embodiment of the present invention.shares many of the same components and functions as are depicted indiscussed above. Therefore, only differences betweenare discussed here. Specifically, in, the reference voltage Vis omitted while the reference voltage Vremains coupled to the second input of the transconductance amplifier GM. Rather than select between the reference voltages Vand Vas in, the output of the comparator CMPselectively adds a resistance Rin series with the resistor Rmulby activating a switch SW. Activating the switch SWhas the effect of increasing the target level for the PFC output V. In an embodiment, the level of the reference voltage Vcorresponds to a first target level (e.g., 380 volts DC) for the PFC output V, while activating the switch SWcorresponds to a second target level (e.g. 400 volts DC) for the PFC output V. As described above in connection with, the DC output voltage of the first power supply stage has two levels, the first target level (e.g., 380 volts) and the second target level (e.g., 400 volts). Alternatively, the resistance Rcan have a variable value dependent upon, for example, the level of the error signal V. In this case, the target level for the DC output voltage may be adjusted over a continuous range of target levels based on the detected load power.

The foregoing detailed description of the present invention is provided for the purposes of illustration and is not intended to be exhaustive or to limit the invention to the embodiments disclosed. Accordingly, the scope of the present invention is defined by the appended claims and any amendments thereto.