Memory device, memory controller, and storage device including the same

This application is based on and claims priority under 35 USC § 119 to Korean Patent Application No. 10-2023-0171823, filed on Nov. 30, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

The present invention relates to a storage device, and more particularly, to a memory device that variably controls parity data, a memory controller, and a storage device including the same.

The performance of storage devices based on a nonvolatile memory device may be significantly affected by an input/output (I/O) occupancy time based on an internal operation of the nonvolatile memory device. The internal operation of a nonvolatile memory device may refer to an operation that is invisible to users. An example of the internal operation of a nonvolatile memory device may include an operation to correct error bits to improve data I/O reliability of storage devices.

Storage devices may perform a correction operation on error bits, based on parity data. Here, storage devices may perform a correction operation on user data by maintaining a designated format and order of parity data. However, the fact that the storage devices have to perform correction operations according to the designated format and order of the parity data may result in an increase in the I/O occupancy time for the nonvolatile memory device, which may degrade the overall performance of the storage device.

The inventive concept provides a storage device in which an I/O occupancy rate for a nonvolatile memory device is reduced by variably adjusting parity data in correcting error bits, thereby having improved performance.

The technical problems of the inventive concept are not limited to the technical problems mentioned above, and other technical problems not mentioned may be clearly understood by those skilled in the art from the description below.

According to an aspect of the inventive concept, there is provided a memory device including a memory cell array including a first memory region storing first data, a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array, and a control logic circuit configured to receive parity adjustment information from an external device and control an operation of the memory cell array. The first data includes first user data and first parity data including parity bits generated based on the first user data, and the control logic circuit adjusts a size of the first parity data based on the parity adjustment information and dumps the adjusted first parity data to the first latch.

According to another aspect of the inventive concept, there is provided a memory controller including an error correction code engine configured to generate parity data corresponding to user data received from a host and a parity controller including information indicating reliability of a plurality of memory regions included in a memory device. The parity controller adjusts a size of the parity data based on reliability information corresponding to a memory region in which the user data is stored among the plurality of memory regions, and the memory controller writes the adjusted parity data and the user data to the memory device.

According to another aspect of the inventive concept, there is provided a storage device including a memory device configured to adjust a size of first parity data based on parity adjustment information and output the first parity data having the adjusted size and a memory controller configured to control an operation of the memory device. The memory device includes a memory cell array including a plurality of memory regions, a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array, and a control logic circuit configured to receive the parity adjustment information from the memory controller and control an operation of the memory cell array. The memory controller includes a parity controller including information indicating reliability of the plurality of memory regions included in the memory device. The parity controller is configured to determine a format and size of the first parity data based on reliability information of a memory region in which user data corresponding to the first parity data is stored, and provide the parity adjustment information indicating the determined format and size of the first parity data to the memory device.

Hereinafter, embodiments are described in detail with reference to the accompanying drawings. In describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof are omitted.

1 FIG. 10 is a block diagram illustrating a storage deviceaccording to an embodiment.

10 10 10 10 The storage devicemay include storage mediums for storing data according to a request from a host. For example, the storage devicemay include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. If the storage deviceis an SSD, the storage devicemay be a device that follows a nonvolatile memory express (NVMe) standard.

10 10 10 10 10 10 10 10 If the storage deviceis an embedded memory or an external memory, the storage devicemay be a device that follows the universal flash storage (UFS) or embedded multi-media card (eMMC) standard. The host and the storage devicemay each generate packets according to an adopted standard protocol and transmit the packets. In an embodiment, the storage devicemay be an embedded memory built into the storage device. For example, the storage devicemay be an eMMC or an embedded UFS memory device. In an embodiment, the storage devicemay be an external memory that is removable from another system. For example, the storage devicemay include a UFS memory card, compact flash (CF), secure digital (SD), micro-SD, mini-SD, extreme digital (xD), or memory stick.

1 FIG. 10 100 200 Referring to, the storage devicemay include a memory controllerand a memory device.

100 150 160 100 200 200 100 200 200 200 10 100 200 The memory controllermay include an error correction code (ECC) engineand a parity controller. The memory controllermay control read, write, and erase operations for the memory deviceby providing an address ADDR, a command CMD, and a control signal CTRL to the memory device. In an embodiment, in response to a read/write request from the host HOST, the memory controllermay read data stored in the memory deviceor control the memory deviceto write data to the memory device. In an embodiment, the storage devicemay perform operations, such as wear leveling management, bad block management, and garbage collection, and for these operations, the memory controllermay provide the address ADDR, the command CMD, the control signal CTRL, and data DATA to the memory device.

100 200 150 150 The data DATA may be transmitted and received between the memory controllerand the memory device. In an embodiment, the data DATA may include user data and parity data. The parity data may be data used by the ECC engineto perform an error correction operation. The parity data may be generated by the ECC engine. The parity data may be data generated based on user data.

150 200 150 200 200 150 The ECC enginemay be configured to detect and correct errors in data read from the memory deviceusing an ECC. In addition, the ECC enginemay generate parity data related to user data to be written to the memory deviceand write the user data and parity data to the memory device. In an embodiment, the ECC enginemay include a circuit, system, or device for error correction.

160 200 230 1 230 230 1 230 160 230 1 230 230 1 230 The parity controllermay provide parity adjustment information PAI to the memory deviceduring a read operation of a first memory region_to an N-th memory region_N (N is a natural number of 2 or greater) based on reliability information on the first memory region_to the N-th memory region_N. In addition, the parity controllermay adjust the size of parity data of data to be written during a write operation of the first memory region_to the N-th memory region_N based on the reliability information for the first memory region_to the N-th memory region_N.

200 230 1 230 A memory cell array of the memory devicemay be divided into a plurality of memory regions. The memory regions may include the first memory region_to the N-th memory region_N. In this disclosure, the memory regions may refer to regions including a plurality of memory cells in the memory cell array.

230 1 230 200 The reliability of each of the memory regions_to_N included in the memory devicemay deteriorate due to various causes. For example, the criteria for determining the reliability of the memory regions may include at least one of read count information, program count information, post-erase elapsed time information, and cell temperature information related to each memory region.

100 200 230 1 230 2 100 200 230 1 230 2 In an embodiment, the reliability of each memory region may be different, and accordingly, parity adjustment information PAI provided by the memory controllerto the memory devicemay also be different. For example, the reliability of the first memory region_may be different from that of the second memory region_. Accordingly, the parity adjustment information PAI provided by the memory controllerto the memory devicemay vary depending on whether the data to be read is read from the first memory region_or the second memory region_.

100 200 100 200 200 200 100 6 6 FIGS.A toD In an embodiment, when the memory controllerreads data from the memory device, the memory controllermay provide the parity adjustment information PAI to the memory device. The memory devicemay adjust the format and size of parity data related to data to be read based on the parity adjustment information PAI. The memory devicemay provide data DATA with the format and size of the parity data adjusted to the memory controller. A detailed description thereof is provided below with reference to.

100 200 100 200 7 FIG. In an embodiment, when the memory controllerwrites data received from the host to the memory device, the format and size of the parity data related to the data to be written may be adjusted based on the reliability of the memory region in which the data to be written is stored. The memory controllermay provide the data DATA with the format and size of the parity data adjusted to the memory device. A detailed description thereof will be given below with reference to.

200 10 200 100 200 10 200 200 10 When reading data stored in the memory device, the storage deviceaccording to an embodiment may perform an error correction operation based on the parity data. The memory devicemay variably adjust the parity data based on the parity adjustment information PAI provided from the memory controller. In addition, when writing data to the memory device, the storage devicemay variably adjust the format and size of the parity data generated in response to user data and write the user data and the adjusted parity data to the memory device. By adjusting the parity data in this manner, the speed of data input/output (I/O) operation from the memory devicemay increase and the performance of the storage devicemay be improved.

2 FIG. 2 FIG. 1 FIG. 100 is a block diagram illustrating a memory controlleraccording to an embodiment.may be described with reference to, and redundant descriptions may be omitted.

2 FIG. 100 110 120 130 140 150 170 180 Referring to, the memory controllermay include a processor, a flash translation layer (FTL), a memory, a host interface (IF) circuit, an ECC engine, and a memory IF circuit, and these components may communicate with each other through a bus.

110 100 110 110 130 The processormay include a central processing unit (CPU) or a microprocessor and may control the overall operation of the memory controller. The processormay include one or more processor cores capable of executing an instruction set of program code configured to perform a specific operation. For example, the processormay execute command codes of firmware stored in the memory.

120 The FTLmay perform various functions, such as address mapping, wear-leveling, and garbage collection.

130 130 The memorymay be used as an operating memory, buffer memory, cache memory, etc. For example, the memorymay be implemented as dynamic random access memory (DRAM), static random access memory (SRAM), phase-change random access memory (PRAM), or flash memory.

140 100 140 140 The host IF circuitmay provide an interface between a host HOST and the memory controller. For example, the host IF circuitmay provide an interface according to universal serial bus (USB), MMC, peripheral component interconnect-express (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), small computer system interface (SCSI), serial attached SCSI (SAS), enhanced small disk interface (ESDI), and integrated drive electronics (IDE). The host IF circuitmay receive requests and data from the host HOST and output data to the host HOST.

150 200 150 200 200 200 150 200 The ECC enginemay perform error detection and correction functions on read data from the memory device. In detail, the ECC enginemay generate parity bits for write data to be provided to the memory device, and the generated parity bits may be stored in the memory devicetogether with the write data. When reading data from the memory device, the ECC enginemay correct errors in read data using the parity bits read from the memory devicetogether with the read data and outputs error-corrected read data.

160 161 160 161 230 1 230 161 230 1 161 130 The parity controllermay include reliability information. In detail, the parity controllermay include the reliability informationfor the first memory region_to the N-th memory region_N generated based on a reliability judgment criteria for the memory region. For example, the reliability informationmay include information indicating the reliability of the first memory region_. In some embodiments, the reliability informationmay be stored in the memory.

160 161 200 160 161 200 The parity controllermay generate the parity adjustment information PAI based on the reliability information. When performing an operation of reading data from the memory device, the parity controllermay generate the parity adjustment information PAI based on the reliability information. The parity adjustment information PAI may include parity data format information that determines the format of parity data related to data read from the memory deviceand parity data size information that determines the size of the parity data.

230 1 100 100 6 FIG.A In an embodiment, when the reliability information for the first memory region_is a first reference value, the parity adjustment information PAI may include parity data format information indicating that the format of the parity data is a first format. In this disclosure, the first reference value indicating the reliability information of the memory region may refer to a reference value for explaining a case in which high error correction capability is required when performing an error correction operation of the memory controller. Here, a case in which high error correction capability is required may refer to a case in which the reliability of the memory region from which data is read is low. One of the reasons of low reliability of the memory region may be that memory cells included in the memory region are deteriorated due to frequent read, write, and erase operations being performed on the memory region. Reading data from a deteriorated memory cell or writing data into a deteriorated memory cell may involve a higher error occurrence probability than in a non-deteriorated memory cell. Accordingly, the memory controllermay select a method of selecting parity data having the highest error correction capability through parity data format information indicating the first format. This is merely an example to aid understanding and is not intended to limit the inventive concept. A detailed description thereof is provided below with reference to.

230 1 200 100 100 6 FIG.B In an embodiment, when the reliability information for the first memory region_is a second reference value, the parity adjustment information PAI may include parity data format information indicating that the format of the parity data is a second format. In this disclosure, the second reference value indicating the reliability information of the memory region may refer to a reference value for explaining a case in which a faster I/O speed is required for data to be input to/output from the memory devicewhen performing an error correction operation of the memory controller. Here, a case in which a faster I/O speed is required may refer to a case in which the reliability of the memory region from which data is read is high. A case in which the reliability of the memory region is high may refer to a case in which the degree of deterioration of the memory cells included in the memory region is not high when many read, write, and erase operations are not performed on the memory region, unlike a case in which the reliability of the memory region is low. In this manner, reading data from a memory region in which the degree of deterioration is not high and writing data into such a memory region may have a relatively lower error occurrence probability than in a deteriorated memory cell. Accordingly, the memory controllermay optimize I/O performance by selecting and transmitting the most efficient parity according to the reliability of the memory region. This is merely an example to aid understanding and is not intended to limit the inventive concept. A detailed description thereof is provided below with reference to.

230 1 100 In an embodiment, when the reliability information for the first memory region_is a third reference value, the parity adjustment information PAI may include parity data format information indicating that the format of the parity data is a third format. In this disclosure, reliability information being the third reference value may refer to that when the memory controllerperforms an error correction operation, the error correction operation is performed based on new parity data that is different from existing parity data. Here, the new parity data may be generated based on user data.

100 100 During the error correction operation of the memory controller, if the error correction capability achievable through parity data configured in the first format or the second format is different from the range of error correction capability considered by the memory controller, the third format may be selected as a format of the parity data.

200 100 6 FIG.C For example, it is assumed that, in an initial state after data is written to the memory region, the reliability of the memory region is very high. In this case, only parity data having a size less than the size of parity data having the lowest error correction capability previously considered in the related art may be required. That is, when performing a read operation by selecting the first format or the second format as the format of the parity data, parity data in a form with higher error correction capability than necessary (i.e., parity data having an unnecessarily large size) has to be transmitted, and thus, the operation of the memory devicemay be inefficient in terms of I/O speed. Here, if the memory controllerselects the third format as the parity data and performs a read operation, the read operation may be performed using new parity data having a different format from and smaller size than the parity data of the first format and the second format, thereby achieving improved I/O speed. This is merely an example to aid understanding and is not intended to limit the inventive concept. A detailed description thereof is provided below with reference to.

100 100 100 100 100 200 6 FIG.D Also, for example, it is assumed that the error correction capability required for the memory controllerdepending on the reliability of a memory region falls between a case of selecting the first format and performing a read operation and a case of selecting the second format. In this situation, if the memory controllerselects the first format, parity data having a high error correction capability (i.e., parity data having an unnecessarily large size) compared to the required error correction capability, which may be inappropriate, and if the memory controllerselects the second format, there may be a high possibility that error correction may fail, which may also be inappropriate. Here, if the memory controllerselects the third format as the parity data and performs a read operation, the memory controllermay perform a read operation based on all or part of the newly generated parity data and the existing parity data together received from the memory device, and thus, a target error correction reliability may be achieved. This is merely an example to aid understanding and is not intended to limit the inventive concept. A detailed description thereof is provided below with reference to.

100 120 200 In an embodiment, the first to third reference values may be values previously input to the memory controller. Alternatively, the first to third reference values may be values determined by the FTLto achieve a certain level of error correction capability or higher in relation to error correction operations during the process of reading data from the memory device.

200 160 161 When performing a data write operation in the memory device, the parity controllermay determine the format and size of the parity data of the data to be written based on the reliability information.

230 1 100 100 7 FIG. In an embodiment, when the reliability information for the first memory region_is a first write reference value, the memory controllermay determine the format of the parity data of the data to be written as a first write format. In some embodiments, the first write reference value may be different from the first reference value in the read operation described above. In this disclosure, the first write reference value indicating the reliability information of a memory region may be a reference value for explaining a case in which the memory controllergenerates parity data corresponding to user data when reliability of a memory region to which data is written is low. The first write format may be a parity data format that has superior error correction capability to a second write format. A detailed description thereof is provided below with reference to.

230 1 100 100 200 7 FIG. In an embodiment, when the reliability information for the first memory region_is a second write reference value, the memory controllermay determine the format of the parity data of the data to be written as a second write format. In some embodiments, the second write reference value may be different from the second reference value in the read operation described above. In this disclosure, the second write reference value indicating the reliability information of a memory region may be a reference value for explaining a case in which the memory controllergenerates parity data corresponding to user data when reliability of a memory region to which data is written is high. The second write format may be a parity data format that is more efficient than the first write format in terms of I/O performance of the memory device. A detailed description thereof is provided below with reference to.

100 120 200 In an embodiment, the first write reference value and the second write reference value may be values previously input to the memory controller. Alternatively, the first write reference value and the second write reference value may be values determined by the FTLto achieve error correction capability above a certain level in consideration of the reliability of a memory region at the time the data is written in the process of writing data to the memory device.

160 160 160 130 110 160 120 The parity controllermay be implemented in hardware, software, or firmware. When the parity controlleris implemented in software or firmware, the parity controllermay be loaded into the memoryand operate under control by the processor. In some embodiments, the parity controllermay be included in the FTLbut is not limited thereto.

170 100 200 100 200 170 The memory IF circuitmay provide an interface between the memory controllerand the memory device. For example, data, commands, and addresses may be transmitted and received between the memory controllerand the memory devicethrough the memory IF circuit.

180 The busmay operate based on one of various bus protocols. The various bus protocols may include at least one of advanced microcontroller bus architecture (AMBA) protocol, USB protocol, MMC protocol, PCI protocol, PCI-E protocol, ATA protocol, Serial-ATA protocol, Parallel-ATA protocol, SCSI protocol, ESDI protocol, integrated drive electronics (ESDI) protocol, mobile industry processor interface (MIPI) protocol, and UFS protocol.

3 FIG. 3 FIG. 1 2 FIGS.and 200 is a block diagram illustrating the memory deviceaccording to an embodiment.may be described with reference to, and redundant descriptions may be omitted.

3 FIG. 200 210 220 230 240 250 260 Referring to, the memory deviceincludes a voltage generator, an address decoder, a memory cell array, a control logic circuit, a page buffer, and an I/O circuit.

210 230 210 210 210 230 The voltage generatormay generate various types of voltages to perform program, read, and erase operations on the memory cell arraybased on a voltage control signal CTRL_vol. In detail, the voltage generatormay generate a word line voltage VWL, for example, a program voltage, a read voltage, a pass voltage, an erase verification voltage, or a program verification voltage. In addition, the voltage generatormay generate a string select line voltage and a ground select line voltage based on the voltage control signal CTRL_vol. In addition, the voltage generatormay generate an erase voltage to be provided to the memory cell array.

220 1 230 The address decodermay select one of a plurality of memory blocks BLKto BLKz (z is a natural number greater than 1) of the memory cell array, select one of word lines WL of the selected memory block, and select one of a plurality of string select lines SSL.

230 230 220 250 230 1 The memory cell arraymay be connected to word lines WL, string select lines SSL, ground select lines GSL, and bit lines BL. The memory cell arraymay be connected to the address decoderthrough word lines WL, string select lines SSL, and ground select lines GSL and may be connected to the page bufferthrough bit lines BL. The memory cell arraymay include the memory blocks BLKto BLKz.

1 1 1 1 230 1 230 1 FIG. Each of the memory blocks BLKto BLKz may include a plurality of memory cells and a plurality of selection transistors. The memory cells may be connected to the word lines WL, and the selection transistors may be connected to string select lines SSL or ground select lines GSL. Each of the memory blocks BLKto BLKz may correspond to an erase unit. Each of the memory blocks BLKto BLKz may include a plurality of pages, and each of the pages may correspond to a program or read unit of data in one memory block. In an embodiment, each of the memory blocks BLKto BLKz may correspond to the first to N-th memory regions_to_N of.

240 230 240 220 250 210 The control logic circuitmay output various control signals to perform program, read, and erase operations on the memory cell arraybased on the command CMD, address ADDR, and control signal CTRL. The control logic circuitmay provide a row address X-ADDR to the address decoder, a column address Y-ADDR to the page buffer, and a voltage control signal CTRL_vol to the voltage generator.

240 241 240 100 241 241 252 250 The control logic circuitmay include a parity generator. The control logic circuitmay generate new parity data based on the parity adjustment information PAI received from the memory controller. The parity data newly generated by the parity generatormay be referred to as generated parity data GPD. The parity generatormay provide the generated parity data GPD to a second latchof the page buffer.

241 In an embodiment, when the parity adjustment information PAI includes parity data format information indicating that the format of the parity data is the third format, the parity generatormay generate parity data GPD that is different from parity data corresponding to read data.

250 251 252 200 250 240 251 252 250 250 251 252 260 240 200 100 251 250 250 230 240 The page buffermay include a first latchand the second latch. During a read operation of the memory device, the page buffermay sense a bit line BL of a selected memory cell under control by the control logic circuit. Sensed data may be dumped into the first latchand the second latchprovided inside the page buffer. The page buffermay provide data latched in the first latchand the second latchto the I/O circuitunder control by the control logic circuit. During a write operation of the memory device, write data provided from the memory controllermay be dumped into the first latchprovided inside the page buffer. The page buffermay provide data latched in the latches to the memory cell arrayunder control by the control logic circuit.

200 251 252 6 6 FIGS.A toD In an embodiment, when the memory deviceperforms a read operation, parity data may be dumped to the first latchor the second latchaccording to the parity data format information included in the parity adjustment information PAI. A detailed description thereof is given below with reference to.

260 200 260 200 260 250 The I/O circuitmay temporarily store the command CMD, address ADDR, control signal CTRL, and data DATA provided from the outside of the memory device. The I/O circuitmay temporarily store the read data of the memory deviceand output the data DATA to the outside at a designated time. In addition, the I/O circuitmay temporarily store write data provided from the outside and provide data DATA to the page bufferat a designated time.

4 FIG. 4 FIG. 4 FIG. 1 3 FIGS.to 200 100 2 200 is a block diagram illustrating a read operation of the memory deviceaccording to an embodiment. In detail,is a diagram illustrating the memory controllerthat reads second data Dfrom the memory device.may be described with reference to, and redundant descriptions may be omitted.

4 FIG. 4 FIG. 200 230 250 230 230 1 230 4 230 230 Referring to, the memory devicemay include the memory cell arrayand the page buffer. The memory cell arraymay include a first memory region_to a fourth memory region_. In, the memory cell arrayis illustrated as including four memory regions, but this is an example and the memory cell arraymay include fewer or more memory regions.

1 230 1 1 1 1 2 230 2 2 2 2 3 230 3 3 3 3 4 230 4 4 4 4 First data Dmay be stored in the first memory region_. The first data Dmay include first user data UDand first parity data PD. The second data Dmay be stored in the second memory region_. The second data Dmay include second user data UDand second parity data PD. Third data Dmay be stored in the third memory region_. The third data Dmay include third user data UDand third parity data PD. Fourth data Dmay be stored in the fourth memory region_. The fourth data Dmay include fourth user data UDand fourth parity data PD.

1 4 1 4 In an embodiment, formats and sizes of the first to fourth parity data PDto PDmay be different. The formats and sizes of the first to fourth parity data PDto PDmay be determined based on reliability information corresponding to the memory region in which each parity data is stored.

200 250 100 2 200 2 250 250 2 2 2 2 200 250 100 2 a a a In an embodiment, the memory devicemay provide read data to the page bufferduring a read operation. For example, when the memory controllerreads the second data D, the memory devicemay provide the second data Dto the page buffer. Read data RD stored in the page buffermay include second user data UDand adjusted parity data PD. The adjusted parity data PDmay have a different format and size from the second parity data PD. The memory devicemay provide the read data RD stored in the page bufferto the memory controller. In an embodiment, the adjusted parity data PDmay be generated based on the parity adjustment information PAI.

100 100 2 2 a. In an embodiment, the memory controllermay perform an error correction operation on the read data RD. In detail, the memory controllermay perform an error correction operation on the second user data UDbased on the adjusted parity data PD

5 FIG. 5 FIG. 5 FIG. 4 FIG. 200 3 230 3 is a block diagram illustrating a write operation of the memory deviceaccording to an embodiment. In detail,is a diagram illustrating writing third data Dinto the third memory region_.may be described with reference to, and redundant descriptions may be omitted.

5 FIG. 5 FIG. 200 230 250 230 230 1 230 4 230 230 Referring to, the memory devicemay include the memory cell arrayand the page buffer. The memory cell arraymay include the first memory region_to the fourth memory region_. In, the memory cell arrayis illustrated as including four memory regions, but this is an example, and the memory cell arraymay include fewer or more memory regions.

1 230 1 1 1 1 2 230 2 2 2 2 230 1 100 230 4 First data Dmay be stored in the first memory region_. The first data Dmay include first user data UDand first parity data PD. Second data Dmay be stored in the second memory region_. The second data Dmay include second user data UDand second parity data PD. The third memory region_may be a memory region into which write data WD provided from the memory controlleris written. The fourth memory region_may be in a state in which no data is stored.

100 200 3 3 3 100 3 200 3 230 3 230 3 3 In an embodiment, the memory controllermay provide the write data WD to the memory deviceduring a write operation. The write data WD may include third user data UDand third parity data PD. Here, the third parity data PDmay be data generated by the memory controllerbased on the third user data UD. The memory devicemay store write data Din the third memory region_. Data stored in the third memory region_may be referred to as third data D.

1 3 1 3 In an embodiment, formats and sizes of the first to third parity data PDto PDmay be different. The formats and sizes of the first parity data PDto third parity data PDmay be determined based on reliability information corresponding to the memory region in which each parity data is stored.

6 6 6 6 FIGS.A,B,C, andD 6 6 6 6 FIGS.A,B,C, andD 1 4 FIGS.to 200 are block diagrams illustrating a read operation of the memory deviceaccording to an embodiment.may be described with reference to, and redundant descriptions may be omitted.

1 1 1 1 1 2 3 100 2 1 3 1 3 1 1 1 2 In an embodiment, the first data Dmay include first user data UDand first parity data PD. The first parity data PDmay be divided into a first parity region P, a second parity region P, and a third parity region P. The memory controllermay perform error correction using data corresponding to each parity region, and each parity region may have different error correction capabilities. As an example, it is assumed that the error correction capability of the second parity region Pis higher than the error correction capability of the first parity region P, and the error correction capability of the third parity region Pis the highest among the first to third parity regions Pto P. Dividing the parity data PDinto three regions may be an example, and the first parity data PDmay also be divided into fewer or more parity regions. Here, each parity region may be generated through a different ECC algorithm. For example, an ECC algorithm used to generate the first parity region Pmay be different from an ECC algorithm used to generate the second parity region P.

6 FIG.A 6 FIG.A 1 230 1 230 1 100 a a is a diagram illustrating reading first data Dstored in a first memory region_. In, it is assumed that the reliability information corresponding to the first memory region_is a first reference value, and the parity adjustment information PAI received from the memory controllerincludes parity data format information indicating that a format of parity data to be read is a first format.

200 1 251 250 200 3 1 3 251 251 1 2 2 3 2 2 1 2 1 a a a a The memory devicemay dump part of the first data Dto the first latchof the page buffer. Because the format of the parity data indicated by the parity adjustment information PAI is the first format, the memory devicemay select only the third parity region Phaving the best error correction capability from the first parity data PDand dump the selected third parity region Pto the first latch. Therefore, the first latchmay store latched data LDa including first user data UDand second parity data PD, and here, the second parity data PDmay include the third parity region P. In an embodiment, the second parity data PDmay additionally include the second parity region Pand/or the first parity region P. The second parity data PDmay be referred to as adjusted first parity data PD.

200 260 260 100 100 1 2 a. The memory devicemay provide the latched data LDa as read data RDa to the I/O circuit, and the I/O circuitmay provide the read data RDa to the memory controller. The memory controllermay perform an error correction operation on the first user data UDbased on the second parity data PD

6 FIG.B 6 FIG.B 1 230 1 230 1 100 b b is a diagram illustrating reading the first data Dstored in a first memory region_. Referring to, it is assumed that the reliability information corresponding to the first memory region_is a second reference value and the parity adjustment information PAI received from the memory controllerincludes parity data format information indicating that the format of the parity data to be read is the second format.

200 1 251 100 200 2 1 2 251 251 1 2 2 2 2 1 3 2 1 6 FIG.B b b b b In an embodiment, the memory devicemay dump part of the first data Dto the first latch. Because the format of the parity data indicated by the parity adjustment information PAI is the second format, the reliability of the memory region is high, so even if parity data having low error correction capability compared to parity data having the first format is used, the memory controllermay correct the error. For example, as shown in, the memory devicemay select the second parity region Pfrom the first parity data PDand dump the selected parity region Pinto the first latch. The first latchmay store latched data LDb including first user data UDand second parity data PD, and in this case, the second parity data PDmay include the second parity region P. In an embodiment, the second parity data PDmay additionally include the first parity region Pand/or the third parity region P. The second parity data PDmay be referred to as adjusted first parity data PD.

6 FIG.B 2 2 251 1 251 2 1 100 1 251 230 1 1 251 230 1 2 251 1 2 251 230 1 b b b b b. In, the second parity region Pas the second parity data PDis shown as being dumped to the first latch, but this is an example, and the first parity region Pmay be dumped to the first latchas the second parity data PD. For example, if error correction is possible only with the first parity region Pwhen the memory controllerperforms an error correction operation, the first parity region Pmay be dumped to the first latch. In this case, the reliability of the first memory region_when the first parity region Pis dumped to the first latchmay be higher than the reliability of the first memory region_when the second parity data Pis dumped to the first latch. In this manner, whether the first parity region Por the second parity region Pis dumped to the first latchmay be determined depending on the reliability of the first memory region_

200 260 260 100 100 1 2 b. The memory devicemay provide the latched data LDb as read data RDb to the I/O circuit, and the I/O circuitmay provide the read data RDb to the memory controller. The memory controllermay perform an error correction operation on the first user data UDbased on the second parity data PD

6 FIG.C 6 FIG.C 6 FIG.C 1 230 1 230 1 100 230 1 100 1 c c c is a diagram illustrating reading the first data Dstored in a first memory region_. In, it is assumed that the reliability information corresponding to a first memory region_is a third reference value and the parity adjustment information PAI received from the memory controllerincludes parity data format information indicating that the format of parity data to be read is a third format. In addition, in, it is assumed that the reliability of the first memory region_is very high, so the error correction capability required for the memory controlleris lower than the error correction capability achieved when the error correction operation based on the first parity region Pis performed.

200 1 1 251 200 1 1 251 240 230 1 1 252 2 2 1 251 1 252 2 2 4 2 1 3 4 1 3 4 1 c c c c c c a c a a In an embodiment, because the format of the parity data is the third format according to the parity adjustment information PAI, the memory devicemay dump the first user data UDof the first data Dto the first latch. The memory devicemay not dump the first parity data PDof the first data Dto the first latch. Here, the control logic circuitmay generate parity data GPD generated based on the reliability information of the first memory region_and the first user data UDand provide the generated parity data GPD to the second latchas second parity data PD. The second parity data PDmay be generated based on the first user data UD. Data dumped in the first latchmay be referred to as first latched data LD, and data dumped in the second latchmay be referred to as second latched data LD. In addition, the second parity data PDmay be referred to as fourth parity region Pto distinguish the second parity data PDfrom the first parity region Pto the third parity region P. The fourth parity region Pmay have a different size from those of the first to third parity regions Pto P. For example, the size of the fourth parity region Pmay be less than the size of the first parity region P.

200 1 2 260 260 100 100 1 2 c c c. The memory devicemay provide the first latched data LDand the second latched data LDas read data RDc to the I/O circuit, and the I/O circuitmay provide the read data RDc to the memory controller. The memory controllermay perform an error correction operation on the first user data UDbased on the second parity data PD

6 FIG.D 6 FIG.D 6 FIG.D 1 230 1 230 1 100 100 1 2 d d is a diagram illustrating reading the first data Dstored in a first memory region_. In, it is assumed that the reliability information corresponding to a first memory region_is a third reference value and the parity adjustment information PAI received from the memory controllerincludes parity data format information indicating that the format of parity data to be read is a third format. In addition, in, it is assumed that the error correction capability considered by the memory controlleris between an error correction capability achieved when an error correction operation based on the first parity region Pis performed and an error correction capability achieved when an error correction operation based on the second parity region Pis performed.

200 1 1 251 200 1 1 251 2 240 230 1 1 252 2 251 1 252 2 2 1 4 4 2 1 4 1 3 4 1 2 d d d d d d b b d b b In an embodiment, because the format of the parity data is the third format according to the parity adjustment information PAI, the memory devicemay dump the first user data UDof the first data Dto the first latch. The memory devicemay dump part of the first parity data PDof the first data Dto the first latchas part of second parity data PD. Here, the control logic circuitmay generate parity data GPD based on the reliability information of the first memory region_and the first user data UDand may provide the generated parity data GPD to the second latchas part of the second parity data PD. Data dumped to the first latchmay be referred to as first latched data LD, and data dumped to the second latchmay be referred to as second latched data LD. In addition, the second parity data PDmay include a first parity region Pand a fourth parity region P. The fourth parity region Pof the second parity data PDmay be data generated based on first user data UD. The fourth parity region Pmay have a different size from those of the first to third parity regions Pto P. For example, the size of the fourth parity region Pmay be greater than the size of the first parity region Pand less than the size of the second parity region P.

200 251 252 260 260 100 100 1 2 100 1 2 1 100 4 2 d d b d. The memory devicemay provide data latched in the first latchand the second latchas read data RDd to the I/O circuit, and the I/O circuitmay provide the read data RDd to the memory controller. The memory controllermay perform an error correction operation on the first user data UDbased on the second parity data PD. In an embodiment, the memory controllermay first perform an error correction operation based on the first parity region Pincluded in the second parity data PD. Here, if the error correction operation based on the first parity region Pfails, the memory controllermay perform an error correction operation based on the fourth parity region Pincluded in the second parity data PD

6 6 FIGS.A toD 200 1 3 251 Although not shown in, in an embodiment, the memory devicemay dump the parity regions Pto Pinto the first latch.

7 FIG. 7 FIG. 1 3 FIGS.to 5 FIG. 200 is a block diagram illustrating a write operation for the memory deviceaccording to an embodiment.may be described with reference toand, and redundant descriptions may be omitted.

7 FIG. 100 200 is a diagram to explain how the memory controllerwrites data to the memory device.

100 100 160 The memory controllermay receive write data from the host. The write data may be divided into user data and parity data. The memory controllermay determine the format and size of parity data through the parity controlleraccording to reliability information of the memory region in which the write data is to be stored.

100 1 230 1 230 1 160 1 1 1 1 1 2 3 1 1 1 In an embodiment, it is assumed that the memory controllerstores first write data WDin the first memory region_. When the reliability information for the first memory region_is the first write reference value, the parity controllermay determine that the format of the first parity data PWD, which is the parity data of the first write data WD, is the first write format. When the format of the first parity data PWDis the first write format, the first parity data PWDmay be divided into the first parity region P, the second parity region P, and the third parity region P. Dividing the first parity data PWDinto three regions may be an example, and the first parity data PWDmay also be divided into fewer or more parity regions. However, when the format of the parity data is the first write format, the parity data PWDmay be divided into more parity regions than when the format of the parity data is the second write format.

100 2 230 1 230 1 160 2 2 2 2 1 2 2 1 2 2 1 3 2 3 2 1 3 In an embodiment, it is assumed that the memory controllerstores second write data WDin the first memory region_. When the reliability information for the first memory region_is the second write reference value, the parity controllermay determine that the format of the second parity data PWD, which is parity data of the second write data WD, is the second write format. When the format of the second parity data PWDis the second write format, the second parity data PWDmay be divided into a first parity region Pand a second parity region P. In detail, when the format of the parity data is the second write format, the parity data may be divided into fewer parity regions than when the format of the parity data is the first write format. Dividing the parity region of the second parity data PWDinto the first parity region Pand the second parity region Pmay be an example, and the parity region of the second parity data PWDmay be divided into the first parity region Pand the third parity region Por may be divided into the second parity region Pand the third parity region P. Alternatively, the second parity data PWDmay include only one parity region among the first parity region Pto the third parity region P.

2 1 2 1 2 2 200 200 1 1 200 10 In an embodiment, an empty region in the second parity data PWDmay not be filled with separate dummy data and may remain empty, when compared to the first parity data PWD. The size of the second parity data PWDmay be less than the size of the first parity data PWD. Therefore, writing the second write data WDbased on the second parity data PWDto the memory devicemay have an I/O occupancy rate in the memory devicethat is lower than that of writing the first write data WDbased on the first parity data PWDto the memory device, and thus, the performance of the storage devicemay be improved.

8 FIG. 2000 is a diagram illustrating a systemto which a storage device according to an embodiment is applied.

8 FIG. 8 FIG. 8 FIG. 2000 2000 Referring to, the systemofmay be basically a mobile system, such as a mobile phone, a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of things (IoT) device. However, the systemofis not limited to mobile systems, but may also include personal computers, laptop computers, servers, media players, or automotive devices, such as navigation devices.

8 FIG. 2000 2100 2200 2200 2300 2300 2410 2420 2430 2440 2450 2460 2470 2480 a b a b Referring to, the systemmay include a main processor, memoriesand, and storage devicesandand may additionally include an image capturing device, a user input device, a sensor, communication device, a display, a speaker, a power supplying device, and a connecting interface.

2100 2000 2100 2000 2100 The main processormay control the overall operation of the system, and in detail, the main processormay control the operations of other components forming the system. The main processormay be implemented as a general-purpose processor, a dedicated processor, or an application processor.

2100 2110 2120 2200 2200 2300 2300 2100 2130 2130 2100 a b a b The main processormay include one or more CPU coresand may further include a controllerfor controlling the memoriesandand/or the storage devicesand. According to an embodiment, the main processormay further include an accelerator, which is a dedicated circuit for high-speed data computation, such as artificial intelligence (AI) data computation. Such an acceleratormay include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU) and may also be implemented as a separate chip physically independent from other components of the main processor.

2200 2200 2000 2200 2200 2100 a b a b The memoriesandmay be used as main memory devices of the systemand may include volatile memory, such as SRAM and/or DRAM, but may also include nonvolatile memory, such as flash memory, PRAM, and/or RRAM. The memoriesandmay also be implemented in the same package as that of the main processor.

2300 2300 2200 2200 2300 2300 2310 2310 2320 2320 2310 2310 2320 2320 a b a b a b a b a b a b a b The storage devicesandmay function as nonvolatile storage devices that store data regardless of whether power is supplied and may have a relatively large storage capacity compared to the memoriesand. The storage devicesandmay include storage controllersandand nonvolatile memories (NVMs)andthat store data under control by the storage controllersand. The NVMsandmay include flash memory having a 2-dimensional (2D) structure or a 3-dimensional (3D) vertical-NAND (V-NAND) structure but may also include other types of nonvolatile memories, such as PRAM and/or RRAM.

2300 2300 2000 2100 2100 2300 2300 2000 2480 2300 2300 2300 2300 10 1 2310 2310 100 2320 2320 2200 2200 200 a b a b a b a b a b a b a b 1 FIG. 1 3 5 6 6 FIGS.,-andA toD The storage devicesandmay be included in the systemwhile being physically separated from the main processoror may be implemented in the same package as that of the main processor. In addition, the storage devicesandmay have a form, such as a solid state device (SSD) or a memory card, and may be detachably coupled to other components of the systemthrough an interface, such as the connecting interfaceto be described below. The storage devicesandmay be devices to which standard protocols, such as UFS, eMMC, or NVMe are applied, but are not limited thereto. In an embodiment, each of the storage devicesandmay be implemented using the storage deviceof FIG.. In an embodiment, each of the storage controllersandmay be implemented using the memory controllerof. In an embodiment, each of the NVMsandand each of the memoriesandmay be implemented using one of the memory devicesof.

2410 The image capturing devicemay capture still images or moving images and may be a camera, camcorder, and/or webcam.

2420 2000 The user input devicemay receive various types of data input from a user of the system, and may include a touch pad, keypad, keyboard, mouse and/or microphone.

2430 2000 2430 The sensormay detect various types of physical quantities that may be obtained from the outside of the systemand convert the detected physical quantities into electrical signals. The sensormay include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

2440 2000 2440 The communication devicemay transmit and receive signals to and from other devices outside the systemaccording to various communication protocols. The communication devicemay be implemented to include an antenna, a transceiver, and/or a modem.

2450 2460 2000 The displayand the speakermay function as output devices that output visual information and auditory information, respectively, to the user of the system.

2470 2000 2000 The power supplying devicemay appropriately convert power supplied from a battery (not shown) built into the systemand/or an external power source and supply power to each component of the system.

2480 2000 2000 2000 2480 The connecting interfacemay provide a connection between the systemand an external device that is connected to the systemand may exchange data with the system. The connecting interfacemay be implemented in various interface methods, such as ATA, SATA, external SATA (e-SATA), SCSI, SAS, PCI, and PCIe, NVMe, IEEE 1394, USB, SD card, MMC, eMMC, UFS, embedded universal flash storage (UFS), compact flash (CF) card, etc.

9 FIG. 2000 is a block diagram illustrating an example of applying a memory controller according to an embodiment to the SSD system.

9 FIG. 1 FIG. 1 FIG. 1 3 5 6 6 FIGS.,-andA toD 3000 3100 3200 3200 3100 3200 3210 3220 3230 3240 3250 3200 10 3210 100 3230 3240 3250 200 Referring to, an SSD systemmay include a hostand an SSD. The SSDmay exchange signals with the hostthrough a signal connector and may receive power through a power connector. The SSDmay include an SSD controller, an auxiliary power supply, and memory devices (e.g., flash memories),, and. Here, the SSDmay be implemented using the storage deviceof. In an embodiment, the SSD controllermay be implemented using the memory controllerof. In an embodiment, each of the memory devices,, andmay be implemented using one of the memory devicesof.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as set forth in the following claims.