Ferroelectric memory architecture with gap region

The present Application for Patent claims the benefit of U.S. Provisional Patent Application No. 63/347,847 by Servalli et al., entitled “FERROELECTRIC MEMORY ARCHITECTURE WITH GAP REGION,” filed Jun. 1, 2022, assigned to the assignee hereof, and expressly incorporated by reference herein.

The following relates to one or more systems for memory, including a ferroelectric memory architecture.

Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, a component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) a stored state in the memory device. To store information, a component may write (e.g., program, set, assign) the state in the memory device.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. FeRAM may be able to achieve densities similar to volatile memory, but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device.

In ferroelectric random access memory (FeRAM) and hybrid FeRAM architectures, a memory cell may include a capacitor that includes a ferroelectric material to store a charge, or a polarization, or both, representative of a programmable logic state. The memory cell may include a logic storage component, such as a capacitor, and a switching component (e.g., a selection component). Each memory cell may be coupled with one or more access lines, including a digit line (e.g., a bit line), a word line, a plate line, or any combination thereof. In some cases, an array of memory cells may have a relatively large capacitance between plates, for example, based on dielectric materials supporting the array or a dielectric constant of the logic storage components of the memory cells, among other factors. It may be beneficial to reduce the capacitance between plates, for example, to improve efficiency of memory operations.

In accordance with examples as disclosed herein, a memory architecture may include a gap region between memory cells to reduce a capacitance between plates coupled with the memory cells. The gap region may include a substance, which may be fluid, such as air. This substance (e.g., fluid such as air) may have a relatively low dielectric constant to reduce a capacitance between plates and may reduce (e.g., eliminate) undesirable coupling between plates during memory operations. Implementing the gap region between memory cells enables a memory device to increase speed and reduce resource consumption associated with memory operations, among other advantages.

1 3 FIGS.through 4 4 FIGS.A-L 5 FIG. Features of the disclosure are initially described in the context of systems and dies with reference to. Features of the disclosure are described in the context of processing steps of a method for forming a ferroelectric memory architecture with reference to. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to a ferroelectric memory architecture as described with reference to.

1 FIG. 100 100 105 110 115 105 110 100 110 110 110 illustrates an example of a systemthat supports a ferroelectric memory architecture in accordance with examples as disclosed herein. The systemmay include a host device, a memory device, and a plurality of channelscoupling the host devicewith the memory device. The systemmay include one or more memory devices, but aspects of the one or more memory devicesmay be described in the context of a single memory device (e.g., memory device).

100 100 110 100 100 The systemmay include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other systems. For example, the systemmay illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, or the like. The memory devicemay be a component of the systemthat is operable to store data for one or more other components of the system.

100 105 105 105 120 120 105 Portions of the systemmay be examples of the host device. The host devicemay be an example of a processor (e.g., circuitry, processing circuitry, a processing component) within a device that uses memory to execute processes (where such “other circuitry” is hereinafter also referred to in the specification and claims as a “processor”), such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other stationary or portable electronic device, among other examples. In some examples, the host devicemay refer to the hardware, firmware, software, or any combination thereof that implements the functions of an external memory controller. In some examples, the external memory controllermay be referred to as a host (e.g., host device).

110 100 110 105 110 105 110 105 110 A memory devicemay be an independent device or a component that is operable to provide physical memory addresses/space that may be used or referenced by the system. In some examples, a memory devicemay be configurable to work with one or more different types of host devices. Signaling between the host deviceand the memory devicemay be operable to support one or more of: modulation schemes to modulate the signals, various pin configurations for communicating the signals, various form factors for physical packaging of the host deviceand the memory device, clock signaling and synchronization between the host deviceand the memory device, timing conventions, or other functions.

110 105 110 105 105 105 120 The memory devicemay be operable to store data for the components of the host device. In some examples, the memory device(e.g., operating as a secondary-type device to the host device, operating as a dependent-type to the host device) may respond to and execute commands provided by the host devicethrough the external memory controller. Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

105 120 125 130 105 135 The host devicemay include one or more of an external memory controller, a processor, a basic input/output system (BIOS) component, or other components such as one or more peripheral components or one or more input/output controllers. The components of the host devicemay be coupled with one another using a bus.

125 100 105 125 125 120 125 The processormay be operable to provide functionality (e.g., control functionality) for the systemor the host device. The processormay be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, the processormay be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or an SoC, among other examples. In some examples, the external memory controllermay be implemented by or be a part of the processor.

130 100 105 130 125 100 105 130 The BIOS componentmay be a software component that includes a BIOS operated as firmware, which may initialize and run various hardware components of the systemor the host device. The BIOS componentmay also manage data flow between the processorand the various components of the systemor the host device. The BIOS componentmay include instructions (e.g., a program, software) stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

110 155 160 160 160 160 160 165 165 165 165 170 170 170 170 170 110 160 a b a b a b The memory devicemay include a device memory controllerand one or more memory dies(e.g., memory chips) to support a capacity (e.g., a desired capacity, a specified capacity) for data storage. Each memory die(e.g., memory die-, memory die-, memory die-N) may include a local memory controller(e.g., local memory controller-, local memory controller-, local memory controller-N) and a memory array(e.g., memory array-, memory array-, memory array-N). A memory arraymay be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) of memory cells, with each memory cell being operable to store one or more bits of data. A memory deviceincluding two or more memory diesmay be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

160 160 170 160 170 170 160 160 170 160 A memory diemay be an example of a two-dimensional (2D) array of memory cells or may be an example of a three-dimensional (3D) array of memory cells. In some examples, a 2D memory diemay include a single memory array. In some examples, a 3D memory diemay include two or more memory arrays, which may be stacked on top of one another or positioned next to one another (e.g., relative to a substrate). In some examples, memory arraysin a 3D memory diemay be referred to as or otherwise include different sets (e.g., decks, levels, layers, dies). A 3D memory diemay include any quantity of stacked memory arrays(e.g., two high, three high, four high, five high, six high, seven high, eight high). In some 3D memory dies, different decks may share a common access line such that some decks may share one or more of a word line, a digit line, or a plate line.

155 110 155 110 110 155 120 160 125 155 110 165 160 The device memory controllermay include components (e.g., circuitry, logic) operable to control operation of the memory device. The device memory controllermay include hardware, firmware, or instructions that enable the memory deviceto perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device. The device memory controllermay be operable to communicate with one or more of the external memory controller, the one or more memory dies, or the processor. In some examples, the device memory controllermay control operation of the memory devicedescribed herein in conjunction with the local memory controllerof the memory die.

165 160 160 165 155 110 155 165 120 165 155 165 120 125 155 165 120 120 155 165 A local memory controller(e.g., local to a memory die) may include components (e.g., circuitry, logic) operable to control operation of the memory die. In some examples, a local memory controllermay be operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller. In some examples, a memory devicemay not include a device memory controller, and a local memory controlleror the external memory controllermay perform various functions described herein. As such, a local memory controllermay be operable to communicate with the device memory controller, with other local memory controllers, or directly with the external memory controller, or the processor, or any combination thereof. Examples of components that may be included in the device memory controlleror the local memory controllersor both may include receivers for receiving signals (e.g., from the external memory controller), transmitters for transmitting signals (e.g., to the external memory controller), decoders for decoding or demodulating received signals, encoders for encoding or modulating signals to be transmitted, or various other components operable for supporting described operations of the device memory controlleror local memory controlleror both.

120 100 105 125 110 120 105 110 120 100 105 125 120 125 100 105 120 110 120 110 155 165 The external memory controllermay be operable to enable communication of information (e.g., data, commands, or both) between components of the system(e.g., between components of the host device, such as the processor, and the memory device). The external memory controllermay process (e.g., convert, translate) communications exchanged between the components of the host deviceand the memory device. In some examples, the external memory controller, or other component of the systemor the host device, or its functions described herein, may be implemented by the processor. For example, the external memory controllermay be hardware, firmware, or software, or some combination thereof implemented by the processoror other component of the systemor the host device. Although the external memory controlleris depicted as being external to the memory device, in some examples, the external memory controller, or its functions described herein, may be implemented by one or more components of a memory device(e.g., a device memory controller, a local memory controller) or vice versa.

105 110 115 115 120 110 115 105 110 115 100 115 105 110 100 The components of the host devicemay exchange information with the memory deviceusing one or more channels. The channelsmay be operable to support communications between the external memory controllerand the memory device. Each channelmay be an example of a transmission medium that carries information between the host deviceand the memory device. Each channelmay include one or more signal paths (e.g., a transmission medium, a conductor) between terminals associated with the components of the system. A signal path may be an example of a conductive path operable to carry a signal. For example, a channelmay be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host deviceand a second terminal at the memory device. A terminal may be an example of a conductive input or output point of a device of the system, and a terminal may be operable to act as part of a channel.

115 115 186 188 190 192 115 Channels(and associated signal paths and terminals) may be dedicated to communicating one or more types of information. For example, the channelsmay include one or more command and address (CA) channels, one or more clock signal (CK) channels, one or more data (DQ) channels, one or more other channels, or any combination thereof. In some examples, signaling may be communicated over the channelsusing single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

170 110 110 110 In accordance with examples as disclosed herein, memory arraysof a memory devicemay include a gap region between memory cells to reduce a capacitance between plates coupled with the memory cells. The gap region may include a substance, which may be a material or a fluid, such as air, which substance may have a relatively low dielectric constant to reduce a capacitance between plates, and which may reduce (e.g., eliminate) undesirable coupling between plates during memory operations at the memory device. Implementing the gap region between memory cells may enable the memory deviceto increase speed and reduce resource consumption associated with memory operations.

2 FIG. 1 FIG. 1 FIG. 200 200 160 200 200 205 205 205 205 170 illustrates an example of a memory diethat supports a ferroelectric memory architecture in accordance with examples as disclosed herein. The memory diemay be an example of the memory diesdescribed with reference to. In some examples, the memory diemay be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory diemay include one or more memory cellsthat may each be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cellmay be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell(e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cellsmay be arranged in an array, such as a memory arraydescribed with reference to.

205 205 240 245 240 245 240 220 245 205 240 In some examples, a memory cellmay store a state (e.g., a polarization state, a dielectric charge) representative of the programmable states in a capacitor. The memory cellmay include a logic storage component, such as capacitor, and a switching component(e.g., a cell selection component). A first node of the capacitormay be coupled with the switching componentand a second node of the capacitormay be coupled with a plate line. The switching componentmay be an example of a transistor or any other type of switch device that selectively establishes or de-establishes electronic communication between two components. In FeRAM architectures, the memory cellmay include a capacitor(e.g., a ferroelectric capacitor) that includes a ferroelectric material to store a charge (e.g., a polarization) representative of the programmable state.

200 210 215 220 205 205 210 215 205 210 215 220 The memory diemay include access lines (e.g., word lines, digit lines, plate lines) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled with a memory celland may be used to perform access operations on the memory cell. In some examples, word linesmay be referred to as row lines. In some examples, digit linesmay be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or plate lines, or their analogues, are interchangeable without loss of understanding. Memory cellsmay be positioned at intersections of the word lines, the digit lines, or the plate lines.

205 210 215 220 210 215 220 210 215 220 205 210 215 205 210 215 220 Operations such as reading and writing may be performed on memory cellsby activating access lines such as a word line, a digit line, or a plate line. By biasing a word line, a digit line, and a plate line(e.g., applying a voltage to the word line, digit line, or plate line), a single memory cellmay be accessed at their intersection. The intersection of a word lineand a digit linein a two-dimensional or in a three-dimensional configuration may be referred to as an address of a memory cell. Activating a word line, a digit line, or a plate linemay include applying a voltage to the respective line.

205 225 230 235 225 265 210 230 265 215 235 265 220 Accessing the memory cellsmay be controlled through a row decoder, a column decoder, or a plate driver, or any combination thereof. For example, a row decodermay receive a row address from the local memory controllerand activate a word linebased on the received row address. A column decodermay receive a column address from the local memory controllerand activate a digit linebased on the received column address. A plate drivermay receive a plate address from the local memory controllerand activate a plate linebased on the received plate address.

205 245 240 215 245 240 215 245 240 215 245 Selecting or deselecting the memory cellmay be accomplished by activating or deactivating, respectively, the switching component. The capacitormay be in electronic communication with the digit lineusing the switching component. For example, the capacitormay be isolated from digit linewhen the switching componentis deactivated, and the capacitormay be coupled with digit linewhen the switching componentis activated.

210 205 205 210 245 205 245 210 205 205 A word linemay be a conductive line in electronic communication with a memory cellthat is used to perform access operations on the memory cell. In some architectures, the word linemay be in electronic communication with a gate of a switching componentof a memory celland may be operable to control the switching componentof the memory cell. In some architectures, the word linemay be in electronic communication with a node of the capacitor of the memory celland the memory cellmay not include a switching component.

215 205 250 205 215 210 245 205 240 205 215 205 215 A digit linemay be a conductive line that couples the memory cellwith a sense component. In some architectures, the memory cellmay be selectively coupled with the digit lineduring portions of an access operation. For example, the word lineand the switching componentof the memory cellmay be operable to selectively couple or isolate the capacitorof the memory celland the digit line. In some architectures, the memory cellmay be in electronic communication (e.g., constant) with the digit line.

220 205 205 220 240 220 215 240 205 A plate linemay be a conductive line in electronic communication with a memory cellthat is used to perform access operations on the memory cell. The plate linemay be in electronic communication with a node (e.g., the cell bottom) of the capacitor. The plate linemay cooperate with the digit lineto bias the capacitorduring access operation of the memory cell.

250 240 205 205 250 205 250 205 215 255 205 250 260 110 200 The sense componentmay determine a state (e.g., a polarization state, a charge) stored on the capacitorof the memory celland determine a logic state of the memory cellbased on the detected state. The sense componentmay include one or more sense amplifiers to amplify the signal output of the memory cell. The sense componentmay compare the signal received from the memory cellacross the digit lineto a reference(e.g., a reference voltage, a reference line). The detected logic state of the memory cellmay be provided as an output of the sense component(e.g., to an input/output), and may indicate the detected logic state to another component of a memory device (e.g., a memory device) that includes the memory die.

265 205 225 230 235 250 265 165 225 230 235 250 265 265 120 105 200 200 200 200 105 265 210 215 220 265 200 200 1 FIG. The local memory controllermay control the operation of memory cellsthrough the various components (e.g., row decoder, column decoder, plate driver, and sense component). The local memory controllermay be an example of the local memory controllerdescribed with reference to. In some examples, one or more of the row decoder, column decoder, and plate driver, and sense componentmay be co-located with the local memory controller. The local memory controllermay be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controllerassociated with a host device, another controller associated with the memory die), translate the commands or the data (or both) into information that can be used by the memory die, perform one or more operations on the memory die, and communicate data from the memory dieto a host (e.g., a host device) based on performing the one or more operations. The local memory controllermay generate row signals and column address signals to activate the target word line, the target digit line, and the target plate line. The local memory controlleralso may generate and control various signals (e.g., voltages, currents) used during the operation of the memory die. In general, the amplitude, the shape, or the duration of an applied voltage or current discussed herein may be varied and may be different for the various operations discussed in operating the memory die.

265 205 200 265 105 265 200 205 The local memory controllermay be operable to perform one or more access operations on one or more memory cellsof the memory die. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controllerin response to various access commands (e.g., from a host device). The local memory controllermay be operable to perform other access operations not listed here or other operations related to the operating of the memory diethat are not directly related to accessing the memory cells.

200 205 205 220 200 205 200 205 In accordance with examples as disclosed herein, the memory diemay include a gap region between memory cellsto reduce a capacitance between plates coupled with the memory cells(e.g., plates coupled with the plate lines). The gap region may include a substance, which may be a material or a fluid, such as air, which substance may have a relatively low dielectric constant to reduce a capacitance between plates, and which may reduce (e.g., eliminate) undesirable coupling between plates during memory operations at the memory die. Implementing the gap region between memory cellsmay enable the memory dieto increase speed and reduce resource consumption associated with memory operations (e.g., access operations on the memory cells).

3 FIG. 2 FIG. 2 FIG. 2 FIG. 300 300 200 300 300 305 310 315 320 355 315 illustrates an example of a memory arraythat supports a ferroelectric memory architecture in accordance with examples as disclosed herein. Memory arraymay be an example of memory arrayas described with reference to. Memory arrayinclude examples of components as described with reference to. For example, the memory arraymay include a memory cell, a word line, a digit line, a plate line, and a sense componentwhich may be examples of corresponding components described with reference to. In some examples, digit linemay also be an example of a global digit line.

305 330 335 330 330 335 330 320 325 320 305 305 320 325 305 305 305 305 335 a b a b a b a A memory cellmay include a logic storage component, such as capacitor, and a switching component. The capacitormay be an example of a ferroelectric capacitor. A first node of the capacitormay be coupled with the switching componentand a second node of the capacitormay be coupled with a plate line. In some examples, a memory cell pairmay be coupled with a single plate line. That is, memory cell-and memory cell-may both be coupled with the same plate line. In such examples, the memory cell pairmay be configured to store one bit of information (e.g., data). Additionally, or alternatively, memory cell-and memory cell-may be configured to store opposite logic states or charges—e.g., if memory cell-stores a logic value ‘1’, memory cell-may store a logic value ‘0’. The switching component-may be an example of a transistor or any other type of switch device that selectively establishes or de-establishes electronic communication between two components.

305 335 330 315 335 330 315 335 330 315 335 Selecting or deselecting the memory cellmay be accomplished by activating or deactivating, respectively, the switching component. The capacitormay be in electronic communication with the digit lineusing the switching component. For example, the capacitormay be isolated from digit linewhen the switching componentis deactivated, and the capacitormay be coupled with digit linewhen the switching componentis activated.

335 310 310 325 335 305 335 305 325 305 315 305 315 a a b b a a b b. In some examples, the switching componentmay be activated by a word line. A word linemay be configured to activate a memory cell pairby activating a switching component-of memory cell-and a switching component-of memory cell-. In such examples, the memory cell pairmay be coupled with a digit line pair—e.g., memory cell-may be coupled with digit line-and memory cell-may be coupled with digit line-

355 325 305 305 335 335 310 305 330 315 305 330 315 355 315 305 315 305 355 305 305 305 355 325 305 305 325 355 305 305 325 305 a b a b a a a b b b a a b b a a b b a a b Sense componentmay be configured to sense a logic state of memory cell pairby determining a difference in a voltage of the memory cell-and the memory cell-. That is, when the switching components-and-are activated by the word line, memory cell-may transfer charge from the capacitor-to the digit line-and memory cell-may transfer charge form the capacitor-to the digit line-. In such examples, the sense componentmay receive a first charge or first voltage from digit line-associated with memory cell-and a second charge of second voltage from the digit line-associated with memory cell-. The sense componentmay then determine a logic state of the memory cell-based on a difference between the first charge or first voltage and the second charge or second voltage—e.g., if memory cell-has a greater charge than memory cell-the sense componentmay determine a logic state ‘1’ for the memory cell pairand if the memory cell-has a greater charge than memory cell-the sense component may determine a logic state ‘0’ for the memory cell pair. Because the sense componentdetermines a logic state based on both the first memory cell-and the second memory cell-, a likelihood of inaccurate sensing due to an uppermost voltage of a first logic state distribution being greater than a lowermost voltage of a second logic state voltage may be reduced. In a differential system (such as the memory cell pair), sources of interference or errors are likely to affect the signals from both memory cells the same way. In contrast, in a single-ended system (e.g., with a single memory cell), sources of interference or errors may affect the signal from the memory cell differently than they affect the reference signal, thereby causing mismatches that may cause one or more errors.

300 305 325 305 300 305 200 305 325 In accordance with examples as disclosed herein, the memory arraymay include a gap region between memory cells(or between memory cell pairs) to reduce a capacitance between plates coupled with the memory cells. The gap region may include a substance, which may be a material or a fluid, such as air, which substance may have a relatively low dielectric constant to reduce a capacitance between plates, and which may reduce (e.g., eliminate) undesirable coupling between plates during memory operations at the memory array. Implementing the gap region between memory cellsmay enable the memory dieto increase speed and reduce resource consumption associated with memory operations (e.g., access operations on the memory cells, access operations on the memory cell pair).

4 4 FIGS.A throughL 4 4 FIGS.A throughL 400 400 401 402 403 404 illustrate examples of processing stepsof a method for forming a ferroelectric memory architecture in accordance with examples as disclosed herein. The processing stepsillustrate various planar viewshorizontal cross-sectional views, and vertical cross-sectional viewsof materials on a transistor array. Various cross-sections depicted inare denoted by the corresponding line in related images on the same sheet.

4 FIG.A 400 301 402 403 402 401 403 401 401 403 400 406 404 406 405 410 404 407 407 404 408 412 408 409 408 412 404 411 413 404 404 a a a a a a a a a a a In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the vertical cross-sectional view-. In the processing step-, a stackof materials may be formed on a transistor array. The stackmay include a first dielectric material(e.g., a nitride material) and an oxide material. The transistor arraymay include one or more access lines(e.g., bit lines, digit lines) coupled with an access line decoder, a sense component, or both. Each access linemay be coupled with a source or a drain of a respective transistor of the transistor array. Each transistor may also include a gate material, which may be activated by a word linecoupled with the gate materialvia an electrode. In some examples, gate materialsof two transistors may be coupled with a common word line. In some examples, the transistor arraymay include one or more materials, such as an insulating material, a shielding material, or both, to isolate (e.g., electrically isolate) the transistors from one another or provide electrostatic shielding for the transistor array. In some examples, each transistor of the transistor arraymay be a thin film transistor (TFT).

4 FIG.B 400 301 402 403 402 401 403 401 401 403 400 406 414 406 404 414 414 414 416 400 b b b b b b b b b b b In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the vertical cross-sectional view-. In the processing step-, the stackof materials may be etched (e.g., using a wet etch process, using a dry etch process) to form a set of cavities. For example, the stackmay be etched down to a surface of TFT pillars in the transistor array. In some examples, the etch may be performed using a contact mask to form the cavitieswith a determined shape. For example, the cavitiesmay be formed with a rounded square shape. In some examples, the cavitiesmay be separated by a distance(e.g., 20 nanometers (nm)) in a first direction to allow for plate cuts (e.g., in another processing step).

4 FIG.C 400 301 402 403 402 401 403 401 401 402 400 415 417 415 414 414 417 414 415 405 417 420 414 417 420 405 405 c c c c c c c c c c c In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the horizontal cross-sectional view-. In the processing step-, a second dielectric materialmay be deposited to form sidewalls. For example, the second dielectric materialmay be deposited in the set of cavities, then etched back to reform the set of cavitiesand form the sidewallssurrounding the cavities. In some examples, the second dielectric materialand the first dielectric materialmay be a same material (e.g., a nitride material). After the sidewallsare formed, a first conductive materialmay be deposited in the set of cavitiesand on the sidewallsfor form a set of electrodes (e.g., bottom electrodes for ferroelectric memory cells). In some examples, the first conductive materialmay be deposited over the first dielectric materialand then etched back to expose the first dielectric material.

4 FIG.D 400 301 402 403 402 401 403 401 401 402 400 420 417 425 417 425 420 d d d d d d d d d d d In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the horizontal cross-sectional view-. In the processing step-, the first conductive materialmay be etched back to expose a portion of each sidewall. A second conductive materialmay be deposited on the exposed portions of the sidewalls. The second conductive materialmay be a leaker (e.g., a weak conductor) between the bottom electrode (e.g., the first conductive material) and a top electrode of a ferroelectric memory cell.

4 FIG.E 400 301 402 403 402 401 403 401 401 403 400 430 414 406 431 406 e e e e e e e e e e e In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the vertical cross-sectional view-. In the processing step-, a first sacrificial materialmay be deposited in the cavitiesto reform the stackof materials. A second sacrificial materialmay be deposited over the stackof materials.

4 FIG.F 400 301 402 403 402 401 403 401 401 402 400 430 420 414 f f f f f f f f f f f In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the horizontal cross-sectional view-. In the processing step-, the first sacrificial materialmay be etched (e.g., using a wet etch process, using a dry etch process such as a carbon dry etch) to expose a portion of the first conductive materialin the set of cavities.

4 FIG.G 400 301 402 403 402 401 403 401 401 402 400 430 431 420 414 g g g g g g g g g g g In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the horizontal cross-sectional view-. In the processing step-, the first sacrificial materialand the second sacrificial materialmay be etched, and the exposed portion of the first conductive materialin the set of cavitiesmay be removed (e.g., using a wet etch process).

4 FIG.H 400 301 402 403 402 401 403 401 401 402 400 435 414 435 435 405 405 h h h h h h h h h h h In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the horizontal cross-sectional view-. In the processing step-, a ferroelectric materialmay be deposited in the set of cavities. In some examples, the deposition of the ferroelectric materialmay be a uniform thickness (e.g., 6 nm). In some examples, the ferroelectric materialmay be deposited over the first dielectric materialand then etched back to expose the first dielectric material.

4 FIG.I 400 301 402 403 402 401 403 401 401 402 400 440 414 435 405 i i i i i i i i i i i In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the horizontal cross-sectional view-. In the processing step-, a third conductive materialmay be deposited in the set of cavitiesand over the ferroelectric materialand the first dielectric material.

4 FIG.J 400 301 402 403 402 401 403 401 401 402 400 445 445 440 440 445 440 440 441 j j j j j j j j j j j In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the horizontal cross-sectional view-. In the processing step-, a mask(or a set of masks) may be placed (e.g., deposited) over a first portion of the third conductive material, leaving a second portion of the third conductive materialexposed. After the maskis placed, the exposed second portion of the third conductive materialmay be etched to separate the first portion of the third conductive materialinto plates.

4 FIG.K 400 301 402 403 402 401 403 401 401 402 400 406 405 410 410 450 417 410 450 417 k k k k k k k k k k k In, processing step-is depicted and includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the horizontal cross-sectional view-. In the processing step-, a second mask (e.g., a print mask) may be placed over the stackof materials, and the first dielectric materialmay be etched (e.g., using a dry etch process) to expose the oxide material. The oxide materialmay be removed to form a gap regionbetween the sidewalls. In some examples, the oxide materialmay be removed using a wet etch process or a wet exhume process to create a void (e.g., the gap region) between the sidewalls.

4 FIG.L 4 FIG.L 4 FIG.L 400 301 1 402 1 403 1 402 1 401 1 403 1 401 1 401 1 402 1 405 410 410 450 417 450 441 441 k In, the processing step-is depicted with alternative views. For example,includes a planar view-, a horizontal cross-sectional view-, and a vertical cross-sectional view-of the ferroelectric memory architecture. The horizontal cross-sectional view-is taken along the line A-A of the planar view-, and the vertical cross-sectional view-is taken along the line B-B of the planar view-. Further, the planar view-is taken along the line C-C of the horizontal cross-sectional view-. As illustrated in, the first dielectric materialmay be etched (e.g., using a dry etch process) to expose the oxide material. The oxide materialmay be removed to form a gap regionbetween the sidewalls. In some examples, the substance such as the fluid (e.g., air) in the gap regionmay have a relatively low dielectric constant to reduce a capacitance between the platesand reduce (e.g., eliminate) undesirable coupling between the platesduring memory operations.

5 FIG. 500 500 shows a flowchart illustrating a methodthat supports a ferroelectric memory architecture in accordance with examples as disclosed herein. The operations of methodmay be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally, or alternatively, one or more controllers may perform aspects of the described functions using special-purpose hardware.

505 505 At, the method may include forming a stack of materials over a transistor array, the stack of materials including an oxide material and a first dielectric material. The operations ofmay be performed in accordance with examples as disclosed herein.

510 510 At, the method may include etching the stack of materials to form a set of cavities. The operations ofmay be performed in accordance with examples as disclosed herein.

515 515 At, the method may include depositing a second dielectric material to form sidewalls. The operations ofmay be performed in accordance with examples as disclosed herein.

520 520 At, the method may include depositing a first conductive material in the set of cavities and on a first respective portion of each sidewall to form a set of electrodes. The operations ofmay be performed in accordance with examples as disclosed herein.

525 525 At, the method may include depositing a second conductive material on a second respective portion of each sidewall. The operations ofmay be performed in accordance with examples as disclosed herein.

530 530 At, the method may include etching the first conductive material to expose the transistor array. The operations ofmay be performed in accordance with examples as disclosed herein.

535 535 At, the method may include depositing a ferroelectric material in the set of cavities. The operations ofmay be performed in accordance with examples as disclosed herein.

540 540 At, the method may include depositing a third conductive material in the set of cavities and over the ferroelectric material and the first dielectric material to form a set of plates. The operations ofmay be performed in accordance with examples as disclosed herein.

545 545 At, the method may include etching the first dielectric material to expose the oxide material. The operations ofmay be performed in accordance with examples as disclosed herein.

550 550 At, the method may include removing the oxide material to form respective gap regions between the sidewalls. The operations ofmay be performed in accordance with examples as disclosed herein.

500 In some examples, an apparatus (e.g., a manufacturing system) as described herein may perform a method or methods, such as the method. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof for performing the following aspects of the present disclosure:

Aspect 1: A method or apparatus including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming a stack of materials over a transistor array, the stack of materials including an oxide material and a first dielectric material; etching the stack of materials to form a set of cavities; depositing a second dielectric material to form sidewalls; depositing a first conductive material in the set of cavities and on a first respective portion of each sidewall to form a set of electrodes; depositing a second conductive material on a second respective portion of each sidewall; etching the first conductive material to expose the transistor array; depositing a ferroelectric material in the set of cavities; depositing a third conductive material in the set of cavities and over the ferroelectric material and the first dielectric material to form a set of plates; etching the first dielectric material to expose the oxide material; and removing the oxide material to form respective gap regions between the sidewalls.

Aspect 2: The method or apparatus of aspect 1 where depositing the second dielectric material, further includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing the second dielectric material in the set of cavities.

Aspect 3: The method or apparatus of aspect 2, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for etching the second dielectric material to reform the set of cavities and the sidewalls, each sidewall including the second dielectric material.

Aspect 4: The method or apparatus of any of aspects 1 through 3 where depositing the first conductive material to form the set of electrodes, further includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing the first conductive material in the set of cavities, on the sidewalls, and over the first dielectric material.

Aspect 5: The method or apparatus of aspect 4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for etching the first conductive material to expose the first dielectric material and expose the respective second portion of each sidewall, where depositing the second conductive material is based at least in part on etching the first conductive material.

Aspect 6: The method or apparatus of any of aspects 1 through 5, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing a first sacrificial material in the set of cavities to reform the stack of materials after depositing the second conductive material and etching the first sacrificial material to expose a portion of the first conductive material in the set of cavities, where etching the portion of the first conductive material to expose the transistor array is based at least in part on etching the first sacrificial material.

Aspect 7: The method or apparatus of aspect 6, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing a second sacrificial material over the stack of materials, where etching the first sacrificial material to expose the portion of the first conductive material is based at least in part on depositing the second sacrificial material and etching the first sacrificial material and the second sacrificial material to reform the set of cavities.

Aspect 8: The method or apparatus of any of aspects 1 through 7 where depositing the ferroelectric material, further includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing the ferroelectric material in the set of cavities and over the first dielectric material.

Aspect 9: The method or apparatus of aspect 8, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for etching the ferroelectric material to expose the first dielectric material.

Aspect 10: The method or apparatus of any of aspects 1 through 9 where forming the set of plates, further includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing a mask over the stack of materials after depositing the third conductive material and etching the third conductive material to form the set of plates based at least in part on depositing the mask.

Aspect 11: The method or apparatus of any of aspects 1 through 10 where the oxide material is removed using a wet exhume process.

Aspect 12: The method or apparatus of any of aspects 1 through 11 where each gap region includes a fluid. In some examples, the gap region may alternatively include another substances, such as a material. In some examples, the material may be a non-fluid (e.g., may be a solid) and may be a material having a relatively lower dielectric constant compared to at least some if not all of the other materials in the apparatus.

Aspect 13: The method or apparatus of any of aspects 1 through 12 where the first dielectric material forms a respective cap over each gap region.

It should be noted that the methods described herein are possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

Aspect 14: An apparatus, including: a first memory cell coupled with a first access line and a first plate line; a second memory cell coupled with a second access line and a second plate line; a first sidewall and a second sidewall between the first memory cell and the second memory cell, the first and second sidewalls including a first dielectric material and separated by a gap region; and a cap over the first sidewall, the second sidewall, and the gap region, the cap including a second dielectric material.

Aspect 15: The apparatus of aspect 14, further including: a third memory cell coupled with a third access line and the first plate line; and a word line coupled with the first memory cell and the third memory cell.

Aspect 16: The apparatus of any of aspects 14 through 15, further including: a transistor array below the first memory cell and the second memory cell.

Aspect 17: The apparatus of aspect 16, where the transistor array includes: a first transistor configured to couple the first access line with a sense amplifier; and a second transistor configured to couple the second access line with the sense amplifier.

Aspect 18: The apparatus of any of aspects 14 through 17, where the first memory cell includes: a ferroelectric material; a first electrode configured to couple the ferroelectric material with the first access line; and a second electrode configured to couple the ferroelectric material with the first plate line.

Aspect 19: The apparatus of any of aspects 14 through 18, where: the first access line includes a first digit line; and the second access line includes a second digit line.

Aspect 20: The apparatus of any of aspects 14 through 19, where the gap region includes a fluid.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

Aspect 21: An apparatus, including: a first pair of memory cells configured to store a single logic state and including a first memory cell and a second memory cell; a second pair of memory cells configured to store a single logic state and including a third memory cell and a fourth memory cell; a first sidewall and a second sidewall between the first pair of memory cells and the second pair of memory cells, the first and second sidewalls including a first dielectric material and separated by a gap region; and a cap over the first sidewall, the second sidewall, and the gap region, the cap including a second dielectric material.

Aspect 22: The apparatus of aspect 21, further including: a first access line coupled with the first memory cell of the first pair of memory cells; and a second access line coupled with the second memory cell of the first pair of memory cells.

Aspect 23: The apparatus of any of aspects 21 through 22, further including: a first plate line coupled with the first pair of memory cells; and a second plate line coupled with the second pair of memory cells.

Aspect 24: The apparatus of any of aspects 21 through 23, further including: a transistor array below the first pair of memory cells and the second pair of memory cells.

Aspect 25: The apparatus of any of aspects 21 through 24, where the gap region includes a fluid.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.

The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (e.g., in conductive contact with, connected with, coupled with) one another if there is any electrical path (e.g., conductive path) between the components that can, at any time, support the flow of signals (e.g., charge, current voltage) between the components. At any given time, a conductive path between components that are in electronic communication with each other (e.g., in conductive contact with, connected with, coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. A conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.

The term “coupling” refers to condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components (e.g., over a conductive path) to a closed-circuit relationship between components in which signals are capable of being communicated between components (e.g., over the conductive path). When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow.

The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other when the switch is open. When a controller isolates two components from one another, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.

The terms “layer” and “level” used herein refer to an organization (e.g., a stratum, a sheet) of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, or materials. In some examples, one layer or level may be composed of two or more sublayers or sublevels.

As used herein, the term “electrode” may refer to an electrical conductor, and in some examples, may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, or the like that provides a conductive path between components of a memory array.

The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A switching component (e.g., a transistor) discussed herein may represent a field-effect transistor (FET), and may comprise a three-terminal component including a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a gate terminal). The terminals may be connected to other electronic components through conductive materials (e.g., metals, alloys). The source and drain may be conductive, and may comprise a doped (e.g., heavily-doped, degenerate) semiconductor region. The source and drain may be separated by a doped (e.g., lightly-doped) semiconductor region or channel. If the channel is n-type (e.g., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (e.g., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to providing an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions (e.g., code) on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a processor, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic device, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer, or a processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.