Methods of Forming Microelectronic Devices

This application is a divisional of U.S. patent application Ser. No. 18/478,821, filed Sep. 29, 2023, which is a divisional of U.S. patent application Ser. No. 17/344,444, filed Jun. 10, 2021, now U.S. Pat. No. 11,810,901, issued Nov. 7, 2023, the disclosure of each of which is hereby incorporated herein in its entirety by this reference.

The disclosure, in various embodiments, relates generally to the field of microelectronic device design and fabrication. More specifically, the disclosure relates to methods of forming microelectronic devices including microelectronic device structures each including control logic regions, and to related microelectronic devices, memory devices, and electronic systems.

Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, microelectronic device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.

One example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory devices including, but not limited to, volatile memory devices, such as dynamic random-access memory (DRAM) devices; and non-volatile memory devices such as NAND Flash memory devices. A typical memory cell of a DRAM device includes one access device, such as a transistor, and one memory storage structure, such as a capacitor. Modern applications for semiconductor devices can employ significant quantities of memory cells, arranged in memory arrays exhibiting rows and columns of the memory cells. The memory cells may be electrically accessed through digit lines (e.g., bit lines, data lines) and word lines (e.g., access lines) arranged along the rows and columns of the memory cells of the memory arrays. Memory arrays can be two-dimensional (2D) so as to exhibit a single deck (e.g., a single tier, a single level) of the memory cells, or can be three-dimensional (3D) so as to exhibit multiple decks (e.g., multiple levels, multiple tiers) of the memory cells.

Control logic devices within a base control logic structure underlying a memory array of a memory device have been used to control operations (e.g., access operations, read operations, write operations) of the memory cells of the memory device. An assembly of the control logic devices may be provided in electrical communication with the memory cells of the memory array by way of routing and interconnect structures. However, processing conditions (e.g., temperatures, pressures, materials) for the formation of the memory array over the base control logic structure can limit the configurations and performance of the control logic devices within the base control logic structure. In addition, the quantities, dimensions, and arrangements of the different control logic devices employed within the base control logic structure can also undesirably impede reductions to the size (e.g., horizontal footprint) of the memory device, and/or improvements in the performance (e.g., faster memory cell ON/OFF speed, lower threshold switching voltage requirements, faster data transfer rates, lower power consumption) of the memory device. Furthermore, as the density and complexity of the memory array have increased, so has the complexity of the control logic devices. In some instances, the control logic devices consume more real estate than the memory devices, reducing the memory density of the memory device.

The illustrations included herewith are not meant to be actual views of any particular systems, microelectronic structures, microelectronic devices, or integrated circuits thereof, but are merely idealized representations that are employed to describe embodiments herein. Elements and features common between figures may retain the same numerical designation except that, for ease of following the description, reference numerals begin with the number of the drawing on which the elements are introduced or most fully described.

The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without employing these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques employed in the semiconductor industry. In addition, the description provided herein does not form a complete process flow for manufacturing a microelectronic device (e.g., a semiconductor device, a memory device), apparatus, or electronic system, or a complete microelectronic device, apparatus, or electronic system. The structures described below do not form a complete microelectronic device, apparatus, or electronic system. Only those process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts to form a complete microelectronic device, apparatus, or electronic system from the structures may be performed by conventional techniques.

The materials described herein may be formed by conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. The removal of materials may be accomplished by any suitable technique including, but not limited to, etching, abrasive planarization (e.g., chemical-mechanical planarization), or other known methods unless the context indicates otherwise.

As used herein, the term “configured” refers to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a predetermined way.

As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” are in reference to a major plane of a substrate (e.g., base material, base structure, base construction, etc.) in or on which one or more structures and/or features are formed and are not necessarily defined by Earth's gravitational field. A “lateral” or “horizontal” direction is a direction that is substantially parallel to the major plane of the substrate, while a “longitudinal” or “vertical” direction is a direction that is substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate. With reference to the figures, a “horizontal” or “lateral” direction may be perpendicular to an indicated “Z” axis, and may be parallel to an indicated “X” axis and/or parallel to an indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9 percent met, or even 100.0 percent met.

As used herein, “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, features (e.g., regions, materials, structures, devices) described as “neighboring” one another means and includes features of the disclosed identity (or identities) that are located most proximate (e.g., closest to) one another. Additional features (e.g., additional regions, additional materials, additional structures, additional devices) not matching the disclosed identity (or identities) of the “neighboring” features may be disposed between the “neighboring” features. Put another way, the “neighboring” features may be positioned directly adjacent one another, such that no other feature intervenes between the “neighboring” features; or the “neighboring” features may be positioned indirectly adjacent one another, such that at least one feature having an identity other than that associated with at least one the “neighboring” features is positioned between the “neighboring” features. Accordingly, features described as “vertically neighboring” one another means and includes features of the disclosed identity (or identities) that are located most vertically proximate (e.g., vertically closest to) one another. Moreover, features described as “horizontally neighboring” one another means and includes features of the disclosed identity (or identities) that are located most horizontally proximate (e.g., horizontally closest to) one another.

As used herein, the term “memory device” means and includes microelectronic devices exhibiting memory functionality, but not necessarily limited to memory functionality. Stated another way, and by way of example only, the term “memory device” means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional DRAM; conventional non-volatile memory, such as conventional NAND memory), but also includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device combining logic and memory, and a graphics processing unit (GPU) incorporating memory.

As used herein, “conductive material” means and includes electrically conductive material such as one or more of a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fc), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), and a conductively-doped semiconductor material (e.g., conductively-doped polysilicon, conductively-doped germanium (Ge), conductively-doped silicon germanium (SiGe)). In addition, a “conductive structure” means and includes a structure formed of and including a conductive material.

As used herein, “insulative material” means and includes electrically insulative material, such one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiO), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlO), a hafnium oxide (HfO), a niobium oxide (NbO), a titanium oxide (TiO), a zirconium oxide (ZrO), a tantalum oxide (TaO), and a magnesium oxide (MgO)), at least one dielectric nitride material (e.g., a silicon nitride (SiN)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiON)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOCN)). Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiO, AlO, HfO, NbO, TiO, SiN, SiON, SiOCN) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including an insulative material.

According to embodiments described herein, a microelectronic device includes a first microelectronic device structure and at least a second microelectronic device structure coupled to the first microelectronic device structure. The first microelectronic device structure may include a memory array region (also referred to herein as an “array region”) and a first complementary metal oxide semiconductor (CMOS) region (e.g., a first control logic region) operably coupled to the array region and including first control logic devices configured to effectuate at least a portion of control operations of the array region. The second microelectronic device structure may include a second CMOS region (e.g., a second control logic region) operably coupled to the array region and including second control logic devices configured to effectuate at least an additional portion of control operations of the array region. In some embodiments, the first microelectronic device structure is attached (e.g., bonded) to the second microelectronic device structure by oxide-to-oxide bonding of a first insulative material of the first microelectronic device structure and a second insulative material of the second microelectronic device structure.

The memory array region of the first microelectronic device structure may include vertical stacks of memory cells. The vertical stacks of memory cells of the array region may individually include a vertical stack of storage devices (e.g., capacitors) each storage device operably coupled to a laterally neighboring access device (e.g., a transistor). Vertically neighboring access devices and vertically neighboring storage devices may be vertically spaced from each other by one or more insulative structures. First conductive pillars (also referred to as “digit lines”) may vertically extend through a vertical stack of the access devices. First conductive lines (also referred to as “word lines”) may vertically neighbor and laterally extend over each level of access devices. The first conductive lines may be configured to operably couple to the access devices to operably couple the access devices to a respective storage device. The first conductive lines may laterally terminate at a stair step structure located at lateral boundaries of the array region. The stair step structure may be defined by steps, the first conductive lines laterally terminating at a step of the stair step structure. Each step may individually be in electrical communication with a second conductive pillar that is, in turn, in electrical communication with one or more control logic devices of the second CMOS region of the second microelectronic device structure. The first CMOS region may vertically neighbor the array region. The first CMOS region may include control logic devices configured for effectuating at least some control operations of the vertical stacks of memory cells. For example, the first CMOS region may include sense amplifier (SA) regions (e.g., SA subregions) operably coupled to control logic devices of the second CMOS region configured to control various operations of the vertical stacks of memory cells. In some embodiments, the first CMOS region includes input/output devices.

The second CMOS region of the second microelectronic device structure may vertically neighbor the array region. In some embodiments, the second CMOS region is located on a vertical side of the array region opposite the first CMOS region. In some such embodiments, the array region may be vertically between (e.g., vertically interposed) the first CMOS region and the second CMOS region. The second CMOS region may include various CMOS circuitry, such as, for example, word line driver circuitry (e.g., sub word line driver circuitry, main word line driver circuitry), row decoders, sense amplifier driver circuitry, column select devices, column decoders, and other CMOS circuitry. In some embodiments, some of the control logic devices of the second CMOS region are electrically coupled to the memory cells of the memory array region and others of the control logic devices of the second CMOS region is electrically coupled to control logic devices of the first CMOS region. For example, the second CMOS region may include sub word line drivers electrically coupled to the memory cells of the memory array region by way of second conductive pillars vertically extending between the steps of the stair step structure and the second CMOS region. In addition, the second CMOS region may include column select devices electrically coupled to the sense amplifiers of the first CMOS region by means of electrically conductive interconnects.

The second microelectronic device structure may further include back end of line (BEOL) structures vertically overlying the second CMOS region. The second CMOS region may be vertically between (e.g., vertically interposed) between the array region and the BEOL structures.

Forming the microelectronic device to include the first microelectronic device structure including the first CMOS region and the second microelectronic device structure including the second CMOS region may improve the area efficiency of the microelectronic device, facilitating an increased density of memory cells (e.g., the vertical stacks of memory cells) of the microelectronic device. In addition, the location of the control logic devices of the first CMOS region and the second CMOS region may reduce the length of electrical connection paths of various circuitry of the microelectronic device, enhancing data transfer speeds and overall operating speed of the microelectronic device relative to conventional microelectronic devices.

throughare simplified partial perspective views (and), a simplified partial planar views (and), and simplified partial cross-sectional views (and) illustrating an embodiment of a microelectronic device(e.g., a memory device, such as a 3D DRAM memory device), in accordance with embodiments of the disclosure. With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods and structures described herein with reference tothroughmay be used in various devices and electronic systems.

Referring to, the microelectronic devicemay include a first microelectronic device structureand a second microelectronic device structureattached (e.g., bonded) to the first microelectronic device structure. The first microelectronic device structuremay be attached to the second microelectronic device structureby, for example, oxide-to-oxide bonding of insulative materials (not illustrated infor clarity) of the first microelectronic device structureand the second microelectronic device structure. The first microelectronic device structureand the second microelectronic device structuremay each individually comprise a die or wafer.

The first microelectronic device structuremay include an array regionincluding vertical stacks of memory cellsvertically overlying complementary metal oxide semiconductor (CMOS) circuitry (e.g., control logic devices) in a first CMOS regionof the microelectronic device.

The second microelectronic device structuremay include a second CMOS regioncomprising CMOS circuitry (e.g., control logic devices) and vertically (e.g., in the Z-direction) overlying the array regionof the microelectronic device.

Each of the first CMOS regionand the second CMOS regionmay include control logic devices (e.g., CMOS control logic devices) configured to effectuate at least a portion of control operations for the vertical stacks of memory cells. As will be described herein, the locations and relative arrangement of the control logic devices within the first CMOS regionand the second CMOS regionwith respect to each other and the array regionmay facilitate improved operation of the vertical stacks of memory cells. For example, the locations and relative arrangement of the control logic devices may reduce a distance between electrically coupled control logic devices and circuitry, facilitating enhancing data transfer speeds and improved operating speeds of the microelectronic device. In addition, the locations and relative arrangement of the control logic devices may facilitate a reduction in the area of the microelectronic deviceper bit of data and may facilitate an increased density of memory cells per unit area relative to conventional microelectronic device configurations. In some embodiments, the control logic devices of the first CMOS regionare different than the control logic devices of the second CMOS region.

With continued reference toand, the vertical stacks of memory cellsmay each include a vertical stack of storage devices(e.g., capacitor structures), individually laterally (e.g., in the X-direction, in the Y-direction) aligned with an access deviceof a vertical stack of access devices. Each storage devicemay be electrically coupled to an access devicelaterally (e.g., in the X-direction) and vertically (e.g., in the Z-direction) aligned with the storage device.

First conductive pillarsmay vertically extend through the access devicesand may be configured to electrically couple the access devicesto a respective storage device. The first conductive pillarsmay be in electrical communication with a column select deviceof the second microelectronic device structure. In some embodiments, and as illustrated in, each of the first conductive pillarsis individually in electrical communication with a routing structurefor electrically coupling the respective first conductive pillarto one of the column select devices. For clarity and case of understanding the description, not all of the each individual routing structureis illustrated in, but it will be understood that each of the routing structuresis in electrical communication a respective one of the first conductive pillarsto facilitate electrical communication between first conductive pillarsand the column select devices. In some embodiments, each column select deviceis in electrical communication with four of the first conductive pillars.

The first conductive pillarsmay be formed of and include conductive material, such as, for example, one or more of a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), a material including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO), ruthenium oxide (RuO), alloys thereof, a conductively-doped semiconductor material (e.g., conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium, etc.), polysilicon, or other materials exhibiting electrical conductivity. In some embodiments, the first conductive pillarsindividually comprise tungsten.

With continued reference to, the column select devicesmay each laterally (e.g., in the X-direction) neighbor a column decoderand may each be in electrical communication with a laterally neighboring column decoder. The column decodersare each, in turn, configured to receive an address signal from, for example, an address decoder.

First conductive linesmay extend laterally (e.g., in the Y-direction) over the access devices. The first conductive linesmay be referred to herein as “word lines.” In use and operation, a current may be applied to the first conductive linesto induce a current in a row of the respective access devicesand electrically couple the storage deviceassociated with a particular access deviceto the first conductive pillar.

The first conductive linesmay be formed of and include conductive material, such as, for example, one or more of the materials described above with reference to the first conductive pillars. In some embodiments, the first conductive linescomprise substantially the same material composition as the first conductive pillars. In other embodiments, the first conductive linescomprise a different material composition than the first conductive pillars. In some embodiments, the first conductive linescomprise tungsten.

The first conductive linesmay individually terminate at a stair step structurelaterally (e.g., in the X-direction) neighboring the array region. The stair step structuremay include stepsthat are vertically (e.g., in the Z-direction) offset from each other and electrically isolated from one another. For example, insulative structures(,) and additional insulative structures() may vertically intervene between vertically neighboring steps.

The number of stepsof the stair step structuresmay correspond to the number of levels of the vertical stack of memory cells(e.g., corresponding to the number of vertical levels of the first conductive lines, the storage devices, and the access device). Althoughillustrates that the stair step structuresinclude only a particular number of steps, the disclosure is not so limited. The stair step structuresmay each individually include a desired quantity of the steps, such as within a range from thirty-two (32) of the stepsto two hundred fifty-six (256) of the steps. In some embodiments, the stair step structureseach individually include sixty-four (64) of the steps. In other embodiments, the stair step structureseach individually include a different number of the steps, such as less than sixty-four (64) of the steps(e.g., less than or equal to sixty (60) of the steps, less than or equal to fifty (50) of the steps, less than about forty (40) of the steps, less than or equal to thirty (30) of the steps, less than or equal to twenty (20) of the steps, less than or equal to ten (10) of the steps); or greater than sixty-four (64) of the steps(e.g., greater than or equal to seventy (70) of the steps, greater than or equal to one hundred (100) of the steps, greater than or equal to about one hundred twenty-eight (128) of the steps, greater than two hundred fifty-six (256) of the steps).

Each stepmay individually be electrically coupled to a second conductive pillarvertically extending from the first CMOS regionto the second CMOS region. The second conductive pillarsmay be electrically coupled to a sub word line driverof the second microelectronic device structure. The sub word line driveris, in turn, electrically coupled to a main word line driverby electrical connections(). The main word line driveris electrically coupled to a row decoderby electrical connections(). The row decodermay be configured to receive an address signal from, for example, an address decoder, as described above with reference to the column decoder.

The second conductive pillarsmay each individually be formed of and include conductive material, such as, for example, for example, one or more of a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), a material including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO), ruthenium oxide (RuO), alloys thereof, a conductively-doped semiconductor material (e.g., conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium, etc.), polysilicon, or other materials exhibiting electrical conductivity. In some embodiments, the second conductive pillarscomprise substantially the same material composition as the first conductive pillars. In some embodiments, the second conductive pillarsindividually comprise tungsten.

The column select devicesmay each be electrically coupled to one or more SA devices of a SA region(e.g., a SA subregion) by way of first conductive interconnect structures. The SA devices of the SA regionmay, for example, include or more of equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs) (also referred to as N sense amplifiers), and PMOS sense amplifiers (PSAs) (also referred to as P sense amplifiers).

The first conductive interconnect structuresmay be formed of and include conductive material, such as one or more of the materials described above with reference to the second conductive pillars. In some embodiments, the first conductive interconnect structurescomprise tungsten. In other embodiments, the first conductive interconnect structurescomprise copper.

With continued reference to, the second microelectronic device structuremay further include a sense amplifier driver region. The sense amplifier driver regionmay include NMOS sense amplifier drivers (RNL) and PMOS sense amplifier drivers (ACT). The NMOS sense amplifier drivers may generate, for example, activation signals for driving the NMOS sense amplifiers of the sense amplifier regionsof the first CMOS regionand the PMOS sense amplifier drivers may generate, for example, activation signals for driving the PMOS sense amplifiers of the sense amplifier regionsof the first CMOS region. By way of non-limiting example, NMOS sense amplifier drivers generate a low potential (e.g., ground) activation signal for activating an NMOS sense amplifier of the sense amplifier regionand the PMPS sense amplifier drivers generate a high potential (e.g., Vec) activation signal for activating a PMOS sense amplifier of the sense amplifier region. However, the disclosure is not so limited and the NMOS sense amplifier drivers and the PMOS sense amplifier drivers may generate sense amplifier activation signals other than those described.

Devices and circuitry of the sense amplifier driver regionof the second CMOS regionmay be electrically coupled to devices and circuitry of the sense amplifier regionsof the first CMOS regions by way of second conductive interconnect structures. In some embodiments, the second conductive interconnect structuresinclude a first group of the second conductive interconnect structureselectrically connecting devices (e.g., NMOS sense amplifiers) and circuitry of the sense amplifier regionsto NMOS sense amplifier drivers of the sense amplifier driver region, and a second group of second conductive interconnect structureselectrically connecting additional devices (e.g., PMOS sense amplifiers) and circuitry of the sense amplifier regionsto PMOS sense amplifier drivers of the sense amplifier driver region.

In some embodiments, the second conductive interconnect structuresinclude first routing structuresfor laterally (e.g., in the X-direction, in the Y-direction) routing the second conductive interconnect structures. In some such embodiments, electrical connections of the second conductive interconnect structuresto devices and circuitry of the sense amplifier driver regiondo not directly vertically (e.g., in the Z-direction) overlie the electrical connections of the second conductive interconnect structuresto devices and circuitry of the sense amplifier regions. The sense amplifier driver regionof the second CMOS regionmay be laterally (e.g., in the Y-direction) offset from the sense amplifier regionsof the first CMOS region. In some embodiments, the sense amplifier regionsis located outside of lateral (e.g., in the Y-direction) boundaries of the sense amplifier driver region.

The second conductive interconnect structuresmay be formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structures. In some embodiments, the second conductive interconnect structurescomprise substantially the same material composition as the first conductive interconnect structures. In some embodiments, the second conductive interconnect structurescomprise tungsten.

With continued reference to, the first CMOS regionof the first microelectronic device structurefurther includes input/output (I/O) devices.

The I/O devicesmay be operably coupled to the second microelectronic device structureby third conductive interconnect structuresvertically (e.g., in the Z-direction) extending through the first microelectronic device structure. The third conductive interconnect structuresmay be electrically connected to a metallization levelconfigured to electrically connect the third conductive interconnect structuresto a global input/output device by means of global routing structuresand fourth conductive interconnect structures.

The third conductive interconnect structures, the fourth conductive interconnect structures, and the metallization levelmay individually be formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structures. In some embodiments, each of the third conductive interconnect structures, the fourth conductive interconnect structures, and the metallization levelindividually comprise tungsten.

The global routing structuresmay be formed of and include conductive material. In some embodiments, the global routing structurescomprises copper.

As will be described herein, the sense amplifier regions, the I/O devices, the column select devices, the column decoders, the main word line drivers, the row decoders, the sense amplifier driver regioneach individually include circuitry including transistors.

Accordingly, the first CMOS regionmay include control logic devices (e.g., the sense amplifiers within the sense amplifier regions, the I/O devices) configured for effectuating control operations for the vertical stacks of memory cellsand the second CMOS regionmay include additional control logic devices (e.g., the sub word line drivers, the main word line drivers, the row decoders, the sense amplifiers of the sense amplifier driver region, the column select devices, the column decoders) at least configured for effectuating additional control operations for the vertical stacks of memory cells. At least some of the control logic devices of the second CMOS regionmay be different than the control logic devices of the first CMOS region. In some embodiments, the array regionis vertically (e.g., in the Z-direction) interposed between the first CMOS regionof the first microelectronic device structureand the second CMOS regionof the second microelectronic device structure.

is a simplified partial planar (top-down) view of the microelectronic deviceandis a simplified partial planar (bottom-up) view of the first microelectronic device structure. With reference to, the second CMOS regionmay include the sub word line driversat and/or proximate lateral (e.g., in the X-direction) edges of the second microelectronic device structure. A main word line drivermay laterally (e.g., in the X-direction) neighbor each of the sub word line drivers. A row decodermay laterally (e.g., in the X-direction) neighbor a main word line driver. The main word line driversmay be laterally between a sub word line driverand a row decoder. The sense amplifier driver regionmay laterally (e.g., in the X-direction) neighbor the row decodersand may be laterally between row decoders.