Multilayer Ceramic Capacitor and Method of Manufacturing the Same

This application is the continuation application of U.S. patent application Ser. No. 18/428,594 filed on Jan. 31, 2024, which is a continuation of U.S. patent application Ser. No. 18/139,007, filed on Apr. 25, 2023, now U.S. Pat. No. 11,923,146, issued on Mar. 5, 2024, which is a continuation of U.S. patent application Ser. No. 17/586,322, filed on Jan. 27, 2022, now U.S. Pat. No. 11,270,844, issued on Mar. 8, 2022, which is a continuation of U.S. patent application Ser. No. 16/824,903, filed on Mar. 20, 2020, now U.S. Pat. No. 11,270,844, issued on Mar. 8, 2022, which claims benefit of priority to Korean Patent Application No. 10-2019-0112304, filed on Sep. 10, 2019, the disclosures of which are incorporated herein by reference in their entireties.

The present disclosure relates to a multilayer ceramic capacitor having improved reliability, and a method of manufacturing the same.

In general, an electronic component using a ceramic material such as a capacitor, an inductor, a piezoelectric element, a varistor, a thermistor, or the like, may include a ceramic body made of a ceramic material, an internal electrode formed in the body, and an external electrode provided on a surface of the ceramic body to be connected to the internal electrode.

It is a recent trend that chip components become miniaturized and multi-functionalized as electronic products are miniaturized and multi-functionalized. Accordingly, there is demand for multilayer ceramic capacitors to be miniaturized and to have high capacitance.

In order to make the multilayer ceramic capacitors small in size and high in capacitance, it may be necessary to maximize an effective area of the electrode and/or increase an effective volume fraction contributing to capacitance.

To accomplish a miniaturized and high capacitance multilayer ceramic capacitor, a method employing exposing the internal electrodes in the width direction of the body to maximize an area of the internal electrodes in the width direction through a design without a margin portion, and separately attaching a side margin portion to the exposed surfaces of the internal electrodes in the width direction of the chip during pre-sintering, after chip preparation, has been applied when manufacturing the multilayer ceramic capacitor.

In the case of the above method, however, a thickness and an area of the side margin portion are reduced, which increases risks of breakage and cracks due to external impacts.

Therefore, there is a need for applications of ceramic materials capable of improving impact resistance and crack resistance to miniaturized and high capacitance products.

An aspect of the present disclosure is to provide a multilayer ceramic capacitor having improved reliability, and a method of manufacturing the same.

According to an aspect of the present disclosure, a multilayer ceramic capacitor includes a ceramic body including a dielectric layer, and a first surface and a second surface opposing each other, a third surface and a fourth surface connecting the first and second surfaces, and a fifth surface and a sixth surface connected to the first to fourth surfaces and opposing each other. A plurality of internal electrodes are disposed in the ceramic body, are exposed on the first and second surfaces, and each have one end exposed through one of the third surface or the fourth surface. A first side margin portion and a second side margin portion are arranged on end portions of the internal electrodes exposed through the first and second surfaces, respectively. The ceramic body includes an active portion including the plurality of internal electrodes arranged to overlap each other with the dielectric layer interposed therebetween to form capacitance, and cover portions disposed above an uppermost internal electrode and below a lowermost internal electrode of the active portion. The first and second side margin portions include tin (Sn), and a content of Sn included in the first and second side margin portions is greater than a content of tin (Sn) included in the dielectric layer of the active portion.

According to another aspect of the present disclosure, a method of manufacturing a multilayer ceramic capacitor includes preparing a first ceramic green sheet having a plurality of first internal electrode patterns formed at a predetermined interval, and a second ceramic green sheet having a plurality of second internal electrode patterns formed at a predetermined interval, the first and second ceramic green sheets having a first content of tin (Sn). A laminated body is formed by laminating the first ceramic green sheet and the second ceramic green sheet such that the first internal electrode patterns and the second internal electrode patterns overlap each other. The laminated body is cut so as to have side surfaces opposing each other in a width direction and to which the first internal electrode patterns and the second internal electrode patterns are exposed, and a first side margin portion and a second side margin portion are respectively formed on the side surfaces opposing each other in the width direction, the first and second side margin portions having a second content of tin (Sn) higher than the first content. The cut laminated body is sintered to prepare a ceramic body having first and second internal electrodes overlapping each other with a dielectric layer therebetween.

According to another aspect of the present disclosure, a multilayer ceramic capacitor includes a ceramic body including pluralities of first internal electrodes and second internal electrodes that are alternately stacked to overlap with each other with dielectric layers interposed therebetween, and first and second external electrodes disposed on one or more external surfaces of the ceramic body and respectively connected to the plurality of first internal electrodes and the plurality of second internal electrodes. A content of tin (Sn) in a region of the ceramic body between an external surface of the ceramic body and the first and second internal electrodes is different from a content of tin (Sn) in the dielectric layers interposed between overlapping first and second internal electrodes.

Hereinafter, preferred embodiments of the present disclosure will be described with reference to the accompanying drawings. Exemplary embodiments of the present disclosure may be modified into various other forms, and the scope of the present disclosure is not limited to the embodiments described below. Exemplary embodiments of the present disclosure may be also provided to more fully describe the present disclosure to those skilled in the art. Therefore, the shapes and sizes of the elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.

is a schematic perspective view illustrating a multilayer ceramic capacitor according to an exemplary embodiment of the present disclosure.

is a perspective view illustrating an appearance of the ceramic body of.

is a perspective view illustrating a ceramic green sheet laminated body of the ceramic body of, prior to a sintering operation.

is a cross-sectional view taken along line I-I′ of.

Referring to, a multilayer ceramic capacitoraccording to an exemplary embodiment may include a ceramic body, a plurality of internal electrodesandformed in the ceramic body, and external electrodesandformed on one or more external surface(s) of the ceramic body.

The ceramic bodymay have a first surfaceand a second surfaceopposing each other, a third surfaceand a fourth surfaceopposing each other and connecting the first surface and the second surface, and a fifth surfaceand a sixth surface, which are an upper surface and a lower surface of the ceramic body.

The first surfaceand the second surfacemay be defined as surfaces opposing each other in a width direction of the ceramic body, the third surfaceand the fourth surfacemay be defined as surfaces opposing each other in a longitudinal or length direction, and the fifth surfaceand the sixth surfacemay be defined as surfaces opposing each other in a thickness direction.

A shape of the ceramic bodyis not particularly limited, but may be a rectangular parallelepiped shape as illustrated in the drawings.

The plurality of the internal electrodesandformed in the ceramic bodymay each have one end exposed through the third surfaceor the fourth surfaceof the ceramic body.

The internal electrodesandmay have a first internal electrodeand a second internal electrode, having different polarities, provided in pairs.

One end of each first internal electrodemay be exposed through the third surface, and one end of each second internal electrodemay be exposed through the fourth surface.

The other ends of the first internal electrodesand the second internal electrodes(e.g., the ends thereof disposed opposite to the one end) may be formed to be spaced apart from the fourth surfaceand the third surface, respectively, at regular intervals.

A first external electrodemay be formed on the third surfaceof the ceramic body to be electrically connected to the first internal electrode(s). A second external electrodemay be formed on the fourth surfaceof the ceramic body to be electrically connected to the second internal electrode(s).

A multilayer ceramic capacitoraccording to an exemplary embodiment of the present disclosure may include a plurality of internal electrodesanddisposed in the ceramic body, each exposed through the first and second surfacesand, and each having one end exposed through the third surfaceor the fourth surface; and a first side margin portionand a second side margin portionrespectively arranged on end portions of the internal electrodesandexposed through the first and second surfacesand, respectively.

A plurality of the internal electrodesandmay be formed in the ceramic body. Ends of each of a plurality of the internal electrodesandmay be exposed through the first and second surfacesand, which are surfaces opposite each other in the width direction of the ceramic body, and the first side margin portionand the second side margin portionmay be arranged on the exposed end portions, respectively.

An average thickness of each of the first side margin portionand the second side margin portionmay be 2 μm to 15 μm.

According to an exemplary embodiment of the present disclosure, the ceramic bodymay include a laminated body in which a plurality of dielectric layersare laminated, and a first side margin portionand a second side margin portionrespectively arranged on both side surfaces of the laminated body.

A plurality of the dielectric layersmay be in a sintered state, and boundaries between neighboring dielectric layers may be unified to a degree not capable of being confirmed with the naked eye.

A length of the ceramic bodymay correspond to a distance from the third surfaceto the fourth surfaceof the ceramic body.

A length of the dielectric layermay correspond to a space between the third surfaceand the fourth surfaceof the ceramic body.

According to an exemplary embodiment of the present disclosure, the length of the ceramic body may be 400 μm to 1400 μm. In particular, the length of the ceramic body may be 400 μm to 800 μm or 600 μm to 1400 μm.

The internal electrodesandmay be formed on the dielectric layers, and the internal electrodesandmay be formed in the ceramic bodywith a single dielectric layerinterposed between each adjacent pair thereof by a sintering process.

Referring to, the first internal electrodemay be formed on the dielectric layer. The first internal electrodemay not be formed entirely in the longitudinal direction of the dielectric layer. For example, one end of each first internal electrodemay be formed at a predetermined interval (e.g., spaced apart by the predetermined interval) from the fourth surfaceof the ceramic body, and the other end of the first internal electrode(e.g., the end opposite the one end) may be formed up to the third surfaceand exposed through the third surface.

End portions of the first internal electrodeexposed through the third surfaceof the ceramic body may be connected to the first external electrode.

In a different manner to the first internal electrode, one end of each second internal electrodemay be formed at a predetermined interval (e.g., spaced apart by the predetermined interval) from the third surface, and the other end of the second internal electrode(e.g., the end opposite the one end) may be exposed through the fourth surfaceand connected to the second external electrode.

The internal electrodes may be laminated in 400 layers or more for the implementation of a high-capacitance multilayer ceramic capacitor, but are not limited thereto.

Each dielectric layermay have a width equal to a width of the first internal electrode(s). For example, the first internal electrode(s)may be formed overall in the width direction of the dielectric layer(s).

According to an exemplary embodiment of the present disclosure, the width of the dielectric layer(s)and the width of the internal electrode(s)andmay be 100 μm to 900 μm, but are not limited thereto. In particular, the width of the dielectric layer(s) and the width of the internal electrode(s) may be 100 μm to 500 μm, or 100 μm to 900 μm.

As the ceramic body is miniaturized, the thickness of the side margin portionandmay affect the electrical characteristics of the multilayer ceramic capacitor. According to an exemplary embodiment of the present disclosure, the thickness of the side margin portion may be formed to be 15 μm or less, to improve the characteristics of the miniaturized multilayer ceramic capacitor.

For example, since the side margin portion may be formed to have a thickness of 15 μm or less, a high-capacitance and a miniaturized multilayer ceramic capacitor may be realized by maximally ensuring an overlapping region of the internal electrodes forming the capacitance.

The ceramic bodymay include an active portion serving as a portion contributing to capacitance formation of the capacitor, and upper and lower cover portions respectively formed on upper and lower surfaces of the active portion, as upper and lower margin portions.

The active portion may be formed by repeatedly laminating a plurality of the first and second internal electrodesandwith the dielectric layerinterposed therebetween.

The upper and lower cover portions may have the same material and configuration as the dielectric layer, except that they do not include internal electrodes. For example, the upper and lower cover portions may respectively extend above an uppermost internal electrode and below a lowermost internal electrode of the capacitor body.

For example, the upper and lower cover portions may include a ceramic material, for example, a barium titanate (BaTiO)-based ceramic material.

Each of the upper and lower cover portions may have a thickness of 20 μm or less, but is not limited thereto.

In an exemplary embodiment of the present disclosure, the internal electrode(s) and the dielectric layer(s) may be simultaneously cut off, and the width of the internal electrode(s) and the width of the dielectric layer(s) may thereby be formed to be the same. More specific details thereof will be described later.

The width of the dielectric layer(s) may be formed to be equal to the width of the internal electrode(s). Therefore, the ends of the internal electrodesandmay be exposed through the first and second surfacesandof the ceramic bodyopposite each other in the width direction.