Inverter Device

This application claims priority to Japanese Patent Application No. 2024-052400 filed on Mar. 27, 2024, the entire disclosure of which is incorporated by reference herein.

The technology disclosed herein belongs to a technical field related to an inverter device.

As inverter devices are becoming increasingly higher in power output with the improvement in power density, a technology for reducing the inductance of the inverter devices is being required.

Japanese Unexamined Patent Publication No. 2003-259656 describes a technology in which, in an inverter of DC-AC conversion, in order to reduce the interconnect inductance, two interconnect conductors are placed in parallel and close to each other and currents in the opposite directions are passed through the conductors, whereby the interconnect inductance is reduced by the use of the mutual inductance.

Conventional inverter devices are formed by mounting transistors on a surface of an interconnect substrate. However, in the mounting of transistors on a surface of an interconnect substrate, there arises a problem of failing to sufficiently reduce the self-inductance due to the influence of bonding wires connecting the transistors and the interconnect substrate.

In view of the above problem, an objective of the technology disclosed herein is reducing the inductance of an inverter device.

According to one mode of the technology disclosed herein, an inverter device includes: an interconnect substrate with a first interconnect layer formed on a surface; a plurality of transistors embedded in the interconnect substrate; a first capacitor provided between a first power line and a ground line in the first interconnect layer; and a second capacitor provided between the ground line and a second power line in the first interconnect layer, wherein the plurality of transistors include: a first transistor having a drain connected to the first power line and a source connected to a first interconnect; and a second transistor, placed on the side of the first transistor in a first direction orthogonal to the thickness direction of the interconnect substrate, having a drain connected to a second interconnect and a source connected to the second power line, and in the first interconnect layer, in planar view, the ground line is placed between the first power line provided at a position overlapping the first transistor and the second power line provided at a position overlapping the second transistor.

Having the above configuration, it is possible to shorten the interconnect between the first power line and the ground line and the interconnect between the second power line and the ground line in the inverter device. This can reduce the inductance of the inverter device. Moreover, since the terminals on the ground-line sides of the first capacitor and the second capacitor can be placed close to each other, the first capacitor and the second capacitor can be put together and placed efficiently. This can achieve downsizing of the inverter device.

As described above, according to the technology disclosed herein, the inductance of the inverter device can be reduced.

An illustrative embodiment will be described hereinafter with reference to the accompanying drawings. Note that the following description of the embodiment is merely illustrative essentially and will be made centering on the configuration related to the subject matter of the technology disclosed. Also, although technical elements different from the subject matter of the technology disclosed may be illustrated or described briefly, or description of such elements may be omitted, this will never be intended to limit the scope of the technology disclosed. In the present disclosure, the term “connection” is used as a concept broadly encompassing the state of being electrically connected. For example, the term “connection” includes, not only the case of direct connection between elements, but also the case of indirect connection between elements through a via or the like.

is a circuit diagram of an inverter deviceaccording to the embodiment.is a plan view of the inverter device, showing interconnects in an interconnect layer L, in which an interconnect layer Lis omitted.

As shown in, in this example, the inverter deviceis a 3-level inverter that outputs AC of three phases (U phase, V phase, and W phase) from a DC power supply such as a battery (not shown). The uses of the inverter deviceare not specifically limited, but include driving of automobiles and actuation of engines (e.g., an integrated starter generator (ISG)), for example.

As shown in, the inverter deviceincludes an interconnect substrateand inverter circuitsof three phases (U phase, V phase, and W phase) mounted in the interconnect substrate. The inverter circuitof each phase includes transistors Qto Q, a first capacitor C, and a second capacitor C. Note that, in the following description, the transistors Qto Qmay be collectively called the “transistors Q” when no distinction is made among them.

The interconnect substrateis a multi-layer interconnect substrate (e.g., a printed board) having six interconnect layers, for example. For convenience of description, as shown in, the thickness direction of the interconnect substrateis defined as the up/down direction, and the interconnect layer (first interconnect layer) having the principal surface (uppermost face) on which the first capacitor Cand the second capacitor Care placed is called an interconnect layer L. From the interconnect layer Ldownward, interconnect layers Lto L(second to sixth interconnect layers) are formed in this order with an insulating layer (e.g., a layer formed of resin) interposed between every adjacent interconnect layers. From the standpoint of improving heat dissipation performance, it is preferable to use a glass epoxy resin or a high thermal conductive resin for the insulating layer between the interconnect layer Land the interconnect layer L.

is a plan view of the inverter deviceas viewed from above the interconnect layer L, andis a bottom view of the inverter deviceas viewed from below the interconnect layer L, illustrated for one phase. In, the positions of the transistors Qto Qare indicated by the broken lines. Note that the X direction and the Y direction are defined as directions perpendicular to the up/down direction and also directions orthogonal to each other. Also, in the following description, out of the X direction, the leftward direction inmay be called the X1 direction and the rightward direction incalled the X2 direction. Also, out of the Y direction, the upward direction inmay be called the Y1 direction and the downward direction incalled the Y2 direction.

The transistors Q are each an n-type power MOSFET of a vertical structure, and in this example, constituted by a semiconductor chip Qa (simply indicated as a “chip” in the figures) and a lead frame Qb (see). The semiconductor chip Qa has a source on one face and a drain on the other face. The lead frame Qb, made of copper, for example, is formed to have a U-shape in sectional side view to cover the other face (drain) of the semiconductor chip Qa, and connected to the drain of the semiconductor chip Qa. That is, the lead frame Qb and the drain of the semiconductor chip Qa have the same potential.

In other words, the transistor Q has a source region S in which a source terminal is provided and a drain region D in which a drain terminal is provided to surround the source region S on one face, and has the drain region D on the other face. The “terminal” is used herein to mean an inlet/outlet of a current, and its specific form and mode are not specifically limited.

In the following description, the one face is called the “source-drain face” and the other face is called the “drain face.” Note that the “one face (source-drain face)” and the “other face (drain face)” as used herein are not limited to be flat faces. Specifically, for example, as will be described with reference tolater, there may be a step (vertical step in) on the source-drain face between the face on which the source is provided and the face on which the drain is provided. As another example, part of the face on which the source is provided and/or the face on which the drain is provided may be inflated or dented. Note that the gate of the transistor Q is formed on the source-drain face of the semiconductor chip Qa although illustration is omitted because it falls outside the subject matter of the technology disclosed.

Note that the source and drain of each transistor Q and interconnects formed in the interconnect layers Land Lare connected through a plurality of vias V and the lead frame Qb. For convenience of description, however, description of the connections through the vias V and the lead frame Qb may be omitted hereinafter. This also applies to connections of interconnects between interconnect layers: i.e., illustration may be omitted and description of connections through vias V and lead frames Qb may be omitted. Note also that, in, for easy understanding of the drawings, common hatching is given to interconnects to which a common signal or voltage is applied. In other words, in, interconnects under common hatching are mutually connected through vias and the like (whether shown or not shown).

The transistors Qto Qwill be described individually hereinafter.

As shown in, the transistors Qto Qof three phases are placed in a middle layer between the interconnect layer Land the interconnect layer L. In this example, the interconnect layer L, the interconnect layer LA, and an insulating layer X3 between the interconnect layers Land LA correspond to the “middle layer.” In other words, the transistors Qto Qof three phases are embedded in the interconnect substrate. As shown in, the transistors Qto Qof three phases are arranged in order in planar view. Note that, since the configurations of the transistors Qto Qare the same among U phase, V phase, and W phase, description here will be made for one phase only.

The transistor Q(corresponding to the first transistor) is placed with the drain face facing the interconnect layer Land the source-drain face facing the interconnect layer L, that is, positioned with the drain face facing upward. In the transistor Q, the drain terminal (hereinafter simply called the “drain”) on the drain face is connected to a first power linein the interconnect layer L, and the source terminal (hereinafter simply called the “source”) is connected to an interconnect(corresponding to the first interconnect) in the interconnect layer L.

The transistor Q(corresponding to the second transistor), located on the side of the transistor Qin the Y2 direction (corresponding to the first direction), is placed with the source-drain face facing the interconnect layer Land the drain face facing the interconnect layer L, that is, positioned with the source-drain face facing upward. In the transistor Q, the source is connected to a second power linein the interconnect layer L, and the drain on the drain face is connected to an interconnect(corresponding to the second interconnect) in the interconnect layer L.

The transistor Q(corresponding to the third transistor), located on the side of the transistor Qin the X2 direction (corresponding to the second direction), is placed with the source-drain face facing the interconnect layer Land the drain face facing the interconnect layer L, that is, positioned with the source-drain face facing upward. In the transistor Q, the source is connected to a ground line GND in the interconnect layer L, and the drain on the drain face is connected to the interconnectin the interconnect layer L.

The transistor Q(corresponding to the fourth transistor), located on the side of the transistor Qin the Y2 direction and on the side of the transistor Qin the X2 direction, is placed with the drain face facing the interconnect layer Land the source-drain face facing the interconnect layer L, that is, positioned with the drain face facing upward. In the transistor Q, the source is connected to the interconnectin the interconnect layer L, and the drain on the drain face is connected to the ground line GND in the interconnect layer L.

The transistor Q(corresponding to the fifth transistor), located on the side of the transistor Qin the X2 direction, is placed with the drain face facing the interconnect layer Land the source-drain face facing the interconnect layer L, that is, positioned with the drain face facing upward. In the transistor Q, the source is connected to an output interconnect OUT in the interconnect layer L, and the drain on the X1-direction side of the source-drain face is connected to the interconnectin the interconnect layer L.

The transistor Q(corresponding to the sixth transistor), located on the side of the transistor Qin the Y2 direction and on the side of the transistor Qin the X2 direction, is placed with the drain face facing the interconnect layer Land the source-drain face facing the interconnect layer L, that is, positioned with the drain face facing upward. In the transistor Q, the source is connected to the interconnectin the interconnect layer L, the drain on the X2-direction side of the source-drain face is connected to the output interconnect OUT in the interconnect layer L, and the drain on the drain face is connected to the output interconnect OUT in the interconnect layer L.

The first capacitor Cis provided between the first power lineto which a positive power supply voltage P (+) is supplied from a battery (not shown) or the like and the ground line GND that is grounded. The second capacitor Cis provided between the ground line GND and the second power lineto which a negative power supply voltage N (−) is supplied from a battery (not shown) or the like.

Specifically, the first capacitor Cand the second capacitor Care mounted on the surface of the interconnect layer L. As shown in, in the interconnect layer L, the ground line GND is placed between the first power lineprovided at the position overlapping the transistor Qand the second power lineprovided at the position overlapping the transistor Qin planar view. Note that, althoughshows an example in which the first power lineis provided to cover the entire of the transistor Q, that is, to overlap the entire of the transistor Qin planar view, the configuration is not limited to this. For example, the first power linemay be provided to cover part of the transistor Q. Specifically, the position of the end of the first power linein the Y1 direction may be located inward of the end of the transistor Qin the Y2 direction in planar view. This also applies to the relationship between the second power lineand the transistor Q.

The first capacitor Cis placed so that a terminal C(corresponding to the one terminal) overlaps the first power lineand a terminal C(corresponding to the other terminal) overlaps the ground line GND in planar view. In the interconnect layer L, the terminal Cand the first power lineare mutually connected, and the terminal Cand the ground line GND are mutually connected. The second capacitor Cis placed so that a terminal C(corresponding to the one terminal) overlaps the second power lineand a terminal C(corresponding to the other terminal) overlaps the ground line GND in planar view. In the interconnect layer L, the terminal Cand the second power lineare mutually connected, and the terminal Cand the ground line GND are mutually connected.

Moreover, in this embodiment, as shown in, in the interconnect layer L, the first power lineextends from the position overlapping the transistor Qto a position overlapping the transistor Qin the X2 direction, and the second power lineextends from the position overlapping the transistor Qto a position overlapping the transistor Qin the X2 direction. Also, in the interconnect layer L, the ground line GND extends in the X2 direction to the space between the first power lineprovided at the position overlapping the transistor Qand the second power lineprovided at the position overlapping the transistor Q. Part of the first capacitor Cis placed so that the terminal Coverlaps the first power lineat the position overlapping the transistor Qand the terminal Coverlaps the ground line GND provided in the Y2 direction with respect to the transistor Qin planar view, and these terminals and the lines are respectively connected. Similarly, part of the second capacitor Cis placed so that the terminal Coverlaps the second power lineat the position overlapping the transistor Qand the terminal Coverlaps the ground line GND provided in the Y1 direction with respect to the transistor Qin planar view, and these terminals and the lines are respectively connected. Note that, when the space for placing the first capacitor Cand the second capacitor Cis sufficiently secured, it is unnecessary to provide the first capacitor Cat the position overlapping the transistor Qand also unnecessary to provide the second capacitor Cat the position overlapping the transistor Q.

As shown in, the first power linein the interconnect layer Lis located to cover part or the entire of the transistor Qin planar view, and the first power lineis connected to the terminal C(see) of the first capacitor Cin the interconnect layer L. Also, the first power linein the interconnect layer Lis connected to the drain of the transistor Q. That is, the first power lineis an interconnect formed in the interconnect layer Land the interconnect layer L. Moreover, the first power linein the interconnect layer Lis connected to the first power linein the interconnect layer Lthrough vias and the like (not shown). The first power linein the interconnect layer Lis connected to the drain on the source-drain face of the transistor Q. Specifically, as shown in the plan view of, the first power lineis connected to the drain of the transistor Qin a C-shaped region in which the first power lineand the drain region D of the transistor Qoverlap each other. In other words, the first power lineoverlaps the drain region D on the source-drain face of the transistor Qin a C-shape and has a recessrecessed in a rectangular shape from the opening of the C-shape to the source region S of the transistor Qin the X1 direction, in planar view.

The interconnectis an interconnect formed in the interconnect layer L, and extends from the source region S of the transistor Qto the drain region D of the transistor Q, for example. The interconnectconnects the source of the transistor Q, the drain of the transistor Q, and the drain of the transistor Qto one another. As shown in, the interconnecthas a protrusionprotruding to the recessof the first power linein the X1 direction and overlapping the source region S of the transistor Qin planar view. At the position of the overlap of the protrusionwith the source region S of the transistor Q, the interconnectis connected to the source of the transistor Q. Also, the interconnectoverlaps the drain region D on the source-drain face of the transistor Qin a C-shape and has a recessrecessed in a rectangular shape from the opening of the C-shape to the source region S of the transistor Qin the X1 direction in planar view.

The output interconnect OUT is an interconnect formed in the interconnect layer L, and connects the source of the transistor Qand the drain of the transistor Qto each other. The power of each phase of the inverter deviceis output from the output interconnect OUT. Specifically, the output interconnect OUT includes: a protrusion OUTa that protrudes into the recessof the interconnectin the X1 direction and overlaps the source region S of the transistor Q; and a rectangular interconnect OUTb that is integrally and continuously formed with the protrusion OUTa and extends in the Y direction, in planar view. Further, the output interconnect OUT extends from the interconnect OUTb in the X1 direction, overlaps the drain region D on the source-drain face of the transistor Qin a C-shape, and has a recess OUTc recessed in a rectangular shape from the opening of the C-shape to the source region S of the transistor Qin the X2 direction, in planar view.

The interconnectis an interconnect formed in the interconnect layer L, and extends from the source region S of the transistor Qto a position beyond the end of the transistor Qin the X1 direction, for example. The interconnectconnects the source of the transistor Q, the source of the transistor Q, and the drain of the transistor Qto one another. The interconnecthas a protrusionprotruding into the recess OUTc of the output interconnect OUT in the X2 direction and overlapping the source region S of the transistor Qin planar view. At the position of the overlap of the protrusionwith the source region S of the transistor Q, the interconnectis connected to the source of the transistor Q.

As shown in, the ground line GND in the interconnect layer Lis positioned between the first power lineand the second power linein planar view. In the example of, the ground line GND has a protrusion GNDa protruding to the space between the first power lineand the second power linein planar view. It is this protrusion GNDa that is placed between the first power lineand the second power linein planar view. To state differently, in the interconnect layer L, the ground line GND is laid between the first power lineprovided at the position overlapping the transistor Qand the second power lineprovided at the position overlapping the transistor Qin planar view.

The ground line GND is connected to the terminal C(see) of the first capacitor Cand the terminal C(see) of the second capacitor Cin the interconnect layer L. Also, as described above, the ground line GND in the interconnect layer Lis connected to the source of the transistor Qand the drain of the transistor Q. Moreover, as shown in, the ground lines GND of the inverter circuitsof three phases are mutually connected through a common ground line GND (corresponding to the common ground line) extending in the Y direction over the three phases. Note that, althoughillustrates the configuration in the interconnect layer L, a common ground line GND extending in the Y direction over the three phases may also be provided in the interconnect layer L. For example, the common ground line may be provided to extend in the Y direction overlapping the transistor Qand the transistor Q. That is, the ground lines GND in the interconnect layer Linmay be mutually connected and extend over the inverter circuitsof three phases.

As shown in, the second power linein the interconnect layer Lis located to cover part or the entire of the transistor Qin planar view, and the second power lineis connected to the terminal C(see) of the second capacitor Cin the interconnect layer L. Also, as described above, the second power linein the interconnect layer Lis connected to the source of the transistor Q. That is, the second power lineis formed in the interconnect layer Land the interconnect layer L.

As described above, the inverter deviceof this embodiment includes the interconnect substratehaving the interconnect layer Lformed on the surface, a plurality of transistors Q embedded in the interconnect substrate, the first capacitor C, and the second capacitor C. The interconnect layer Lhas the first power line, the second power line, and the ground line GND. The first capacitor Cis provided between the first power lineand the ground line GND in the interconnect layer L. The second capacitor Cis provided between the ground line GND and the second power linein the interconnect layer L. The plurality of transistors Q include the transistors Qto Q. In the transistor Q, the drain is connected to the first power lineand the source is connected to the interconnect. In the transistor Q, placed on the side of the transistor Qin the Y2 direction, the drain is connected to the interconnectand the source is connected to the second power line. In the interconnect layer L, the protrusion GNDa of the ground line GND is provided between the first power lineprovided the a position overlapping the transistor Qand the second power lineprovided at the position overlapping the transistor Qin planar view. In other words, in the inverter deviceof this embodiment, in planar view, (1) the transistor Qand the transistor Qare placed side by side, (2) the first power lineis located to overlap part or the entire of the transistor Q, (3) the second power lineis located to overlap part or the entire of the transistor Q, (4) the ground line GND is located between the first power lineand the second power line, (5) the first capacitor Cis located so that the terminal Coverlaps the first power lineand the terminal Coverlaps the ground line GND, and (6) the second capacitor Cis located so that the terminal Coverlaps the second power lineand the terminal Coverlaps the ground line GND.

With the above configuration, it is possible to shorten the interconnect between the first power lineand the ground line GND and the interconnect between the second power lineand the ground line GND in the inverter device. In this way, the inductance of the inverter devicecan be reduced.

In the transistor Q, placed on the side of the transistor Qin the X2 direction, the drain is connected to the interconnectand the source is connected to the ground line GND. In the transistor Q, placed on the side of the transistor Qin the X2 direction and on the side of the transistor Qin the Y2 direction, the drain is connected to the ground line GND and the source is connected to the interconnect. In other words, the transistor Qand the transistor Qare placed side by side in the Y direction. The transistor Qis placed on the side of the transistor Qin the X2 direction, and the transistor Qis placed on the side of the transistor Qin the X2 direction.

In the transistor Q, placed on the side of the transistor Qin the X2 direction, the drain is connected to the interconnectand the source is connected to the output interconnect OUT. In the transistor Q, placed on the side of the transistor Qin the X2 direction and on the side of the transistor Qin the Y2 direction, the drain is connected to the output interconnect OUT and the source is connected to the interconnect. In other words, the transistor Qand the transistor Qare placed side by side in the Y direction. The transistor Qis placed on the side of the transistor Qin the X2 direction, and the transistor Qis placed on the side of the transistor Qin the X2 direction.

According to the configuration of this embodiment, downsizing of the inverter devicecan be achieved. This will be described with reference to the relevant drawings.shows a module configuration of the inverter deviceof this embodiment, andshows a module configuration (comparative example) of an inverter device in which the transistors Qto Qfor each phase are arranged linearly. In, a capacitor moduleof the same size and the interconnect substrateare placed side by side. The capacitor moduleis used for stabilizing the DC voltage.

As shown in, in the configuration of this embodiment, since the terminals on the ground-line sides of the first capacitor Cand the second capacitor C(the terminal Cand the terminal C) can be placed close to each other, the first capacitor Cand the second capacitor Ccan be put together and placed efficiently. This permits downsizing of the interconnect substrate, and in turn can achieve downsizing of the inverter device.

Moreover, in this embodiment, as shown in, the inverter circuitsof three phases (U phase, V phase, and W phase), each including the transistors Qto Q, the first capacitor C, and the second capacitor C, are arranged in the Y direction in the interconnect substrate. The ground lines GND of the inverter circuitsof three phases are mutually connected through the common ground line GND extending in the Y direction over the three phases.

Having the configuration described above, since a current route through the common ground line is formed between U phase and V phase, the inductance of the inverter devicecan be reduced. This will be described with reference to.

In U phase and V phase, a current may flow through the route indicated by the dashed-line arrow in the circuit diagram ofunder certain conditions in some cases. In such cases, if the ground line GND for U phase and the ground line GND for V phase are not connected through the common ground line GND, the current will flow through the route indicated by the dashed line in. By contrast, by mutually connecting the ground lines GND for U phase and V phase through the common ground line GND, the current flows through the route indicated by the solid line in. This shortens the current route and thus can reduce the inductance of the inverter device. This also applies to the other combinations of the phases.

As described above, the above embodiment is a mere illustration of the present disclosure and should not be construed to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims, and all modifications and changes belonging to the equivalence scope of the claims fall within the scope of the present disclosure. For example, the technology of the present disclosure is also applicable to inverter devices having circuit configurations other than that shown in. For example, in the above embodiment, the transistor Qand the transistor Qmay be replaced with diodes (not shown).

In the above case, a diode (first diode) replacing the transistor Qhas a cathode connected to the interconnectin the interconnect layer Land an anode connected to the ground line GND in the interconnect layer L. Similarly, a diode (second diode) replacing the transistor Qhas a cathode connected to the ground line GND in the interconnect layer Land an anode connected to the interconnectin the interconnect layer L.

In the above configuration using the first diode and the second diode, also, effects similar to those in the above embodiment can be obtained. Specifically, it is possible to shorten the interconnect between the first power lineand the ground line GND and the interconnect between the second power lineand the ground line GND in the inverter device. With this, the inductance of the inverter devicecan be reduced. Also, since the terminals on the ground-line sides of the first capacitor Cand the second capacitor C(the terminal Cand the terminal C) can be placed close to each other, the first capacitor Cand the second capacitor Ccan be put together and placed efficiently. This permits downsizing of the interconnect substrate, and in turn can achieve downsizing of the inverter device.