Semiconductor Memory Device and Manufacturing Method Thereof

The present application is a continuation application of U.S. patent application Ser. No. 18/435,272, filed on Feb. 7, 2024, which is a divisional application of U.S. patent application Ser. No. 17/543,525, filed on Dec. 6, 2021, which claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2021-0088742, filed on Jul. 6, 2021, in the Korean Intellectual Property Office, the entire contents of which applications are incorporated herein by reference.

The present disclosure generally relates to an electronic device, and more particularly, to a semiconductor memory device with a vertical channel structure and a manufacturing method thereof.

The paradigm on recent computer environment has been turned into ubiquitous computing environment in which computing systems can be used anywhere and anytime. This promotes increasing usage of portable electronic devices such as mobile phones, digital cameras, notebook computers, and the like. Such portable electronic devices may generally include a memory system using a semiconductor memory device, i.e., a data storage device. The data storage device is used as a main memory device or an auxiliary memory device of the portable electronic devices.

A data storage device that uses a semiconductor memory device has excellent stability and durability, high information access speed, and low power consumption, since there is no mechanical driving part. In an example of memory systems with such advantages, the data storage device includes a Universal Serial Bus (USB) memory device, memory cards with various interfaces, a Solid State Drive (SSD), and the like.

The semiconductor memory device is generally classified into a volatile memory device and a nonvolatile memory device.

The nonvolatile memory device has relatively slow write and read speeds, but retains stored data even when the supply of power is interrupted. Thus, the nonvolatile memory device is used to store data to be retained regardless of whether power is supplied. Examples of the nonvolatile memory include a Read Only Memory (ROM), a Mask ROM (MROM), a Programmable ROM (PROM), an Electrically Programmable ROM (EPROM), an Electrically Erasable and Programmable ROM (EEPROM), a flash memory, a Phase-change RAM (PRAM), a Magnetic RAM (MRAM), a Resistive RAM (RRAM), a Ferroelectric RAM (FRAM), and the like. The flash memory is classified into a NOR type flash memory and a NAND type flash memory.

In accordance with an aspect of the present disclosure, there is provided a semiconductor memory device including: a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on a substrate; a plurality of channel structures penetrating the gate stack structure, each of the plurality of channel structures with one end portion protruding past a boundary of the gate stack structure; and a source layer formed on the gate stack structure, wherein the protruding end portion of each of the plurality of channel structures extends into the source layer, and wherein the protruding end portion of each of the plurality of channel structures has a flat section.

In accordance with another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor memory device, the method including: forming a memory cell array on a first substrate, wherein the memory cell array includes a gate stack structure with interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction, a plurality of channel structures penetrating the gate stack structure, the plurality of channel structures each with an end portion extending into the first substrate, and a memory layer extending from between the plurality of channel structures and the gate stack structure to between the end portion of each of the plurality of channel structures and the first substrate; removing the first substrate to expose the memory layer; forming a first source layer on the top of the entire structure including the memory layer; performing an etching process to expose and level the memory layer, the channel structure, and the first source layer to be at the same height; and forming a second source layer on the memory layer, the channel structure, and the first source layer.

In accordance with still another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor memory device, the method including: forming a memory cell array on a first substrate, wherein the memory cell array includes a gate stack structure with interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction, a plurality of channel structures penetrating the gate stack structure, the plurality of channel structures each with an end portion extending into the first substrate, and a memory layer extending from between the plurality of channel structures and the gate stack structure to between the end portion of each of the plurality of channel structures and the first substrate; forming a bit line that is connected to the memory cell array; removing the first substrate to expose the memory layer; forming a first source layer on the top of the entire structure including the memory layer; etching the first source layer, the memory layer, and the end portion of each of the plurality of channel structures by performing a Chemical Mechanical planarization (CMP) process; and forming a second source layer on the top of the entire structure that includes the first source layer, the memory layer, and the end portion of each of the plurality of channel structures, which are planarized.

The specific structural or functional description disclosed herein is merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms, and cannot be construed as limited to the embodiments set forth herein.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings in order for those skilled in the art to be able to readily implement the technical spirit of the present disclosure.

Embodiments provide a semiconductor memory device capable of suppressing a pattern defect in a process for connecting a channel layer with a vertical channel structure and a source layer to each other, and a manufacturing method of the semiconductor memory device.

is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present disclosure.

Referring to, the semiconductor memory devicemay include a peripheral circuit PC and a memory cell array.

The peripheral circuit PC may be configured to control a program operation to store data in the memory cell array, a read operation to output data that is stored in the memory cell array, and an erase operation to erase data that is stored in the memory cell array. In an embodiment, the peripheral circuit PC may include a

voltage generator, a row decoder, a control logic, and a page buffer group.

The memory cell arraymay include a plurality of memory blocks. The memory cell arraymay be connected to the row decoderthrough word lines WL and connected to the page buffer groupthrough bit lines BL.

The control logicmay control the voltage generator, the row decoder, and the page buffer groupin response to a command CMD and an address ADD.

The voltage generatormay generate various operating voltages, such as an erase voltage, a ground voltage, a program voltage, a verify voltage, a pass voltage, and a read voltage, which are used for a program operation, a read operation, and an erase operation, based on the control logic.

The row decodermay select a memory block based on the control circuit. The row decodermay apply operating voltages to word lines WL that are connected to the selected memory block. The page buffer groupmay be connected to the memory cell

arraythrough the bit lines BL. The page buffer groupmay temporarily store data that is received from an input/output circuit (not shown) in a program operation based on the control logic. The page buffer groupmay sense a voltage or current of the bit lines BL in a read operation or a verify operation based on the control logic. The page buffer groupmay select bit lines BL based on the control circuit.

Structurally, the memory cell arraymay overlap with a portion of the peripheral circuit PC.

is a circuit diagram illustrating the memory cell array shown in.

Referring to, the memory cell arraymay include a plurality of cell strings CSand CSthat are connected between a source line SL and a plurality of bit lines BL. The plurality of cell strings CSand CSmay be commonly connected to a plurality of word lines WLto WLn. Each of the plurality of cell strings CSand CSmay include at

least one source select transistor SST that is connected to the source line SL, at least one drain select transistor DST that is connected to the bit line BL, and a plurality of memory cells MCto MCn that are connected in series between the source select transistor SST and the drain select transistor DST.

Gates of the plurality of memory cells MCto MCn may be respectively connected to the plurality of word lines WLto WLn that are stacked to be spaced apart from each other. Two or more drain select lines DSLand DSLmay be spaced apart from each other at the same level.

A gate of the source select transistor SST may be connected to a source select line SSL. A gate of the drain select transistor DST may be connected to a drain select line that corresponds to the gate of the drain select transistor DST.

The source line SL may be connected to a source of the source select transistor SST. A drain of the drain select transistor DST may be connected to a bit line that corresponds to the drain of the drain select transistor DST.

The plurality of cell strings CSand CSmay be divided into string groups that are respectively connected to the two or more drain select lines DSLand DSL. Cell strings that are connected to the same word line and the same bit line may be independently controlled by different drain select lines. Also, cell strings that are connected to the same drain select line may be independently controlled by different bit lines.

In an embodiment, the two or more drain select lines DSLand DSLmay include a first drain select line DSLand a second drain select line DSL. The plurality of cell strings CSand CSmay include a first cell string CSof a first cell string group that is connected to the first drain select line DSLand a second cell string CSof a second cell string group that is connected to the second drain select line DSL.

is a perspective view schematically illustrating a semiconductor memory device in accordance with an embodiment of the present disclosure.

Referring to, the semiconductor memory devicemay include a peripheral circuit that is disposed on a substrate SBU and gate stack structures GST that overlap with the peripheral circuit PC.

Each of the gate stack structures GST may include a source select line SSL, a plurality of word lines WLto WLn, and two or more drain select lines DSLand DSLthat are isolated from each other at the same level by an isolation structure DSM.

The source select line SSL and the plurality of word lines WLto WLn may extend in a first direction X and a second direction Y and may be formed into a flat plate shape that is parallel to a top surface of the substrate SUB. The first direction X may be a direction in which an X-axis faces in an XYZ coordinate system, and the second direction Y may be a direction in which a Y-axis faces in the XYZ coordinate system.

The plurality of word lines WLto WLn may be stacked to be spaced apart from each other in a third direction Z. The third direction Z may be a direction in which a Z-axis faces in the XYZ coordinate system.

The plurality of word lines WLto WLn may be disposed between the two or more drain select lines DSLand DSLand the source select line SSL.

The gate stack structures GST may be isolated from each other by a slit SI. The isolation structure DSM may be formed to be shorter in the third direction Z than the slit SI and may overlap with the plurality of word lines WLto WLn.

Each of the isolation structure DSM and the slit SI may extend in a linear shape, extend in a zigzag shape, or extend in a wave form. The width of each of the isolation structure DSM and the slit SI may be variously changed according to a design rule.

In accordance with an embodiment, the source select line SSL may be disposed to be closer to the peripheral circuit PC than the two or more drain select lines DSLand DSL.

The semiconductor memory devicemay include a source line SL, disposed between the gate stack structures GST and the peripheral circuit PC, and a plurality of bit lines BL, spaced apart farther from the peripheral circuit PC than the source line SL. The gate stack structures GST may be disposed between the plurality of bit lines BL and the source line SL.

is a sectional view illustrating the memory cell array shown in.

Referring to, in the memory cell array, a lower structure U and an upper structure T may be adhered to each other, and a string line structure STL_S may be disposed on the top of the upper structure T.

The upper structure T may include gate stack structures GST that are isolated by a slit SI, channel structures CH that penetrate the gate stack structures GST, a memory layer ML that extends along a sidewall of each of the channel structures CH, and a bit lineand a first connection structure Cthat are disposed under the gate stack structure GST.

The gate stack structure GST may include interlayer insulating layers ILD and conductive patterns CPto CPn, which are alternately stacked in a vertical direction. Each of the conductive patterns CPto CPn may include various conductive materials, including a doped silicon layer, a metal layer, a metal silicide layer, and a barrier layer, and the like. Each of the conductive patterns CPto CPn may include two or more kinds of conductive materials. For example, each of the conductive patterns CPto

CPn may include tungsten and a titanium nitride layer (TiN) surrounding a surface of the tungsten. The tungsten is a low-resistance metal and may decrease resistance of the conductive patterns CPto CPn. The titanium nitride layer TIN is a barrier layer and may prevent direct contact between the tungsten and the interlayer insulating layers ILD.

A first conductive pattern CP, among the conductive patterns CPto CPn, adjacent to the bit line, may be used as a drain select line DSL. In another embodiment, two or more conductive patterns that are adjacent to the bit lineand consecutively stacked may be used as drain select lines. An nth conductive pattern CPn, among the conductive patterns CPto CPn, adjacent to first and second source layers SLand SL, may be used as a source select line SSL. In another embodiment, two or more conductive patterns that are adjacent to the first and second source layers SLand SLand consecutively stacked may be used as source select lines. Conductive patterns (e.g., CPto CPn-) that are adjacent to each other in the vertical direction and disposed between the drain select line and the source select line may be used as the word lines WLto WLn, described above with reference to.

The channel structure CH may penetrate the gate stack structure GST in the vertical direction, and one end portion of the channel structure CH may be formed to protrude farther than the gate stack structure GST. The channel structure CH may be formed to be a hollow type. The channel structure CH may include a core insulating layerthat is filled in a central region thereof, a doped semiconductor layerthat is located at a lower end of the core insulating layer, and a channel layerthat surrounds the surfaces of the core insulating layerand the doped semiconductor layer. The channel layermay be used as a channel region of a cell string corresponding thereto. The channel layermay be formed of a semiconductor material. In an embodiment, the channel layermay include a silicon layer. The channel structure CH may be formed to protrude farther than the interlayer insulating layer ILD that is disposed at an uppermost portion of the gate stack structure GST. The protruding end portion, i.e., the core insulating layerand the channel layerof the channel structure CH may be formed to penetrate the first source layer SLand be directly connected to the second source layer SL. The core insulating layerand the channel layer, which protrude farther than the gate stack structure GST, may extend to the same height.

The memory layer ML may be formed to surround a surface of the channel structure CH. The memory layer ML may include a tunnel insulating layer TI that surrounds the channel layer of the channel structure CH, a data storage layer DS that surrounds the tunnel insulating layer TI, and a blocking insulating layer BI that surrounds the data storage layer DS. The memory layer ML may be formed to have the same length as the channel structure CH in the vertical direction. The memory layer ML may be formed to protrude farther than the interlayer insulating layer ILD that is disposed at the uppermost portion of the gate stack structure GST. A protruding end portion of the memory layer ML may be formed to penetrate the first source layer SLand be directly connected to the second source layer SL. The core insulating layer, the channel layer, and the memory layer ML, which protrude farther than the gate stack structure GST, may extend to the same height. The memory layer ML may be defined as a component that is included in the channel structure CH. In other words, the core insulating layer, the channel layer, and the memory layer ML, which protrude farther than the gate stack structure GST, may have a flat end portion at the top of the channel structure CH.

The bit linemay be disposed under the gate stack structure GST. The bit linemay be connected to the channel structure CH through contact plugsthat penetrate a plurality of insulating layers,, and. The bit linemay be spaced apart from a substrate SUB by a first insulating structureand a second insulating structure.

A first connection structurest_CS may include the first insulating structureand first connection structures Cthat are formed in the first insulating structure. The first connection structures Cmay include various conductive patterns,, and. The first insulating structuremay include two or more insulating layersA toD that are stacked between the bit lineand the second insulating structure.