Ferroelectric Memory Device and Method of Forming the Same

This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 17/572,623, filed on Jan. 10, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography and etching techniques to form circuit components and elements thereon.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Various embodiments provide a memory device such as a 3D memory array. In some embodiments, the 3D memory array is a ferroelectric field effect transistor (FeFET) memory circuit including a plurality of vertically stacked memory cells. In some embodiments, each memory cell is regarded as a FeFET that includes a word line region acting as a gate electrode, a bit line region acting as a first source/drain electrode, and a source line region acting as a second source/drain electrode, a ferroelectric material as a gate dielectric, and an oxide semiconductor (OS) as a channel layer. In some embodiments, each memory cell is regarded as a thin film transistor (TFT).

In the disclosure, the channel regions of the memory array are provided at gated regions only while removed from ungated regions. Therefore, the leakage current of such memory array is significantly reduced.

illustrate varying views of manufacturing a ferroelectric memory device in accordance with some embodiments.

Referring to, a substrateis provided. The substratemay be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substratemay be an integrated circuit die, such as a logic die, a memory die, an ASIC die, or the like. The substratemay be a complementary metal oxide semiconductor (CMOS) die and may be referred to as a CMOS under array (CUA). In some embodiments, the substrateincludes transistors at a top surface of the substrate. The transistors may include fin field effect transistors (FinFETs), nanostructure FETS (nano-FETs) (e.g., nanosheet transistors, nanowire transistors or gate-all-around transistors), planar FETs, the like, or combinations thereof, and may be formed by gate-first processes or gate-last processes. In some embodiments, the substratefurther includes interconnect structure electrically connected to the transistors. Although the transistors discussed above are formed over the substrate, other active devices (e.g., diodes or the like) and/or passive devices (e.g., capacitors, resistors, or the like) may also be formed as part of the functional circuits.

In some embodiments, a bulk multi-layer stackis formed over the substrate. In some embodiments, one or more interconnect layers including conductive features in insulting layers (e.g., low-k dielectric layers) may be disposed between the substrateand the multi-layer stack. In some embodiments, the conductive features may be patterned to provide power, ground, and/or signal lines for the active devices on the substrateand/or the ferroelectric memory devices (e.g., memory arrays/in). In some embodiments, one or more interconnect layers including conductive features in insulting layers (e.g., low-k dielectric layers) may be disposed over the multi-layer stack.

In, the multi-layer stackincludes alternating layers of sacrificial layersA-D (collectively referred to as sacrificial layers) and dielectric layersA-E (collectively referred to as dielectric layers). The sacrificial layersmay be patterned and replaced in subsequent stages to define conductive layers(e.g., the word lines). The sacrificial layersmay include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The dielectric layersmay include insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The sacrificial layersand the dielectric layersinclude different materials with different etching selectivities. In some embodiments, the sacrificial layersinclude silicon nitride, and the dielectric layersinclude silicon oxide. Each of the sacrificial layersand the dielectric layersmay be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), or the like.

Althoughillustrates a particular number of the sacrificial layersand the dielectric layers, other embodiments may include different numbers of the sacrificial layersand the dielectric layers. Besides, although the multi-layer stackis illustrated as having dielectric layers as topmost and bottommost layers, the disclosure is not limited thereto. In some embodiments, at least one of the topmost and bottommost layers of the multi-layer stackis a sacrificial layer.

Referring toand, photoresist patternsand underlying hard mask patternsare formed over the multi-layer stack. In some embodiments, a hard mask layer and a photoresist layer are sequentially formed over the multi-layer stack. The hard mask layer may include, for example, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The photoresist layer is formed by a spin-on technique, for example.

Thereafter, the photoresist layer is patterned to form photoresist patternsand trenchesbetween the photoresist patterns. The photoresist layer is patterned by a photolithography technique, for example. The patterns of the photoresist patternsare then transferred to the hard mask layer to form hard mask patternsby using an acceptable etching process. The etching may be anisotropic. Thus, trenchesare formed extending through the hard mask layer. Thereafter, the photoresistmay be optionally removed by an ashing process, for example.

Referring to,and, the patterns of the hard mask patternsare transferred to the multi-layer stackusing one or more etching processes. The etching processes may be anisotropic. Thus, the trenchesextend through the bulk multi-layer stack, and strip-shaped sacrificial layersand strip-shaped dielectric layersare accordingly defined. The hard mask patternsmay be then removed by an etching process.

Referring to,,and, the sacrificial layersA-D (collectively referred to as sacrificial layers) are replaced with conductive layersA-D (collectively referred to as conductive layers). In some embodiments, the sacrificial layersare removed by an etching process. Thereafter, conductive layersare filled into the space between adjacent dielectric layers. The replacement process includes performing suitable combination of deposition and etching operations. In some embodiments, each conductive layerincludes a metal layer(e.g., W, Ru, Co, Cu, Al, Ni, Au, Ag etc.) surrounded by a barrier layer(e.g., Ti, TiN, Ta, TaN, etc.), and the barrier layeris exposed to the adjacent trenches. In other embodiments, a metal layeris sandwiched by upper and lower barrier layers, and the sidewall of the metal layeris exposed to the adjacent trench.

Referring toand, upon the replacement process, the conductive layersA-D (collectively referred to as conductive layers) include the barrier layersA-D (collectively referred to as barrier layers) and the metal layersA-D (collectively referred to as metal layers).

Referring to, cap layersA-E (collectively referred to as cap layers) are formed on the sidewalls of the dielectric layersexposed by the trenches. In some embodiments, the operation of forming the cap layersincludes performing a selective growth process, such as a selective chemical vapor deposition (selective CVD) process, a selective atomic layer deposition (selective ALD) process or the like. In some embodiments, the cap layersinclude silicon-containing material, such as silicon oxide (SiO), silicon oxynitride (SiON), silicon oxycarbide (SiOC), the like or a combination thereof. In some embodiments, the cap layershave a thickness of about 1-15 nm, such as 5-10 nm. Other thickness ranges (e.g., more than 15 nm) may be applicable.

When the reaction temperature and the reaction gas are appropriately selected, the cap layersare selectively formed on the dielectric layers, rather than on the conductive layers. In some embodiments, the cap layersare selectively formed merely on the dielectric layers. In other embodiments, the cap layersare further formed to cover a portion of the adjacent conductive layers.

Referring to, a ferroelectric layeris formed on the sidewalls of the cap layersand sidewalls of the conductive layers. The ferroelectric layermay be deposited conformally in the trenchesalong sidewalls of the dielectric layersand the cap layers, along top surfaces of the dielectric layerE, and along the bottom surfaces of the trenches. The ferroelectric layermay include materials that are capable of switching between two different polarization directions by applying an appropriate voltage differential across the ferroelectric layer. For example, the ferroelectric layerincludes a high-k dielectric material, such as a hafnium (Hf) based dielectric materials or the like. In some embodiments, the ferroelectric layerincludes hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like.

In some embodiments, the ferroelectric layermay include barium titanium oxide (BaTiO), lead titanium oxide (PbTiO), lead zirconium oxide (PbZrO), lithium niobium oxide (LiNbO), sodium niobium oxide (NaNbO), potassium niobium oxide (KNbO), potassium tantalum oxide (KTaO), bismuth scandium oxide (BiScO), bismuth iron oxide (BiFeO), hafnium erbium oxide (HfErO), hafnium lanthanum oxide (HfLaO), hafnium yttrium oxide (HfYO), hafnium gadolinium oxide (HfGdO), hafnium aluminum oxide (HfAlO), hafnium zirconium oxide (HfZrO, HZO), hafnium titanium oxide (HfTiO), hafnium tantalum oxide (HfTaO), or the like. Specifically, the ferroelectric layerincludes HfZrO, HfAlO, HfLaO, HfCeO, HfO, HfGdO, HfSiO or a combination thereof. In some embodiments, the method of forming the ferroelectric layerincludes performing a suitable deposition technique, such as CVD, PECVD, metal oxide chemical vapor deposition (MOCVD), ALD, RPALD, PEALD, MBD or the like.

In some embodiments, the ferroelectric layerhas a thickness of about 1-20 nm, such as 5-10 nm. Other thickness ranges (e.g., more than 20 nm or 5-15 nm) may be applicable. In some embodiments, the ferroelectric layeris formed in a fully amorphous state. In alternative embodiments, the ferroelectric layeris formed in a partially crystalline state; that is, the ferroelectric layeris formed in a mixed crystalline-amorphous state and having some degree of structural order. In yet alternative embodiments, the ferroelectric layeris formed in a fully crystalline state. In some embodiments, the ferroelectric layeris a single layer. In alternative embodiments, the ferroelectric layerhas a multi-layer structure.

Thereafter, an annealing process is performed to the ferroelectric layer. The temperature range of the annealing process ranges from about 350° C. to about 450° C. (e.g., 400° C.) in an ambient containing N, H, Ar or a combination thereof, so as to achieve a desired crystalline lattice structure for the ferroelectric layer. In some embodiments, upon the annealing process, the ferroelectric layeris transformed from an amorphous state to a partially or fully crystalline state. In alternative embodiments, upon the annealing ferroelectric layeris transformed from a partially crystalline state to a fully crystalline state.

In some embodiments, the ferroelectric layeris conformally formed on the sidewall of the multi-layer stackand therefore has an uneven and wavy sidewall profile. Specifically, the ferroelectric layerhas a wavy profile including multiple separate recesses R from bottom to top, and the recesses R correspond to the conductive layers.

Referring to, a channel material layeris formed on the ferroelectric layer. The channel material layeris conformally deposited in the trenchesover the ferroelectric layerand fills in the recesses R of the ferroelectric layer. The channel material layerincludes materials suitable for providing channel layersfor the memory cells(see). For example, the channel material layerincludes oxide semiconductor (OS) such as zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO), indium tin oxide (ITO), combinations thereof, or the like. The channel material layermay be deposited by CVD, PVD, ALD, PECVD, or the like. The channel material layermay extend along sidewalls and bottom surfaces of the trenchesover the ferroelectric layer.

After the channel material layeris deposited, an annealing process is performed to the channel material layer. In some embodiments, the annealing process is performed at a temperature of about 300° C. to about 450° C. in oxygen-related ambient, so as to activate the charge carriers of the channel material layer.

Referring to, the channel material layeris partially removed, such that the remaining channel material layer forms channel layersA-D (collectively referred to as channel layers) on the ferroelectric layerand corresponding to the conductive layersA-D (collectively referred to as conductive layers), respectively.

In some embodiments, the channel material layeris partially removed by using an etching process. The etching may be anisotropic. In some embodiments, the portions of the channel material layerwithin the recesses R remain, while the portions the channel material layeroutside of the recesses R are removed. In some embodiments, the exposed surfaces of the channel regionsare flushed with the exposed surfaces of the ferroelectric layer.

Referring to, a dielectric layeris deposited in the trenchesover the channel layers. In some embodiments, the dielectric layerincludes silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like.

In some embodiments, isolation pillarsare formed through the dielectric layer. The isolation pillarsmay include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be formed by suitable combination of etching and deposition and operations. The isolation pillarsand the dielectric layermay include different materials. In some embodiments, the dielectric layerinclude oxide and the isolation pillarsinclude nitride. In some embodiments, the dielectric layerinclude nitride and the isolation pillarsinclude oxide. Other materials are also possible.

In some embodiments, conductive pillarsandare formed through the dielectric layeraside the isolation pillars. The conductive pillarsandare arranged alternately in some examples. In some embodiments, one isolation pillarare formed between two adjacent conductive pillarsand(e.g., source/drain pillars). The conductive pillarsandmay extend along a direction perpendicular to the conductive layerssuch that individual cells of the memory arraymay be selected for read and write operations. The conductive material may include copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, which may be formed by suitable combination of etching and deposition and operations. In the resulting structure, top surfaces of the multi-layer stack(e.g., the dielectric layerE), the ferroelectric layer, the conductive pillars, and the conductive pillarsmay be substantially level (e.g., within process variations). In some embodiments, the conductive pillarscorrespond to and are electrically connected to the bit lines in the memory array, and the conductive pillarscorrespond to correspond to and are electrically connected to the source lines in the memory array.

Thus, stacked memory cellsmay be formed in the memory array, as shown in. Each memory cellincludes a gate electrode/gated region (e.g., a portion of a corresponding conductive layer), a gate dielectric (e.g., a portion of a corresponding ferroelectric layer), a channel region (e.g., a channel layercorresponding to the gate electrode), and source/drain pillars (e.g., portions of corresponding conductive pillarsand). The isolation pillarsisolates adjacent memory cellsin a same column and at a same vertical level. The memory cellsmay be disposed in an array of vertically stacked rows and columns.

Although the embodiments ofillustrate a particular pattern for the conductive pillarsand, other configurations are also possible. For example, in these embodiments, the conductive pillarsandhave a staggered pattern. However, in other embodiments, the conductive pillarsandin a same row of the array are all aligned with each other.

In the disclosure, the channel regions of the memory array are provided at gated regions only while removed from ungated regions. Therefore, the leakage current of such memory array is significantly reduced.

The inventive concept of discontinuous channel layer can be modified.illustrate varying views of manufacturing a ferroelectric memory device in accordance with other embodiments. Similar elements are labeled as similar reference numerals. The difference between embodiments is described in details below, and the similarity between embodiments is omitted herein.

Referring to,,and, one or more multi-layer stacksare provided on a substrate. Each of the multi-layer stackincludes alternating layers of sacrificial layersA-D (collectively referred to as sacrificial layers) and dielectric layersA-E (collectively referred to as dielectric layers). The materials and forming methods of elements oftoare similar to those described into, so details are not iterated herein.

Referring toA,,and, the sacrificial layersA-D (collectively referred to as sacrificial layers) are replaced with conductive layersA-D (collectively referred to as conductive layers). The replacement process includes performing suitable combination of deposition and etching operations. In some embodiments, each conductive layerincludes a metal layer(e.g., W, Ru, Co, Cu, Al, Ni, Au, Ag etc.) surrounded by a barrier layer(e.g., Ti, TiN, Ta, TaN, etc.).

In some embodiments, liner layersA-D (collectively referred to as liner layers) are formed before the barrier layersA-D (collectively referred to as liner layers) are formed. The liner layersinclude silicon nitride (SiN), silicon carbide (SiC), metal oxide (e.g., HfO, AlO, etc.), the like or a combination thereof. Specifically, each conductive layeris surrounded by a liner layer, and sidewall of the liner layeris exposed to the adjacent trenches. In some embodiments, the liner layershave a thickness of about 1-15 nm, such as 5-10 nm. Other thickness ranges (e.g., more than 15 nm) may be applicable.

Referring to, the liner layersare partially removed, so that a recessis formed between the two adjacent dielectric layers. The recessesare connected to (e.g., in spatial communication with) the corresponding trenches. Specifically, the lateral portions of each liner layerremain between the dielectric layerand the adjacent barrier layer, while the vertical portions of each liner layerare removed. Accordingly, the recessesexpose the sidewalls of the barrier layers. In some embodiments, the recessesfurther expose the sidewalls of the metal layers. In some embodiments, the partial removing process includes an etching process, such as a lateral etching. The etching may be anisotropic. In some embodiments, the operation of partially removing the liner layersincludes performing a selective etching process. Accordingly, the multi-layer stackhas a curvy sidewall. Specifically, the ends of the dielectric layersare protruded from the ends of the conductive layers.

Upon the partial removing process, the conductive layerA is sandwiched by two liner layersAandA, the conductive layerB is sandwiched by two liner layersBandB, the conductive layerC is sandwiched by two liner layersCandCand the conductive layerD is sandwiched by two liner layersDandD.

Referring to, a ferroelectric layeris conformally formed on the sidewall of the multi-layer stackand therefore has an uneven and wavy sidewall profile. Specifically, the ferroelectric layerhas a wavy profile including multiple separate recesses R from bottom to top, and the recesses R correspond to the conductive layers. The material and forming method of the ferroelectric layerofare similar to the ferroelectric layerdescribed in, so details are not iterated herein.

Referring to, a channel material layeris formed on the ferroelectric layer. The channel material layeris conformally deposited in the trenchesover the ferroelectric layerand fills in the recesses R of the ferroelectric layer. The material and forming method of the channel material layerofare similar to the ferroelectric layerdescribed in, so details are not iterated herein.

Referring to, the channel material layeris partially removed, such that the remaining channel material layer forms channel layersA-D (collectively referred to as channel layers) on the ferroelectric layerand corresponding to the conductive layersA-D (collectively referred to as conductive layers), respectively. The partial removing of the channel material layerofare similar to those described in, so details are not iterated herein.

Referring to, a dielectric layeris deposited in the trenchesover the channel layers. In some embodiments, isolation pillarsare formed through the dielectric layer. In some embodiments, conductive pillarsandare formed through the dielectric layeraside the isolation pillars. In some embodiments, one isolation pillarare formed between two adjacent conductive pillarsand(e.g., source/drain pillars). The conductive pillarsandmay extend along a direction perpendicular to the conductive layerssuch that individual cells of the memory arraymay be selected for read and write operations. In the resulting structure, top surfaces of the multi-layer stack(e.g., the dielectric layerE), the ferroelectric layer, the conductive pillars, and the conductive pillarsmay be substantially level (e.g., within process variations). In some embodiments, the conductive pillarscorrespond to and are electrically connected to the bit lines in the memory array, and the conductive pillarscorrespond to correspond to and are electrically connected to the source lines in the memory array.

Thus, stacked memory cellsmay be formed in the memory array, as shown in. Each memory cellincludes a gate electrode/gated region (e.g., a portion of a corresponding conductive layer), a gate dielectric (e.g., a portion of a corresponding ferroelectric layer), a channel region (e.g., a channel layercorresponding to the gate electrode), and source/drain pillars (e.g., portions of corresponding conductive pillarsand). The isolation pillarsisolates adjacent memory cellsin a same column and at a same vertical level. The memory cellsmay be disposed in an array of vertically stacked rows and columns.

Although the embodiments ofillustrate a particular pattern for the conductive pillarsand, other configurations are also possible. For example, in these embodiments, the conductive pillarsandhave a staggered pattern. However, in other embodiments, the conductive pillarsandin a same row of the array are all aligned with each other.

In the disclosure, the channel regions of the memory array are provided at gated regions only while removed from ungated regions. Therefore, the leakage current of such memory array is significantly reduced.

The structures of the ferroelectric memory devices of the disclosure are described below with reference toto.

In some embodiments of the present disclosure, a ferroelectric memory device (e.g., memory array/) includes a multi-layer stack, a ferroelectric layer, and channel layers. The multi-layer stackis disposed on a substrateand includes conductive layersand dielectric layersstacked alternately. The ferroelectric layerhas a curvy profile and is disposed along sidewalls of the conducive layersand sidewalls of the dielectric layers. The channel layersare separated from each other and disposed on the ferroelectric layer, and correspond to the conductive layersrespectively. In some embodiments, surfaces of the channel layersare flushed with a surface of the ferroelectric layer.

In some embodiments, the ferroelectric memory device (e.g., memory array) further includes a plurality of cap layers, wherein each of the cap layersis disposed between one of the dielectric layersand the ferroelectric layer. The cap layersare regarded as part of the multi-layer stackin some examples. In some embodiments, each of the cap layersincludes silicon oxide, silicon oxynitride, silicon oxycarbide or a combination thereof.