Source & Drain Bodies in Stacked Transistor Architectures

Demand for higher performance integrated circuits (ICs) in electronic device applications has motivated increasingly dense transistor architectures. Stacked gate-all-around (GAA) transistor structures, such as ribbon or wire (RoW) structures, include a plurality of channel material structures that are in a vertical stack with one channel structure over another.

For any transistor architecture, it is advantageous to reduce extrinsic electrical resistances. Extrinsic resistance may be limited by a conductivity of source and/or drain semiconductor material and/or a contact resistance between the source and/or drain semiconductor material and a contact metallization. For stacked transistor structures, the device geometry and/or small spaces between vertically stacked channel regions may induce higher extrinsic resistance.

Fabrication techniques and stacked transistor architectures that reduce extrinsic resistance for even the most aggressively scaled devices are therefore commercially advantageous.

Embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to “an embodiment” or “one embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” or “some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. These terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause-and-effect relationship).

The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or layer over or under another may be directly in contact or may have one or more intervening materials or layers. Moreover, one material between two materials or layers may be directly in contact with the two materials/layers or may have one or more intervening materials/layers. In contrast, a first material or layer “on” a second material or layer is in direct contact with that second material/layer. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.

The inventors have determined extrinsic resistance of a stacked transistor structure can be reduced if contact metallization is interfaced to multiple, individual source/drain material bodies rather than interfacing with a single contiguous source/drain material.illustrates an isometric sectional view of an integrated circuit (IC) portion, which includes two adjacent transistor stack structuresand. Each of transistor stack structures,include a stack of multiple source and/or drain bodies. Transistor stack structures,have a GAA transistor architecture with a plurality of stacked channel regions, layers, or structuressurrounded by a gate electrode material. Transistor stack structures,are illustrated as including a vertical (e.g., z-axis) stack of four active channel structures, but transistor stack structures,may include any integer number of channel regions (e.g., 2, 3, 4, 5 . . . 10 . . . 20, etc.) as embodiments herein are not limited in this respect. Channel structuresmay each have any dimensions and architecture, such as a ribbon or wire (RoW) of any thickness (e.g., z-dimension), width (e.g., x-dimension), and length (e.g., y-dimension), etc.

Channel structuresare over a sub-channel material, which may have been part of a workpiece substrate, such as a large format semiconductor wafer, for example. An integrated circuit including IC portionmay include any number of backend interconnect metallization levelsover a “top” or “front” side of transistor structuresand. Metallization levelsmay have any known structure interconnecting one or more transistor terminals with other nodes in a circuit topology. Structural aspects of sub-channel materialand metallization levelsare not depicted into avoid obscuring the view of transistor stack structures,. However, it is in reference to sub-channel materialand/or metallization levelsthat channel structuresmay be referred to herein as within a vertical stack between overlying metallization levelsand underlying substrate material.

In, two orthogonal planes A and B are demarked by dashed line. Plane A is a “gate-cut” plane that passes through a transverse width of a gate electrodeand passes through a longitudinal length of channel structures. Plane B is a “fin-cut” plane that passes through a transverse width of the stacks of channel structuresand passes through a longitudinal length of one gate electrode.

Transistor stack structures,may each comprise one or more transistors within each stack structure. For embodiments where stack structure(and) includes a plurality of transistors, the two or more transistors may each include one or more of channel structures. The four channel structuresillustrated may therefore be components of a single transistor, or each a component of a different transistor. If there are multiple transistors within each of stack structureand/or, they may be of the same conductivity type (e.g., PMOS), or of complementary conductivity types (e.g., a CMOS stacked transistor, or “CFET”).

In accordance with some embodiments, transistor stack structuresandinclude a PMOS stack where at least two of channel structuresare coupled at opposite ends to source and/or drain bodieshaving p-type conductivity. In some exemplary embodiments, all of channel structuresare portions of one or more p-type transistors. In one illustrative embodiment, all of channel regionsare operable to contribute to a total drive current of a single (e.g., PMOS) transistor.

As described further below, a plurality of source and/or drain bodiesare in a vertical stack, with each individual source/drain bodybeing a head, or “nub,” at an end of one channel structure. This stack of individual source/drain bodiesis in contrast to a single contiguous body that unifies the stack of channel structures. Individual source and/or drain bodiesare ready to be directly contacted with a metallization (e.g., source/drain contact metallization), which is not depicted into avoid obscuring the stack of source and/or drain bodies. The surface area of each individual source and/or drain bodymay be entirely covered by the contact metallization, reducing contact resistance for any given specific contact resistivity. Contact metallization may extend along, or line a sidewall of, the entire vertical height of each transistor stack structure,effectively providing a localized vertical interconnect route across the stack of source and/or drain bodies. Any vertical spacing between adjacent source and/or drain bodiesmay be spanned by the contact metallization. According to embodiments herein, a total volume of the source and/or drain bodiesmay be reduced in favor of metallization.

Source and/or drain bodiesare electrically and physically coupled to opposite sides of channel structures. In this example, source and/or drain bodiesare each faceted epitaxial material that has been grown, for example laterally from an end seeding surface of channel structureswhich are otherwise embedded in one or more dielectric materials. However, source and drain bodiesneed not be epitaxial material, in which case the facets shown inmay not be present.

In some PMOS embodiments, each source/drain bodycomprises a SiGealloy with one or more p-type (acceptor) impurities. As further described below, each source/drain bodymay include multiple layers with different alloy compositions and/or impurity dopant compositions. Although described below in the context of a PMOS transistor stack structure, transistor stack structures,may be similarly implemented as an NMOS transistors stack. For such embodiments, the principles taught in the context of a PMOS transistor stack structure may be likewise applied toward reducing extrinsic electrical resistance of an NMOS transistor stack structure.

Gate electrodeis between channel structures, and between dielectric material. A gate insulator (not depicted) is between gate electrodeand each channel structure. Transistor stack structures,may further include one or more additional dielectric materials. In the illustrated example, an isolation dielectric materialis under gate electrodewhere gate electrodeextends laterally beyond a sidewall of channel structures. Other dielectric material (not depicted) may surround source and/or drain bodies, as well as gate electrode.

is a flow diagram illustrating methodsfor forming a transistor stack structure including a stack of multiple source or drain bodies, in accordance with some embodiments. Methodsbegin at inputwhere a workpiece, such as a 300 mm semiconductor material wafer, is received. The workpiece includes a stack of channel structures as fabricated according to any suitable techniques upstream of methods. At blocka stack of individual source and/or drain material bodies are formed at exposed ends of the channel structures, resulting in a stack of two or more discrete source/drain material bodies. In exemplary embodiments, blockentails an epitaxial growth process that may seed from exposed end surfaces of crystalline material of the channel structures. In some PMOS embodiments where the channel material is substantially single crystalline silicon, a substantially single-crystal SiGe alloy is grown at block. The SiGe alloy comprises one or more acceptor impurities. In advantageous embodiments, the composition of the SiGe alloy is modulated over a duration of the growth and/or between multiple growth cycles, for example to form compositionally layered or graded source and/or drain material bodies. The growth process is performed for a sufficient total duration that a thickness of the source and/or drain material bodies becomes larger than a corresponding thickness of the channel material, but ideally not so long that a first source or drain material body seeded from a first channel structure merges with a second source or drain material body seeded from a second channel structure immediately above or below the first channel structure.

Methodscontinue at blockwhere a contact metallization is deposited to contact the individual source or drain material bodies. The contact metallization advantageously contacts the enlarged surface of each source or drain material body increasing the contact surface area between the metallization. For embodiments where each source or drain body is compositionally layered or graded, the enlarged metallization interface area contact resistance may be further reduced.

Methodsend at outputwhere a transistor structure is completed according to any known techniques and terminals of the transistor structure are interconnected into integrated circuitry through the fabrication of any number of metallization features (e.g., lines and vias) within any number of interconnect metallization levels.

is a flow diagram illustrating methodsfor forming a stack of Ga-enriched layered SiGe source and drain bodies, in accordance with some stacked PMOS transistor embodiments. Methodsagain begin at inputwith receipt of a workpiece suitable for IC fabrication. A working surface of the workpiece comprises a plurality of channel structure stacks, for example that are to be further processed into transistor stack structures.illustrates a cross-sectional view of channel stack structures corresponding to the transistor stack structureand transistor stack structurealong the A-A′ plane introduced in, in accordance with some embodiments.illustrates a second cross-sectional view a channel stack structure corresponding to transistor stack structurealong the B-B′ plane introduced in.

As shown in, adjacent channel stack structures are separated by an intervening space or trench. Channel structureshave a longitudinal channel length (e.g., along y-axis) extending between two trenches. Channel structuresextend through dielectric material, and one or more additional dielectric materialsmay be adjacent to an end surface of channel structuresexposed along a sidewall of trench. Channel structuresare bodies of semiconductor material that may have been patterned from a fin of a substrate material layers, for example. Although the substantially rectilinear profiles of channel structuresillustrated inare simplifications, an exposed end surface of each channel structurehas a thickness Tregardless of the channel structure profile. Thickness Tmay be associated with a layer thickness of an epitaxial stack, for example. Although channel structuresare illustrated inas nanoribbons having a transverse width greater than thickness T, channel structuresmay instead have alternative forms. For example, channel structuresmay also be nanowires of nearly equal thickness and width.

In exemplary embodiments, channel structuresare crystalline semiconductor. Although the crystalline semiconductor includes polycrystalline thin film material, the crystalline semiconductor may be advantageously substantially monocrystalline. In some such embodiments, the crystallinity of channel structuresis cubic with the top surfaces (opposite substrate material) having crystallographic orientation of (100), (111), or (110), for example. Other crystallographic orientations are also possible. In some embodiments, channel structuresare a substantially monocrystalline group IV semiconductor material, such as, but not limited to substantially pure silicon (e.g., having only trace impurities), silicon alloys (e.g., SiGe), or substantially pure germanium (e.g., having only trace impurities). Channel structuresmay also have any of these same exemplary compositions in alternative polycrystalline or amorphous embodiments, for example where a channel structure stack has been fabricated from thin film semiconductor material layers. Although in exemplary embodiments channel structureseach have a substantially homogenous composition, a channel structuremay alternatively comprise one or more semiconductor heterojunctions that, for example further include a first semiconductor material adjacent to a second semiconductor material.

As further illustrated in, channel structuresare separated from each other by an intervening material, which may be subsequently replaced with a gate stack (e.g., comprising a gate insulator and gate electrode material). Intervening materialmay have any compatible composition, such as SiGe for embodiments where channel structuresare substantially single crystalline silicon.

Returning to, methodscontinue at blockwhere semiconductor material is grown from individual exposed ends of the channel structures. The growth is advantageously selective to the channel structure surfaces, and may comprise a vapor phase epitaxy/deposition process, for example a low pressure CVD (LPCVD) process performed a temperature in the range of 325-500° C. and a pressure in the range of 5-20 Torr. Precursor gases may be co-flowed or cyclically flowed, for example in a dep-etch process. Precursor gases may include silane, silicon tetrachloride, germanium tetrachloride, or the like. The material grown at blockmay comprise one or more electrically active impurities that are cither introduced in-situ during epitaxial growth, or implanted into the semiconductor material subsequent to material growth. According to some exemplary embodiments, the volume of semiconductor material grown at blockis limited to form a plurality of separate crystals that can each serve as a seed for subsequent additional material growth.

In the example illustrated in, semiconductor material protrusionshave been selectively formed upon the end faces of channel structures. In exemplary PMOS embodiments, semiconductor material protrusionsare p-type, comprising at least one of a p-type (acceptor) impurity species, such as boron. Although acceptor concentrations may vary with species and implementation, in exemplary boron embodiments semiconductor material protrusionshave a boron concentration less than 2e21 atoms/cm. In some specific examples, boron concentration is in the range of 4-5e20 atoms/cm.

For embodiments where the channel structuresare substantially pure silicon, semiconductor material protrusionsare also a Group IV material, such as silicon, germanium, or a silicon-germanium alloy having a first germanium concentration (SiGe). In some exemplary PMOS embodiments, protrusionsare SiGehaving a germanium concentration less than 50 atomic percent (at. %). Although germanium concentration may vary with implementation, in some examples the germanium concentration is at least 20 at. % and may be in the range of 20-40 at. %.

As further illustrated inand, source and drain semiconductor material protrusionsare grown to have a thickness T, greater than the corresponding thickness Tof channel structures. Thickness Tis limited such that adjacent protrusions remain spaced apart by an intervening non-zero gap or space S. Source and drain semiconductor material protrusionstherefore remain a stack of individual bodies.

Returning to, methodscontinue at blockwhere a protective material is deposited over the source and drain semiconductor material protrusions formed at block. The deposited material may protect source and drain semiconductor material from subsequent fabrication operations. Advantageously, the material deposited at blockmay limit the loss of impurity dopants from within the underlying source and drain semiconductor material bodies during subsequent fabrication operations. The material deposited at blockmay have any chemical composition suitable as a protective layer and that can be subsequently removed with adequate selectively relative to other materials present within the stacked transistor structure. In some embodiments, a silicon-based dielectric material or a carbon-based dielectric material is deposited at block, for example with a chemical vapor deposition process or a spin-on/cure process.

In the example illustrated in, materialhas been deposited over source and drain semiconductor material protrusions. In this example, materialsubstantially fills trenchbetween adjacent channel stack structures. In advantageous embodiments, materialretards outdiffusion of impurity dopants (e.g., boron in exemplary PMOS embodiments) from source and drain semiconductor material protrusions, which may otherwise occur during subsequent fabrication operations, particularly those involving elevated temperatures (e.g., exceeding 400° C.).

Returning to, methodscontinue at blockwhere one or more fabrication operations are performed. Such operations may entail any frontside or backside processing of a workpiece comprising stacked transistor structures. Frontside processing may comprise a thermal annealing of transistor structures formed thus far. For example, the source and drain material protrusions may be annealed and impurities (e.g., that had been implanted) within the source and drain material electrically activated, and/or impurities present within the source and drain material may be thermally driven into ends of the channel structures. Frontside processing may also (or in the alternative) entail the further formation of one or more additional transistor structures. In some embodiments, at blocksacrificial material between channel material structures is replaced with a gate stack comprising a gate insulator and a gate electrode. For example, while source and drain material protrusions are protected, a wet chemical etch process is utilized to remove sacrificial layers (e.g., comprising SiGe) selectively from intervening channel structures (e.g., comprising Si) to expose the channel structures as ribbons or wires. Following the exposure of channel structures, gate insulator material and gate electrode material may be deposited (e.g., by atomic layer deposition) around the channel structures while source and drain material protrusions remain protected. After the gate structure is formed, the transistor stack structures may be heated to a temperature of over 400° C. (e.g., 500° C., 750° C., or 850° C.) for a predetermined time in the presence of any suitable ambient, such as, but not limited to, nitrogen (N), or forming gas (N:H). Such a post-gate thermal cycle may be performed to set a transistors threshold voltage (Vi), for example.

Following operations performed at block, methodscontinue at blockwhere at least a portion of the material deposited at blockis removed to expose the source and drain material protrusions formed at block. Any etch process selective to the composition of the material deposited at blockmay be practiced at blockas embodiments are not limited in this respect.

Methodscontinue at blockwhere the source and drain material protrusions formed at blockare augmented with a further deposition of semiconductor material. Material growth is advantageously selective to the to the source and drain material protrusions relative to one or more dielectric materials surrounding the protrusions. In some embodiments, a vapor phase epitaxy or deposition process is performed at block. The process may be similar to that performed at block(e.g., performed a temperature in the range of 325-500° C. and a pressure in the range of 5-20 Torr). Precursor gases may again be introduced either cyclically or co-flowed and may similarly include silane, silicon tetrachloride, germanium tetrachloride, or the like. In some PMOS embodiments where a silicon-germanium alloy was grown at block, a silicon-germanium alloy is also grown at block. However, in exemplary embodiments, the silicon-germanium alloy grown at blockhas a significantly higher germanium concentration than that grown at block. For example, the atomic percentage of germanium in the material grown at blockmay be two, or even three, times that of the material grown at block. Higher germanium concentrations have been found to reduce external resistance, and although not bound by theory, it is thought to lower the barrier height between the semiconductor material grown at blockand subsequently deposited contact metallization.

The semiconductor material grown at blockmay comprise one or more electrically active impurities that are either introduced in-situ during epitaxial growth, or implanted into the semiconductor material subsequent to material growth. In exemplary PMOS embodiments, p-type semiconductor material comprising at least one acceptor impurity species, such as boron, is grown at block. In advantageous embodiments, a greater concentration of p-type dopants are introduced at blockthan at block. Higher acceptor concentrations can also reduce external resistance by lowering the barrier height between the semiconductor material grown at blockand subsequently deposited contact metallization. In further embodiments, p-type semiconductor material comprising multiple acceptor impurity species, such as both boron and gallium, is grown at block. Although not bound by theory, gallium enrichment of SiGematerial may lower bandgap of the semiconductor material and/or improve band alignment with subsequently deposited contact metallization.

In the example illustrated in, materialhas been removed from within trenchbetween two adjacent channel stack structures. Source and drain material protrusionsare augmented with an additional layer of source and drain semiconductor material. An as-grown layer thickness of source and drain semiconductor materialmay vary, for example from 2-8 nm. The resulting layered source and drain material bodies have a total thickness T, which is greater than thickness T, and significantly greater than channel structure thickness T, as introduced above. Although thickness Tmay vary with implementation, in exemplary embodiments, thickness Tis at least 30% larger than channel structure thickness Tand may be 50% larger, or more. Although source and drain materialmay unify individual source and drain material protrusionsinto a single body, in the illustrated embodiment individual source and drain material bodies remain vertically separated by an intervening non-zero space S.

Although the composition of source and drain semiconductor materialmay vary with implementation, in some PMOS embodiments source and drain semiconductor materialis a silicon-germanium alloy (SiGe) comprising over 50 at. % germanium. In some embodiments where source and drain material protrusionscomprise 20-40 at. % germanium, source and drain materialcomprises 60-80 at. % germanium.

Acceptor concentrations within source and drain semiconductor materialmay similarly vary, for example according to the dopant species and implementation. In some PMOS embodiments where source and drain material protrusionshave a boron concentration below 4-5e20 atoms/cmrange, source and drain semiconductor materialhas a boron concentration in the range of 2-4e21 atoms/cm, or more. In some further embodiments, source and drain semiconductor materialalso comprises gallium, for example as a co-dopant countering any loss of boron solubility that may occur with higher concentrations of germanium. Although the amount gallium enrichment may vary, in some exemplary embodiments where gallium is substantially absent from source and drain material protrusionsthe concentration of gallium within source and drain semiconductor materialis in the range of 1-8e19 atoms/cm.

Although the layered source and drain semiconductor bodies in accordance with embodiments herein may undergo some amount of atomic diffusion, higher concentrations of p-type impurities within the outer layer of source and drain semiconductor materialmay be distinguished from lower concentrations within source and drain material protrusionswith one or more analysis techniques, such as atom probe tomography (APT), or STEM-EELS (electron energy-loss spectroscopy)/EDS (energy dispersive x-ray spectroscopy).

At the stage of transistor fabrication illustrated inand, sacrificial channel stack materialhas been replaced with gate electrode material. Where gate electrode material(and underlying gate insulator) was formed prior to formation of source and drain semiconductor material, source and drain semiconductor materialmay retain a highest concentration of impurities in preparation for interfacing with metallization.

Gate electrode materialis separated from channel structuresby a gate insulator (not depicted) cladding channel structures, for example to provide gate-all-around control of channel conductivity. In the illustrated embodiment, the gate electrode materialis a single homogeneous material. For such embodiments, the single homogenous material is a single workfunction metal. In some PMOS embodiments, gate electrode materialincludes a p-type workfunction metal, which may have a workfunction between about 4.9 eV and about 5.2 eV, for example. Suitable p-type materials include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel titanium, tungsten, conductive metal nitrides (e.g., TiN, WN), and conductive metal oxides (e.g., ruthenium oxide). Although not illustrated in, orB, a compositionally distinct gate fill metal may be over the workfunction metal where a thickness of the workfunction metal is insufficient to occupy the topography allocated to gate structure. For a CFET transistor stack structures, gate electrode materialmay include both a p-type workfunction metal and an n-type workfunction metal as embodiments are not limited in this respect.

Gate insulator between gate electrode materialand channel structuresmay vary with implementation. In accordance with some exemplary embodiments, a high-k material (with a bulk relative permittivity greater than 9) is between gate electrode materialand channel structures. One exemplary high-k material is metal oxide (MIOx). Examples include a metal oxide comprising predominantly aluminum (e.g., AlOx), a metal oxide comprising predominantly magnesium (e.g., MgO), a metal oxide comprising predominantly lanthanum (e.g., LaO), a metal oxide comprising predominantly hafnium (e.g., HfO) or predominantly zirconium (e.g., ZrO). In other examples, the high-k material is an alloy metal oxide comprising significant portions of two or more metals (e.g., HfAlO, or HfZrO).

Returning to, methodscontinue at blockwhere metallization is deposited directly upon the source and drain material bodies as source and drain (contact) terminal metallization. The metallization deposited at blockadvantageously spans the stack of source and drain material bodies, filling in any spaces between the bodies and forming a larger semiconductor-metal interface area than would otherwise be possible if the source and drain material bodies had been unified into a single body. Metallization may be deposited at blockimmediately following the source drain material growth at block, ensuring minimal loss of impurity dopants. Metallization may comprise one or more layers of a substantially pure (elemental) metal, or an alloy of one or more metals. In some embodiments, metallization comprising titanium (Ti) is deposited at block. In some further embodiments, one or more layers of a metal other than Ti, such as, but not limited to tungsten (W), molybdenum (Mo), niobium (Nb), tantalum (Ta), and/or rhenium (Re) is deposited as a first layer followed by one or more additional layers of metallization (e.g., Ti, nickel, aluminum, copper, cobalt, etc.).

In some embodiments, blockcomprises a formation of metal silicide through a solid-state reaction at the interface of metallization deposited at blockand the semiconductor material deposited at block. Silicidation may be promoted with a thermal anneal performed at elevated temperatures subsequent to the deposition of metal.

Following block, methodsend at outputwhere a stacked transistor structure may be completed according to any known techniques and architectures. The transistor structures may be further interconnected into an IC through any known backend of line (BEOL) interconnect fabrication processes as embodiments are not limited in this respect.

In the example illustrated inand, transistor structuresandare illustrated as substantially complete three terminal devices comprising source and drain metallization. In the illustrated example, metallizationsubstantially fills trenchand is in contact with each source and drain material body stacked adjacent to the stack of channel structures. Metallizationtherefore forms a vertical interconnect between individual ones of the plurality of source drain material bodies, and more specifically contacts source and drain semiconductor material. Although not depicted, metallizationmay comprise a liner of a first metal or first metal alloy, which makes direct contact with each of the plurality of source drain material bodies. Over the liner, a fill metal may at least partially fill any remaining gap or trench between adjacent transistor stack structures,.

In some embodiments, metallizationin contact with source and drain semiconductor materialis primarily Ti and may be substantially pure Ti. In some further embodiments, a layer of metallizationin direct contact with source and drain semiconductor materialis other than Ti, such as predominantly W, Mo, Nb, Ta, or Re. For exemplary embodiments where source and drain semiconductor materialhas a layer thickness of at least 2 nm and comprises Ga, the Ga concentration is at least 1e19 atoms/cmwithin 1-3 nm of the interface with metallization. In further embodiments where no Ga was deliberately introduced into source and drain semiconductor material protrusions, the concentration of Ga beyond 4 nm of the interface with the metallizationis less than 1e18 atoms/cm.

The transistor stack structures,, and methods of forming such structures described herein, may be integrated into a wide variety of ICs and computing systems that include such ICs.illustrates a system in which a mobile computing platformand/or a data server machineincludes an IC diehaving a memory and/or microprocessor IC with transistors comprising stacked source and/or drain material bodies, for example in accordance with some embodiments described elsewhere herein. The server machinemay be any commercial server, for example including any number of high-performance computing platforms within a rack and networked together for electronic data processing. The mobile computing platformmay be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platformmay be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level integrated system, and a battery.

Whether disposed within the integrated systemillustrated in the expanded view, or as a stand-alone packaged chip within the server machine, IC diemay include memory circuitry (e.g., RAM), and/or a logic circuitry (e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like). At least one of these circuitries comprises one or more transistor structures including a stack of source/drain material bodies, for example in accordance with some embodiments described elsewhere herein. IC diemay be further coupled to a board or package substratethat further hosts one or more additional ICs, such as power management ICand radio frequency IC. RFICmay have an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.