Backside-Patterned Fin Isolation Structures Between Semiconductor Devices

As integrated circuits continue to scale downward in size, a number of challenges arise. For instance, reducing the size of memory and logic cells within the interconnect structure is becoming increasingly more difficult, as is reducing device spacing at the device layer. Maintaining a certain level of quality among the various transistor elements can be a challenge due to the number of different fabrication processes they may be subjected to. Accordingly, there remain a number of non-trivial challenges with respect to forming such high-density semiconductor devices.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. As will be further appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and/or rounded corners), and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used.

Techniques are provided herein to form an integrated circuit having fin isolation structures patterned from the backside of the structure. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells, such as those cells that use finFETs or gate-all-around transistors (e.g., ribbonFETs and nanowire FETs) or forksheet transistors. In one such example, FETs (field effect transistors) each includes semiconductor material extending colinearly in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. The semiconductor material of each FET may be a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be). A fin isolation structure may extend along the second direction between the FETs to provide electrical isolation between the FETs. The fin isolation structure may include one or more dielectric materials that are deposited within a trench and patterned from the backside of the structure, which helps avoid damaging topside features of the FETs. According to some embodiments, N-channel FETs are separated by a fin isolation structure having a high-k dielectric liner and a low-k dielectric fill, and P-channel FETs are separated by a fin isolation structure having a high-k dielectric liner and a dielectric fill that includes both high-k and low-k dielectric materials. The different dielectric materials used between N-channel and P-channel devices impart different strain on the devices to improve performance. Numerous variations and embodiments will be apparent in light of this disclosure.

As previously noted above, there remain a number of non-trivial challenges with respect to integrated circuit fabrication. In more detail, isolating semiconductor devices from one another is important to provide desired circuit and logic arrangements. Several different isolation structures and techniques are used to provide electrical isolation. One such structure is a fin isolation structure that electrically isolates different portions of a semiconductor fin. Since several devices can be formed along the length of a single fin, fin isolation structures can be used to isolate devices along the fin. The fin isolation structures may include dielectric material formed within a trench that cuts through a given fin and runs perpendicular to the length of the fin. However, many of the processes used to form the isolation structures can damage other topside semiconductor features, such as spacer structures, which leads to decreased device performance or inoperability.

Thus, and in accordance with an embodiment of the present disclosure, techniques are provided herein to pattern the dielectric material of the fin isolation structures form the backside of the substrate to avoid performing etching processes to the topside that may damage other transistor elements. In some embodiments, the fin isolation structures are formed by filling an opening between semiconductor devices with one or more dielectric materials. The opening may be a trench-like opening that cuts across the height of a fin (or the semiconductor material from the fin) in order to isolate semiconductor devices on either side of the opening. One or more of the dielectric materials within the opening may then be exposed and patterned from the backside of the structure to avoid damaging topside transistor features.

According to some embodiments, the dielectric material within the opening may be different depending on whether the adjacent semiconductor devices are n-channel devices or p-channel devices. In the case of n-channel devices, the fin isolation structure may include a high-k dielectric liner with a low-k dielectric fill along an entire height of the fin. In the case of p-channel devices, the fin isolation structure may include a high-k dielectric liner and a dielectric fill that includes both low-k and a high-k dielectric material. In some examples, the low-k dielectric material may be present near the top end of the fin isolation structure, above a topmost surface of the source or drain regions and/or above a topmost surface of the semiconductor region of the adjacent semiconductor devices. High-k dielectric materials may include dielectric materials with a dielectric constant of 6.0 or greater, such as silicon nitride, while low-k dielectric materials may include dielectric materials with a dielectric constant of less than 5.0, such as silicon dioxide. Using fin isolation structures with different dielectric material compositions can impart a different strain on the adjacent devices.

According to an embodiment, an integrated circuit includes a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region and a first gate structure extending in a second direction over the first semiconductor region, a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region and a second gate structure extending in the second direction over the second semiconductor region, and a dielectric structure extending in the second direction between the first source or drain region and the second source or drain region and extending in a third direction along an entire height of the first source or drain region and the second source or drain region. The second semiconductor region is aligned with the first semiconductor region along the first direction. The dielectric structure extends to a depth below a bottommost surface of the first and second source or drain regions.

According to another embodiment, an integrated circuit includes a first semiconductor region extending in a first direction from a first source or drain region and a first gate structure extending in a second direction over the first semiconductor region, a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region and a second gate structure extending in the second direction over the second semiconductor region, and a dielectric structure extending in the second direction between the first source or drain region and the second source or drain region and extending in a third direction along an entire height of the first source or drain region and the second source or drain region. The second semiconductor region is aligned with the first semiconductor region along the first direction. The dielectric structure includes a first dielectric material and a second dielectric material on the first dielectric material. The second dielectric material is a plug (body) of material above a topmost surface of the first source or drain region and the second source or drain region. The first dielectric material wraps around the second dielectric material and fills a region of the dielectric structure below the second dielectric material.

According to another embodiment, an electronic device includes a chip package having one or more dies. At least one of the one or more dies includes a first semiconductor region extending in a first direction from a first source or drain region and a first gate structure extending in a second direction over the first semiconductor region, a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region and a second gate structure extending in the second direction over the second semiconductor region, and a dielectric structure extending in the second direction between the first source or drain region and the second source or drain region, and extending in a third direction along an entire height of the first source or drain region and the second source or drain region. The second semiconductor region is aligned with the first semiconductor region along the first direction. The first and second source or drain regions each extend to a first depth below a bottommost surface of the first and second gate structures, and the dielectric structure extends to a second depth below the bottommost surface of the first and second gate structures. The second depth is greater than the first depth.

According to an embodiment, a method of forming an integrated circuit includes forming fins comprising semiconductor material where the fins extend above a substrate and each extend in line with one another along a first direction; forming a dielectric layer around a base portion of the fins; forming source or drain regions at the ends of each of the fins; forming a recess through a given fin, wherein the recess extends below a bottommost surface of the dielectric layer; forming a first dielectric material on the sidewalls of the recess; forming a second dielectric material on the first dielectric material within the recess, the first and second dielectric materials together forming a dielectric structure; forming gate electrodes extending over the semiconductor material of the fins in a second direction different from the first direction; removing a portion of the substrate from the backside and exposing a bottom surface of the dielectric structure; recessing or removing the second dielectric material from the backside to form a backside recess; and filling the backside recess with a third dielectric material.

The techniques can be used with any type of planar or non-planar transistors, including finFETs (sometimes called double-gate transistors, or tri-gate transistors), or nanowire and nanoribbon transistors (sometimes called gate-all-around transistors), or forksheet transistors, to name a few examples. The source and drain regions can be, for example, epitaxial regions that are deposited during an etch-and-replace source/drain forming process. The dopant-type in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented with a gate-first process or a gate-last process (sometimes called a replacement metal gate, or RMG, process), or any other gate formation process. Any number of semiconductor materials can be used in forming the transistors, such as group IV materials (e.g., silicon, germanium, silicon germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. For instance, in some example embodiments, such tools may indicate the presence of one or more fin isolation structures (e.g., dielectric walls) between semiconductor devices and extending in the same lengthwise direction as the gate structures, that also extend in a third direction (e.g., along the height of the devices) beneath a bottommost surface of the source or drain regions. In some examples, the fin isolation structures extend through an entire thickness of a base dielectric layer beneath the semiconductor devices (e.g., to a first backside interconnect layer). In some embodiments, such imaging tools may be used to observe the presence of a plug (body) of low-k dielectric material within a given fin isolation structure that is above a topmost surface of the source or drain regions or above a topmost surface of the semiconductor regions of the adjacent devices. In some such cases, the plug may appear to be laterally surrounded by a larger body of high-k dielectric material that may also be under the plug in some locations.

It should be readily understood that the meaning of “above” and “over” in the present disclosure should be interpreted in the broadest manner such that “above” and “over” not only mean “directly on” something but also include the meaning of over something with an intermediate feature or a layer therebetween. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A monolayer is a layer that consists of a single layer of atoms of a given material. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure, with the layer having a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A layer can be conformal to a given surface (whether flat or curvilinear) with a relatively uniform thickness across the entire layer.

Materials that are “compositionally different” or “compositionally distinct” as used herein refers to two materials that have different chemical compositions. This compositional difference may be, for instance, by virtue of an element that is in one material but not the other (e.g., SiGe is compositionally different than silicon), or by way of one material having all the same elements as a second material but at least one of those elements is intentionally provided at a different concentration in one material relative to the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different than from SiGe having 25 atomic percent germanium). In addition to such chemical composition diversity, the materials may also have distinct dopants (e.g., gallium and magnesium) or the same dopants but at differing concentrations. In still other embodiments, compositionally distinct materials may further refer to two materials that have different crystallographic orientations. For instance, (110) silicon is compositionally distinct or different from (100) silicon. Creating a stack of different orientations could be accomplished, for instance, with blanket wafer layer transfer. If two materials are elementally different, then one of the material has an element that is not in the other material.

is a cross-section view taken through semiconductor devicesalong a ‘fin’ direction that illustrates the semiconductor bodies extending between source or drain regions of each of the semiconductor devices, in accordance with an embodiment of the present disclosure.illustrates a cross-section view taken through different semiconductor deviceson the same die as semiconductor devices. Semiconductor devicesmay be further along the same fin as semiconductor devices, or may be part of a different fin extending parallel to the fin of semiconductor devices. Each of the semiconductor devices may be, for instance, non-planar metal oxide semiconductor (MOS) transistors, such as tri-gate (e.g., finFET) or gate-all-around (GAA) transistors, although other transistor topologies and types could also benefit from the techniques provided herein. The examples herein illustrate semiconductor devices with a GAA structure (e.g., having nanoribbons, nanowires, or nanosheets that extend between source and drain regions). Other examples may have a forksheet structure having a p-type device and an n-type device separated by a dielectric spine or structure. According to some embodiments, semiconductor devicesare p-channel devices (e.g., PMOS) and semiconductor devicesare n-channel devices (e.g., NMOS).

The semiconductor material used in each of the semiconductor devices may be formed from or on a semiconductor substrate. According to some embodiments, the substrate is removed following the completion of all topside processing and is replaced with a base dielectric structure. Base dielectric structuremay represent any number of dielectric layers and/or materials. In some examples, base dielectric structureincludes one or more layers of silicon dioxide.

The one or more semiconductor regions of the devices may include fins that can be, for example, native to the substrate (formed from the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins can be formed of material deposited onto the substrate. In one such example case, a blanket layer of SiGe can be deposited onto a silicon substrate, and then patterned and etched to form a plurality of SiGe fins extending from that substrate. In still other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitates forming of nanowires and nanoribbons and nanosheets during a gate forming process where one type of the alternating layers is selectively etched away so as to liberate the other type of alternating layers within the channel region, so that a gate-all-around process or a forksheet gate process can then be carried out. Again, the alternating layers can be blanket deposited and then etched into fins or deposited into fin-shaped trenches, in some examples.

Each semiconductor deviceincludes one or more semiconductor regions (also called channel regions), such as one or more nanoribbonsextending between epitaxial source or drain regionsin the first direction. Similarly, each semiconductor deviceincludes one or more semiconductor nanoribbonsextending between epitaxial source or drain regionsin the first direction. First gate structuresextend over nanoribbonsof semiconductor devicesin a second direction (e.g., into and out of the page) to form the transistor gates of semiconductor devicesand second gate structuresextend over nanoribbonsof semiconductor devicesin the second direction to form the transistor gates of semiconductor devices.

Any of source or drain regions/may act as either a source region or a drain region, depending on the application and dopant profile. Any semiconductor materials suitable for source and drain regions can be used (e.g., group IV and group III-V semiconductor materials) for any of the illustrated source or drains regions/. In any such cases, the composition and doping of source or drain regionsandmay be the same or different, depending on the polarity of the transistors. In an example, semiconductor devicesare p-channel devices having a high concentration of p-type dopants in the associated source or drain regions, and semiconductor devicesare n-channel devices having a high concentration of n-type dopants in the associated source or drain regions. Example p-type dopants include boron and example n-type dopants include phosphorous or arsenic. Any number of source and drain configurations and materials can be used. In some examples, source or drain regionsinclude silicon germanium doped with boron and source or drain regionsinclude silicon doped with phosphorous.

The gate structures/may each include a gate electrode that is made up of a conductive fill and one or more metal workfunction layers, according to some embodiments. The gate structures/also include a gate dielectric that may represent any number of dielectric layers. The conductive fill may include any sufficiently conductive material such as a metal, metal alloy, or doped polysilicon. In some examples, the conductive fill includes tungsten (W), although other metals or conductive materials may be used, such as aluminum (Al), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or doped polysilicon. In some embodiments, semiconductor devicesare p-channel devices having gate structureswith one or more workfunction layers of molybdenum nitride (MoN). Other metal workfunction layers of p-channel devices can include tantalum nitride (TaN) and titanium nitride (TiN). In some embodiments, semiconductor devicesare n-channel devices having gate structureswith one or more workfunction layers of tungsten. Other metal workfunction layers of n-channel devices can include tantalum nitride (TaN).

The gate dielectric of each gate structure/may include any suitable gate dielectric material(s). In some embodiments, the gate dielectric includes a layer of native oxide material (e.g., silicon dioxide germanium dioxide, or SiGe oxide) on nanoribbons/, and a layer of high-k dielectric material (e.g., hafnium oxide or aluminum oxide) on the native oxide. According to some embodiments, spacer structuresand inner spacersare present along the sidewalls of gate structures/. Spacer structuresand inner spacersmay be any suitable dielectric material, such as silicon nitride, and provide separation between a given gate structure/and the adjacent source or drain region/. Inner spacersmay separate adjacent nanoribbons/from one another along a third direction (e.g., a vertical direction).

According to some embodiments, a dielectric fillmay be present over the source or drain regions/within the corresponding source/drain trenches of semiconductor devicesand. A top surface of dielectric fillmay be substantially co-planar with a top surface of spacer structures. Dielectric fillmay include any suitable dielectric material, such as silicon dioxide, in some examples.

According to some embodiments, conductive contactsare provided through dielectric filland contacting a top portion of source or drain regions/. Conductive contactscan include any suitable conductive material, such as tungsten, molybdenum, ruthenium, cobalt, or other metals. Conductive contactsmay be formed during the same metal deposition process(es) such that they all include the same conductive material.

According to some embodiments, semiconductor devicesare electrically isolated by a first fin isolation structureextending along the second direction between semiconductor devices, and semiconductor devicesare electrically isolated by a second fin isolation structureextending along the second direction between semiconductor devices. According to some embodiments, first fin isolation structureand second fin isolation structureare partially formed from the backside of the integrated circuit, such that bottom surfaces of first fin isolation structureand second fin isolation structureare substantially coplanar with a bottom surface of base dielectric structure. The backside processing of first fin isolation structureand second fin isolation structurealso results in both first fin isolation structureand second fin isolation structureextending below the bottommost surfaces of source or drain regions/. First fin isolation structureextends in the third direction along at least an entire height of the adjacent source or drain regions, and second fin isolation structureextends in the third direction along at least an entire height of the adjacent source or drain regions

According to some embodiments, first fin isolation structureincludes a first dielectric materialand a second dielectric material. First dielectric materialmay be a high-k dielectric material, such as silicon nitride, while second dielectric materialis a low-k dielectric material, such as silicon dioxide. According to some embodiments, first dielectric materialfills a region of first fin isolation structurethat is below second dielectric materialand is also along the sides of second dielectric material. In this way, second dielectric materialacts like a plug of dielectric material at the top end of first fin isolation structure. In some examples, a top surface of second dielectric materialis substantially coplanar with a top surface of first fin isolation structure. A bottommost surface of second dielectric materialmay be higher than a topmost surface of the adjacent source or drain regionsor higher than a topmost surface of nanoribbons. According to some embodiments, the dielectric material arrangement of first fin isolation structureimparts a first beneficial strain on the adjacent p-channel semiconductor devices.

According to some embodiments, second fin isolation structureincludes a dielectric linerand a dielectric fill. Dielectric linermay be a high-k dielectric material, such as silicon nitride, while dielectric fillis a low-k dielectric material, such as silicon dioxide. According to some embodiments, dielectric linerextends along the sidewalls of second fin isolation structureand dielectric filloccupies a remaining volume of second fin isolation structure. According to some embodiments, dielectric lineris also a part of first dielectric material. Dielectric linermay have the same material composition as first dielectric material, and dielectric fillmay have the same material composition as second dielectric material. According to some embodiments, the dielectric material arrangement of second fin isolation structureimparts a second beneficial strain on the adjacent n-channel semiconductor devices. The second strain is different from the first strain imparted by first fin isolation structureon the adjacent p-channel semiconductor devices.

include cross-sectional views that collectively illustrate an example process for forming an integrated circuit configured with backside-patterned fin isolation structures, in accordance with an embodiment of the present disclosure.represent a similar cross-sectional view as that ofacross a series of semiconductor devices, whilerepresent a similar cross-sectional view as that ofacross a series of different semiconductor devices. Each set of figures sharing the same letter shows an example structure that results from the process flow up to that point in time, so the depicted structure evolves as the process flow continues, culminating in the structure shown in, which is similar to the structure shown in. Such a structure may be part of an overall integrated circuit (e.g., such as a processor or memory chip) that includes, for example, digital logic cells and/or memory cells and analog mixed signal circuitry. Thus, the illustrated integrated circuit structure may be part of a larger integrated circuit that includes other integrated circuitry not depicted. Example materials and process parameters are given, but other materials and process parameters may be used as well, as will be appreciated in light of this disclosure.

each illustrates a cross-sectional view taken through a substratehaving a series of material layers formed over substrate, according to an embodiment of the present disclosure. Alternating material layers may be deposited over substrateincluding sacrificial layersalternating with semiconductor layers. The alternating layers are used to form GAA transistor structures. Any number of alternating sacrificial layersand semiconductor layersmay be deposited over substrate.

Substratecan be, for example, a bulk substrate including group IV semiconductor material (such as silicon, germanium, or SiGe), group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and/or any other suitable material upon which transistors can be formed. Alternatively, substratecan be a semiconductor-on-insulator substrate having a desired semiconductor layer over a buried insulator layer (e.g., silicon over silicon dioxide). Alternatively, substratecan be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers indium gallium arsenide and indium phosphide). Any number of substrates can be used.

According to some embodiments, semiconductor layershave a different material composition than sacrificial layers. In some embodiments, semiconductor layersinclude a semiconductor material suitable for use as a nanoribbon such as silicon (Si), SiGe, germanium, or III-V materials like indium phosphide (InP) or gallium arsenide (GaAs). Sacrificial layersinclude a material that can be selectively removed relative to semiconductor layers. In some examples, for instance, semiconductor layersare silicon and sacrificial layersare SiGe, or vice-versa. In some other examples where SiGe is used in each of semiconductor layersand in sacrificial layers, the germanium concentration is different between semiconductor layersand sacrificial layers, so as to allow for etch selectivity. For example, semiconductor layersmay include a higher germanium content compared to sacrificial layers.

While dimensions can vary from one example embodiment to the next, the thickness of each semiconductor layermay be between about 5 nm and about 20 nm, in some examples. In some embodiments, the thickness of each semiconductor layeris substantially the same (e.g., within 1-2 nm). The thickness of each of sacrificial layersmay be about the same as the thickness of each semiconductor layer(e.g., about 5-20 nm). Each of semiconductor layersand sacrificial layersmay be deposited using any material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), or epitaxial growth.

depict the cross-section views of the structure shown in, respectively, following the formation of a cap layerand the subsequent formation of fins beneath cap layer, according to an embodiment. Cap layermay be any suitable hard mask material such as a carbon hard mask (CHM) or silicon nitride. Cap layeris patterned into rows to form corresponding rows of fins from the alternating layer stack of sacrificial layersand semiconductor layers. Cap layerextends along the top of each fin in a first direction. In some embodiments,illustrate different portions of the same fin (e.g., patterned under the same strip of cap layer). In some embodiments,illustrate portions of different parallel fins (e.g., under different parallel strips of cap layer).

According to some embodiments, an anisotropic etching process through the layer stack continues into at least a portion of substrate. Portions of substratebeneath the fins are not etched and yield subfin regions. The etched portions of substratethat are not under the fins may be filled with a dielectric fill that acts as shallow trench isolation (STI) between adjacent fins. The dielectric fill is not shown in these cross-sections as it extends in the first direction along the sides of subfin regionsthat are into and out of the page. The dielectric fill may be any suitable dielectric material such as silicon dioxide. The subfin regionsrepresent remaining portions of substrateflanked by the dielectric fill, according to some embodiments.

depict cross-section views of the structures shown infollowing the formation of sacrificial gatesand spacer structures, according to some embodiments. A gate masking layer may first be patterned in strips that extend orthogonally across each of the fins (e.g., in a second direction) in order to form corresponding sacrificial gatesin strips beneath the gate masking layers. Afterwards, the gate masking layers may be removed or may remain as a cap layer above each sacrificial gate. According to some embodiments, the sacrificial gate material is removed in all areas not protected by the gate masking layers. Sacrificial gatemay be any suitable material that can be selectively removed without damaging the semiconductor material of the fins. In some examples, sacrificial gateincludes polysilicon.

According to some embodiments, spacer structuresare formed along the sidewalls of sacrificial gates. Spacer structuresmay be conformally deposited (e.g., CVD or ALD) and then etched back or otherwise removed (e.g., via anisotropic or directional etch) from horizontal surfaces, such that spacer structuresremain mostly only on sidewalls of any exposed structures. The width of spacer structures(along the first direction) may vary from one example to the next, but in some cases is in the range of 3 nm to 20 nm. According to some embodiments, spacer structuresmay be any suitable dielectric material, such as silicon nitride, silicon carbon nitride, or silicon oxycarbonitride. In one such embodiment, spacer structurescomprise a nitride and the dielectric fill adjacent to subfin regionscomprises an oxide, so as to provide a degree of etch selectivity during final gate processing.

depict cross-section views of the structures shown infollowing the removal of exposed portions of the fins not protected by sacrificial gatesand spacer structures, according to some embodiments. The exposed fin portions may be removed using any anisotropic etching process, such as reactive ion etching (RIE) or other directional etch process. The removal of the exposed fin portions creates source or drain trenches that alternate with gate trenches (currently filled with sacrificial gates) along the first direction, according to some embodiments. In some embodiments, at least a portion of subfin regionsis also removed such that a top surface of subfin regionsis recessed below a top surface of the adjacent dielectric fill. The recessed area above subfin regionsmay be filled with one or more dielectric materials.

depict cross-section views of the structures shown infollowing the removal of portions of sacrificial layers, according to an embodiment of the present disclosure. An isotropic etching process may be used to selectively recess the exposed ends of each sacrificial layer(e.g., while etching comparatively little of semiconductor layers).

depict cross-section views of the structures shown infollowing the formation of internal spacers, according to an embodiment of the present disclosure. Internal spacersmay have a material composition that is similar to or the exact same as spacer structures. Accordingly, internal spacersmay be any suitable dielectric material that exhibits high etch selectively to semiconductor materials such as silicon and/or silicon germanium. Internal spacersmay be, for example, conformally deposited over the sides of the fin structure using a conformal deposition process like CVD or ALD and then etched back using an isotropic etching process to expose the ends of semiconductor layers. According to some embodiments, internal spacershave a similar width (e.g., along the first direction) to spacer structures.

depict cross-section views of the structure shown in, respectively, following the formation of first source or drain regionsand second source or drain regionswithin the source/drain trenches, according to some embodiments. Source or drain regions/may be formed in the areas that had been previously occupied by the exposed fins between spacer structures. According to some embodiments, source or drain regions/are epitaxially grown from the exposed semiconductor material at the ends of semiconductor layers. In some example embodiments, first source or drain regionsare p-channel source or drain regions (e.g., epitaxial silicon germanium with p-type dopants) and second source or drain regionsare n-channel source or drain regions (e.g., epitaxial silicon with n-type dopants).

According to some embodiments, a dielectric fillis provided over source or drain regions/. In some examples, dielectric filloccupies a remaining volume within the source/drain trenches around and over portions of source or drain regions/. Dielectric fillmay be any suitable dielectric material, such as silicon dioxide. In some examples, dielectric fillextends up to and planar with a top surface of spacer structures(e.g., following a polishing procedure).

depict cross-section views of the structure shown in, respectively, following the formation of fin isolation structuresand, according to some embodiments. A trench recess extending along the second direction between two semiconductor devices may first be formed along a gate trench (e.g., through sacrificial gateand the layer stack of semiconductor layersand sacrificial layersbetween spacer structures). The trench recess may be formed by etching through the noted materials using a suitable anisotropic etching process, such as reactive ion etching (RIE). The trench recess extends along at least an entire height of the adjacent source or drain regions/and, according to some embodiments, extends below a bottommost surface of the source or drain regions/, such as at least 25 nm, at least 50 nm, at least 75 nm, or at least 100 nm below the bottommost surface of the source or drain regions. In some examples, the trench recess extends below a bottom surface of the dielectric fill (e.g., indicated by the dashed line) adjacent to subfin regions.

According to some embodiments, any number of trench recesses are filled with one or more dielectric materials to form fin isolation structuresand. In an example, a dielectric lineris deposited along all exposed surfaces of the trench recesses followed by a dielectric filldeposited on dielectric liner. According to some embodiments, dielectric lineris a high-k dielectric material, such as silicon nitride, and dielectric fillis a low-k dielectric material, such as silicon dioxide. Dielectric linermay have a thickness between about 3 nm and about 8 nm, about 5 nm and about 10 nm, or between about 5 nm and about 20 nm. The top surface of fin isolation structuresandmay be polished to be substantially coplanar with a top surface of the adjacent spacer structures.

depict cross-section views of the structure shown in, respectively, following the removal of sacrificial gatesand sacrificial layers, according to some embodiments. In examples where gate masking layers are still present, they may be removed at this time. Once sacrificial gatesare removed, the remaining fin portions extending between spacer structuresare exposed.

In the example where the fins include alternating sacrificial layersand semiconductor layers, sacrificial layersare selectively removed to leave behind nanoribbonsextending between first source or drain regionsand nanoribbonsextending between second source or drain regions. Each vertical set of nanoribbons/represents the semiconductor region (also called channel region) of a different semiconductor device. It should be understood that nanoribbons/may also be nanowires or nanosheets. Sacrificial gatesand sacrificial layersmay be removed using the same isotropic etching process or different isotropic etching processes.

depict cross-section views of the structure shown in, respectively, following the formation of first gate structuresaround the suspended nanoribbonsand second gate structuresaround the suspended nanoribbons, according to an embodiment of the present disclosure. As noted above, gate structures/each include a gate dielectric and a gate electrode.

The gate dielectric may be conformally deposited around nanoribbons/using any suitable deposition process, such as ALD. The gate dielectric may include any suitable dielectric (such as silicon dioxide, and/or a high-k dielectric material). Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. According to some embodiments, the gate dielectric is hafnium oxide with a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). The gate dielectric may be a multilayer structure, in some examples. For instance, the gate dielectric may include a first layer on nanoribbons/, and a second layer on the first layer. The first layer can be, for instance, an oxide of the semiconductor layers (e.g., silicon dioxide) and the second layer can be a high-k dielectric material (e.g., hafnium oxide). In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k dielectric material is used. In some embodiments, the high-k material can be nitridized to improve its aging resistance.

The gate electrode may be deposited over the gate dielectric and can be any standard or proprietary conductive material that may include any number of gate cuts. In some embodiments, the gate electrode includes doped polysilicon, a metal, or a metal alloy. Example suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and carbides and nitrides thereof. The gate electrode may include, for instance, one or more workfunction layers, resistance-reducing layers, and/or barrier layers. In an example, first gate structuresinclude p-type workfunction materials such as, for example, titanium nitride. In an example, second gate structuresinclude n-type workfunction materials such as tungsten or titanium aluminum carbide.

According to some embodiments, source/drain contactsmay be formed through dielectric fillto contact the top surfaces of source or drain regions/. Contactsmay include any suitable conductive material, such as tungsten, cobalt, molybdenum, or ruthenium, for making electrical contact with the underlying source or drain regions/

depict cross-section views of the structure shown in, respectively, following the removal of a backside portion of substrate, according to some embodiments. Any number of polishing, grinding, or etching processes may be used to remove the bulk portion of substrate. According to some embodiments, substrateis removed until a bottom surface of fin isolation structuresandis exposed. Accordingly, a portion of substrateremains across the structure beneath subfin regionsand beneath the dielectric fill adjacent to subfin regions. As noted above, a bottom surface of the dielectric fill adjacent to subfin regionsis identified by the dashed line. The remaining portion of substratemay have a thickness between about 5 nm and about 20 nm, between 15 nm and about 30 nm, or greater than 30 nm.