Stacked Gate-All-Around Transistor and Forksheet Transistor

The present disclosure relates to semiconductors and transistors and, more specifically, to stacked field-effect transistors (FETs). Semiconductors, such as complementary metal-oxide-semiconductors (CMOS), are commonly used in computer chips and computer technology. These semiconductor chips/devices typically include transistor(s). Transistors are devices which may be used to switch or amplify electric current or voltage.

FETs use an electric field effect to control current flow within a semiconductor. FETs have three terminals-a source, a drain, and a gate. The source introduces/provides current to the transistor, the drain is the terminal that provides the output current, and the gate is used to control the current flow from the source to the drain. Specifically, FETs use the electric charge of their gates to affect and control the current flow through the channel.

Current flows using charge carriers that are either electrons or holes. Electron charge carriers are negatively charged particles (i.e., electrons) that carry charge and create an electric current. Hole charge carriers (referred to herein as holes) are positions on the FET channel that lack an electron (for instance, at positions of positive charge that is equal in magnitude to the negative charge of an electron and/or positions where an electron could or should be). These holes are positive charges, and they move in an opposite direction of electrons, in some instances. The electric charge and/or voltage of the FET gates is used to control the movements of the electrons and/or holes, which can then affect the current and charge being transmitted through the channel from the source to the drain.

One common type of FET is a nanosheet FET. Nanosheet FETs may have multiple nanosheets stacked (for example, vertically and/or horizontally) above/below each other. The nanosheets act as channels in the FET. In some instances, at least a portion of one or more sides of the nanosheet channels are surrounded by a gate material in nanosheet FETs.

The present disclosure provides a semiconductor structure, a system, and a method of forming a stacked transistor structure with a gate-all-around (GAA) transistor and a forksheet/dielectric bar. The semiconductor structure may include a set of stacked transistors. The set of stacked transistors may include a first transistor, where the first transistor includes a first gate having a gate-all-around (GAA) structure. The set of stacked transistors may also include a second transistor, where the second transistor has a gate structure different than a GAA structure. The set of stacked transistors may also include a dielectric bar.

The system may include a semiconductor structure. The semiconductor structure may include a set of stacked transistors. The set of stacked transistors may include a first transistor, where the first transistor includes a first one or more channels and a first gate having a gate-all-around (GAA) structure. The set of stacked transistors may also include a second transistor, where the second transistor includes a second one or more channels and a second gate, the second transistor having a gate structure different than a GAA structure. The set of stacked transistors may also include a dielectric bar.

The method may include forming a set of stacked nanosheets, the set of stacked nanosheets including top nanosheets and bottom nanosheets. The method may also include forming a dielectric bar, the dielectric bar including a first layer and a second layer, where the second layer is directly contacting the set of stacked nanosheets. The method may also include selectively recessing the second layer of the dielectric bar, resulting in a space between the top nanosheets and the dielectric bar. The method may also include depositing a first gate. The method may also include depositing a second gate, where the second gate surrounds all sides of the top nanosheets, resulting in a gate-all-around (GAA) structure for the second gate.

The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Aspects of the present disclosure relate to semiconductors and transistors and, more specifically, to stacked field-effect transistors (stacked FETs, also referred to as SFETs) with forksheets/dielectric bars and gate-all-around (GAA) transistors. While the present disclosure is not necessarily limited to such applications, various aspects of the disclosure may be appreciated through a discussion of various examples using this context.

Transistors, such as field-effect transistors (FETs), may be used within a system (for example, within a semiconductor structure) to switch or amplify electric current or voltage. FETs may have two typical configurations, N-channel FETs and P-channel FETs. N-channel FETs introduce (for example, through doping) an n-type impurity to the semiconductor material of the channel between the source and the drain, and P-channel FETs introduce a p-type impurity to the semiconductor material of the channel.

For n-type impurities, arsenic, phosphorous, or any other n-type material may be added to the silicon. N-type materials may have five electrons in their outer orbitals. When the n-type materials are combined with the silicon of the semiconductor, the fifth electron may not have anything to bond to and may freely move around, which may allow an electric current to flow through the silicon semiconductor channel. Because there are extra electrons from the n-type materials, the majority carriers/charge carriers for N-channel FETs are electrons.

In P-channel FETs, p-type impurities such as boron, gallium, etc., may be added to the silicon semiconductor(s) for the silicon doping. The p-type materials may have three electrons in their outer orbitals which, when added to silicon, may form holes (i.e., may lack electrons) in the valence bonds of the silicon atoms. Because there are holes in the valence bonds due to the p-type materials, the majority carriers/charge carriers for P-channel FETs are holes. An N-channel FET may be referred to herein as an NFET and a P-channel FET may be referred to herein as a PFET.

In some instances, it may be beneficial to have multiple FETs connected to each other. For example, in logic gate designs, an N-gate from an NFET may be electrically connected to a P-gate from a PFET in order to form an input for the logic gate. A logic gate may be a circuit with one or more inputs (for example, any number of inputs), but only one output. In some instances, for example, combining NFET and PFET in a logic gate design can eliminate large current leakage from VDD (a positive supply voltage) to ground in a static/non-switching period, as one of the transistors will be off which may prevent different shorts between VDD and ground. This design is conventionally referred to as a complementary metal-oxide-semiconductor (CMOS) logic design. Because of the benefits of combining NFET and PFET in a logic gate design, various logic designs may include NFET-PFET pairs.

As technology has advanced, it has become increasingly beneficial to have large amounts of technology and components in very small spaces. Reducing the size of the technology and components may be referred to herein as scaling. One method of scaling to help fit components in a small area, without reducing the capabilities of the components, is to stack transistors. Stacking transistors may increase the height of the semiconductor chip/semiconductor structure, but may reduce the area on the chip taken up by transistors. This may help allow for more components on the surface of a chip and/or may allow for a smaller chip, in some instances. For example, for logic gate designs, the connected NFET and PFET may be stacked on top of each other in order to have the benefit of the NFET-PFET pair (discussed above) while also saving space and reducing the area on the chip taken up by the NFET and PFET.

However, in conventional stacked FETs, it may be necessary and/or useful to have separation between various components of the transistors (for example, the contacts, interconnects, PFETs, NFETs, etc.) to prevent unwanted current and/or heat transfer between components. This may make it difficult for scaling and reducing the size of semiconductors/devices. For example, there may be a necessary physical separation/distance needed between an NFET and a PFET in order to help prevent unwanted current and/or heat transfer between the NFET and PFET, device shorts, etc.

In some instances, forksheets (i.e., isolation bars), also referred to herein as dielectric bars, may help create electrical and/or current separation between various components (for example, contacts, interconnects, PFETs, NFETs, etc.) of a semiconductor and/or device while also reducing the physical distance/space needed between components. A forksheet/dielectric bar may help prevent current and/or heat transfer between components (such as the NFET and PFET) due to the material(s) of the dielectric bar. In addition, a dielectric bar may allow the various components to be closer in physical location (i.e., less physically separated), as the dielectric bar is separating/isolating the components, as opposed to using physical space to separate/isolate components.

However, when a device/semiconductor has dielectric bar(s), the transistors may conventionally have a tri-gate structure, as the stacked nanosheets are connected to the dielectric bar and only three sides of the nanosheets are exposed to the gate. A tri-gate structure is a transistor structure with gate(s) on/around three sides of the channel(s). Therefore, while a dielectric bar may improve scaling and reduce the space/distance between transistors, a dielectric bar may also reduce the amount of gates, as one sidewall of stacked nanosheets may be directly connected to and/or contacting the dielectric bar (instead of to the gate(s)). Only having a tri-gate structure (as opposed to a gate-all-around (GAA) structure) due to the forksheet may have a negative impact on PFETs in particular, as a tri-gate nanosheet transistor structure may have limited hole mobility, for instances, due to the elimination of one sidewall (for example, on the (110) surface) of the channel in (001)-Si orientation.

Additionally, conventional stacked transistor structures, such as those that include dielectric bar(s), may not allow for flexibility and/or variability in the structure (for example, the gate structure) for the top transistor and the bottom transistor. Put differently, conventional stacked transistor structures, and the methods for forming conventional stacked transistor structures, may not allow for different gate structures (such as dual work function metal (WFM) schemes) for the top transistor and the bottom transistor. This may be because conventional stacked transistors have a continuous path (e.g., a merged gate cavity) between the top and bottom transistors and the corresponding top and bottom gates. This may render it extremely difficult to change/remove/replace WFM operations for one FET without penalizing the other FET in the set of stacked transistors.

Below, above, on top of, etc. may refer to components (such as transistors) and their positions when looking at a cross-sectional view such as the views depicted in.

However, it is advantageous to have different gate structures for the top and bottom transistors. For instance, an NFET has electron charge carriers and a PFET has hole charge carriers, and different gate structures may have different impacts on electron mobility compared to hole mobility. The ability to have different gate structures for the different transistors (e.g., a top transistor and a bottom transistor) may allow for gate structures that can be tailored specifically for electron mobility and/or hole mobility, which may improve the functioning of the stacked transistors.

The present disclosure relates to semiconductors and transistors and, more specifically, to stacked FETs with dielectric bars. As discussed herein, dielectric bars can help improve scaling and decrease the size of the semiconductors and transistors, particularly the portions of the components (such as the base(s) of the components) attached to the substrate and/or chip, as dielectric bars may allow for components to be in closer proximity to each other due to the isolation created by the dielectric bars. Therefore, dielectric bar(s) may be desired to help decrease the size of a device and/or semiconductor chip and its components.

However, in conventional nanosheet transistors, the addition of a dielectric bar may cause the nanosheet transistor to have a tri-gate structure with only three sides of the nanosheets exposed to the gate material, which may negatively impact PFET structures, in particular, and PFET hole mobility. Electron mobility and NFET structures may not be negatively impacted by a tri-gate structure.

To help reduce and/or eliminate any issues, particularly in the PFET region of the stacked transistors, due to a dielectric bar, while also allowing for additional scaling by utilizing the dielectric bar, stacked FETs with dielectric bars and different gate structures are discussed herein. Different gate structures in the different transistors within a stacked FET set may also be referred to herein as different and/or dual WFM structures.

By utilizing different gate structures, the NFET portion of the stacked transistor set may include a gate structure, or WFM structure, that is beneficial for scaling as well as the functionality of the NFET, as electron charge carriers are not negatively affected by a tri-gate structure (as opposed to a gate-all-around (GAA) structure). However, the PFET portion of the stacked transistor set, which is negatively affected by a tri-gate structure, may instead have a different gate/WFM structure that is a gate-all-around (GAA structure). A GAA structure may surround the channels/nanosheets on all four sides (for example, when viewing from the cross-sections depicted in) which may help increase current flow (also referred to as drive current) as well as decrease current leakage. By utilizing different gate structures such as a PFET GAA structure and an NFET tri-gate structure (with a dielectric bar), the stacked transistors may still have the scaling benefits due to the dielectric bar and may also eliminate/reduce any negative impacts to the PFET portion (due to the use of the dielectric bar) by utilizing a GAA structure instead of a tri-gate structure, as the GAA structure has gate(s) surrounding all four sides/sidewalls (including on the (110) surface, in some instances) of the channel (for example, in (001)-Si orientation).

According to an aspect of the invention, there is provided a semiconductor structure, where the semiconductor structure includes a set of stacked transistors, where the set of stacked transistors includes a first transistor, where the first transistor includes a gate having a gate-all-around (GAA) structure, a second transistor, where the second transistor has a gate structure different than a GAA structure, and a dielectric bar. In some instances, the use of a dielectric bar can serve to create electrical and/or current separation between components of a semiconductor and can serve to reduce physical distance/space between components (i.e., improve scaling of the semiconductor structure). In some instances, a GAA structure can serve to improve hole mobility, which is especially beneficial to PFETs, and can help improve the functioning of the semiconductor structure.

In some embodiments, the second transistor includes a gate having a tri-gate structure. In some instances, the use of a tri-gate structure can serve to improve scaling and reduce physical distance/space between components, as the gate(s) may be connected to three sides of the channel(s)/nanosheet(s), which may open up the fourth side of the channel(s) to contact with other components, such as the dielectric bar.

In some embodiments, the first transistor is in a top region of the set of stacked transistors and the second transistor is in a bottom region of the set of stacked transistors. In some embodiments, the dielectric bar has a first width in the top region of the set of stacked transistors and a second width, different from the first width, in the bottom region of the set of stacked transistors. In some embodiments, the second width is wider than the first width. In some instances, the second wider width can allow for a tri-gate structure for the second transistor, which may help improve scaling of the semiconductor structure. In some instances, the wider width of the second width can also serve to prevent unwanted gate removal during any gate recessing and/or selective recessing processes.

In some embodiments, the dielectric bar includes a first layer and a second layer. In some embodiments, the first layer is in the top region and the bottom region and the second layer is only in the bottom region. In some embodiments, the second layer includes one or more different materials than the first layer. In some instances, the multiple layers of the dielectric bar can help with customization/tailoring of the dielectric bar and can help create different gate structures (including a GAA structure) for the first and second transistor.

In some embodiments, the first transistor has a first gate extension between one or more channels and the dielectric bar and a second gate extension, different from the first gate extension, between the one or more channels and a gate cut pillar. In some embodiments, the first gate extension is smaller than the second gate extension. In some instances, the smaller gate extension of the first gate extension can help with the formation/inclusion of a GAA structure, while also preventing too much gate extension in order to help with scaling of the semiconductor structure.

In some embodiments, the one or more channels are nanosheets. In some instances, nanosheet transistors and nanosheet channels may help with scaling and decreasing size of a semiconductor structure, as a plurality of nanosheets may be stacked on top of each other, resulting in multiple channels without taking up too much space on a surface of a semiconductor structure/chip.

According to an aspect of the invention, there is provided a system, where the system comprises a semiconductor structure, where the semiconductor structure includes a set of stacked transistors, where the set of stacked transistors includes a first transistor, where the first transistor includes a first one or more channels and a first gate having a gate-all-around (GAA) structure, a second transistor, where the second transistor includes a second one or more channels and a second gate, the second transistor having a gate structure different than a GAA structure, and a dielectric bar. In some instances, the use of a dielectric bar can serve to create electrical and/or current separation between components of a semiconductor and can serve to reduce physical distance/space between components (i.e., improve scaling of the semiconductor structure). In some instances, a GAA structure can serve to improve hole mobility, which is especially beneficial to PFETs, and can help improve the functioning of the semiconductor structure.

In some embodiments, the second gate has a tri-gate structure. In some instances, the use of a tri-gate structure can serve to improve scaling and reduce physical distance/space between components, as the gate(s) may be connected to three sides of the channel(s)/nanosheet(s), which may open up the fourth side of the channel(s) to contact with other components, such as the dielectric bar.

In some embodiments, the first one or more channels have a first width and the second one or more channels have a second width different than the first width. In some embodiments, the second width is greater than the first width. In some instances, a second width greater than the first width can help prevent short channel effects for the second one or more channels, due to the wider width, as the first one or more channels may already be protected from at least some short channel effects due to the GAA structure.

In some embodiments, the system further includes a contact via connected to the first gate and the second gate, and a contact connected to the first gate and an interconnect, where the second gate is connected to the interconnect through the contact via and the first gate. In some instances, the contact via can serve to help form a shared gate structure for the first gate and the second gate.

In some embodiments, the system further includes a contact via connected to the second gate, where the contact via is separated from the first gate, a first contact connected to the contact via and an interconnect, where the second gate is connected to the interconnect through the contact via and the first contact, and a second contact connected to the first gate and the interconnect. In some instances, the contact via can serve to help form an independent gate structure for the first gate and the second gate.

In some embodiments, the dielectric bar has a first width in a top region of the set of stacked transistors and a second width, different from the first width, in a bottom region of the set of stacked transistors. In some embodiments, the second width is wider than the first width. In some instances, the second wider width can allow for a tri-gate structure for the second transistor, which may help improve scaling of the semiconductor structure. In some instances, the wider width of the second width can also serve to prevent unwanted gate removal during any gate recessing and/or selective recessing processes.

According to an aspect of the invention, there is provided a method of forming a semiconductor structure, the method including forming a set of stacked nanosheets, the set of stacked nanosheets including top nanosheets and bottom nanosheets; forming a dielectric bar, the dielectric bar including a first layer and a second layer, where the second layer is directly contacting the set of stacked nanosheets; selectively recessing the second layer of the dielectric bar, resulting in a space between the top nanosheets and the dielectric bar; depositing a first gate; and depositing a second gate, where the second gate surrounds all sides of the top nanosheets, resulting in a gate-all-around (GAA) structure for the second gate. In some instances, the use of a dielectric bar can serve to create electrical and/or current separation between components of a semiconductor and can serve to reduce physical distance/space between components (i.e., improve scaling of the semiconductor structure). In some instances, a GAA structure can serve to improve hole mobility, which is especially beneficial to PFETs, and can help improve the functioning of the semiconductor structure.

Referring now to, a cross-sectional view of a semiconductor structurewith stacked transistors and a dielectric bar is depicted, according to some embodiments. The cross-sectional views depicted inare cross-section(s) in a gate region (for example, a cross-section along the PC and/or the gate) of a semiconductor structure.

Semiconductor structureincludes a backside interconnectwith backside contactsand(referred to collectively as backside contacts) directly connected to the backside interconnect, as well as a frontside interconnectwith frontside contacts,, and(referred to collectively as frontside contacts) directly connected to the frontside interconnect. In some instances, backside interconnectand frontside interconnectmay be back end of line (BEOL) interconnects. Frontside and backside, as referred to herein, may refer to the frontside and backside of a semiconductor die/chip. In some instances, contactsandmay be metal contacts, and may be a metal material such as cobalt (Co), tungsten (W), copper (Cu), ruthenium (Ru), etc. In some instances, as depicted in, backside contactsmay have direct contact with dielectric, gate(s), and gate cut pillar(s)and/or(referred to collectively as gate cut pillar(s)).

Frontside contactsmay be directly and/or indirectly connected to contact viasand(collectively contact vias). Contact viasconnect the bottom gatesto the frontside contacts(specifically, frontside contactsand) and the frontside interconnect. In some instances, as depicted in, the contact viasextend through the MDIand touch/have direct contact with the bottom gate(s). In some instances, contact viasmay be metal contacts, and may be a metal material such as Co, W, Cu, Ru, etc.depicts two exemplary types of gate connections, independent gates/connections and dependent gates/connections. Specifically,depicts an example of independent gates for stacked transistors, and shared gates for stacked transistors.

Specifically, for stacked transistors, contact viais directly connected to bottom gateand to contact, creating a connection between bottom gateand frontside interconnect. However, contact viahas no direct connection to top gate, and instead contact viais separated from top gateby gate cut pillar(also referred to as CT pillar). Because contact viahas no direct connection to top gate, top gateand bottom gateare not connected through contact via, and are independent gates. Top gateis connected to frontside interconnectthrough frontside contact

For stacked transistors, contact viais directly connected to both top gateand bottom gate. Therefore, contact viaconnects bottom gateto top gate, resulting in shared gates (and). Top gateis connected to frontside interconnectthrough frontside contactand, due to contact viaconnecting bottom gateto top gate, bottom gateis connected to frontside interconnectthrough its shared gate connection to top gateand the connection between top gateand frontside contact. This is referred to herein as a shared gate structure.

Althoughdepicts stacked transistorshaving independent gates and stacked transistorshaving shared gates, semiconductor structuremay include any combination of shared and/or independent gates. For example, stacked transistorsandmay both have shared gates, stacked transistorsandmay both have independent gates, stacked transistorsmay have shared gates and stacked transistorsmay have independent gates, etc.

Semiconductor structuremay also include a wafer(for example, a handler wafer) on top of (when viewing from the cross-section depicted in) the frontside interconnect, as well as a wafer/substrateon top of the backside interconnect. Semiconductor structurefurther includes various dielectrics, including dielectricand dielectric. In some instances, dielectricis shallow trench isolation (STI), and may help prevent current leakage and/or heat transfer between various components of the semiconductor structure. In some instances, dielectricand dielectricmay be dielectric materials such as silicon nitride (SiN), silicon dioxide (SiO), other oxide(s), silicoboron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon carbide (SiC), silicon oxycarbide (SiOC), etc. In some instances, dielectricand dielectricmay be the same material(s). In some instances, dielectricand dielectricmay be different materials.

As depicted in, semiconductor structureincludes two sets of stacked transistors, stacked transistorsand stacked transistors, separated by dielectric barsand(referred to collectively as dielectric bar). Each set of stacked transistorsandinclude a top transistorand a bottom transistor. Although semiconductor structuredepicts four transistors (a topand bottomtransistor for stacked transistors, and a topand bottomtransistor for stacked transistors), semiconductor structuremay include any number of transistors. In some instances, each transistor includes stacked nanosheetsand/or.depicts the nanosheets that make up the set of stacked transistorsas nanosheetsand the nanosheets that make up the set of stacked transistorsas nanosheets, however the nanosheets may also be referred to collectively as nanosheets. In some instances, the nanosheetsmay include silicon (Si) (or silicon compound) materials.

In some instances, the nanosheetsof the top transistors(also referred to as top nanosheets) may be separated from the nanosheetsof the bottom transistors(also referred to as bottom nanosheets) by middle dielectric isolation (MDI)and. MDImay correspond to stacked transistorsand MDImay correspond to stacked transistors, and MDIandmay be referred to collectively as MDI, in some instances. In some instances, MDImay be dielectric materials such as SiN, SiO, other oxide(s), SiBCN, SiOCN, SiC, SiOC, etc.

Semiconductor structureincludes gatesand(collectively gates) for the top transistorsand gatesand(collectively gates) for the bottom transistorsin the stacked transistor setsand. The gatesandmay surround a plurality of sides of the corresponding nanosheets, discussed further herein. In some instances, as depicted in, gates(for the top transistors) are gate-all-around (GAA) structures, and are in direct contact with all sides of the corresponding nanosheets. For example, when viewing from the cross-section depicted in, gatesare in contact with all four sides of the corresponding nanosheets. In some instances, the top transistorsin the sets of stacked nanosheetsandare PFETs. As discussed herein, a tri-gate structure can have a negative impact on PFETs in particular due to limited hole mobility. However, a GAA may not have the same negative impacts on PFETs and may instead improve hole mobility and the functioning of PFETs due to the additional contact between the gate(s)and the corresponding nanosheets.

As discussed herein, a dielectric bar (such as dielectric bar) may help improve scaling and reduce the space/distance between transistors (such as stacked transistorsand). A tri-gate structure may help further improve scaling and reduce spacing/distance between transistors, as the nanosheets may be in direct contact with the dielectric bar in a tri-gate structure. In some instances, as depicted in, gatesare tri-gate structures, and are in direct contact with three sides (for example, when viewing from the cross-section depicted in) of the corresponding nanosheets. By utilizing a tri-gate structure, the corresponding nanosheets(for instance, the nanosheetsfor the bottom transistors) are in direct contact with the dielectric bar, therefore helping decrease spacing/distance between the nanosheets.

In some instances, as depicted in, dielectric barmay include a first portion/layerand second portion/layer(s). The first layerof the dielectric barmay extend along both the topand bottomtransistors and may help separate stacked transistorsfrom stacked transistors(and vice versa). Put differently, the first layerof the dielectric barmay be in both the PFET region (for example, the top transistorregion) and NFET region (for example, the bottom transistorregion) of the stacked transistorsand. However, as depicted in, the second layer(s)of the dielectric barmay only separate the NFETs (for example, bottom transistors) from each other and may only be in an NFET region of the stacked transistor structure. In some instances, layerof the dielectric bar may be described as being part of both the topand bottomtransistor portions of the semiconductor structure, and layersmay be described as being part of/in a bottomtransistor portion of the semiconductor structure. In some instances, although layer(s)are depicted inas being on either side of layer(and, in some instances, may not be a continuous component but instead a plurality of components), layersmay be referred to herein as layerand/or second layer