Polishing Pad with Heat Dissipation Pattern

Semiconductor or integrated circuit (IC) devices are constructed using complex fabrication processes that form a plurality of different layers on top of one another. Many of the layers are patterned using photolithography, in which a light sensitive photoresist material is selectively exposed to light. For example, photolithography is used to define back-end metallization layers that are formed on top of one another. To ensure that the metallization layers are formed with a good structural definition, the patterned light must be properly focused. To properly focus the pattered light, a workpiece must be substantially planar to avoid depth of focus problems.

Chemical mechanical polishing (CMP) is a widely used process by which both chemical and mechanical forces are used to globally planarize a semiconductor workpiece. The planarization prepares the workpiece for the formation of a subsequent layer. A typical CMP tool comprises a rotating platen covered by a polishing pad. A slurry distribution system is configured to provide a polishing mixture, having chemical and abrasive components, to the polishing pad. A workpiece is then brought into contact with the rotating polishing pad to planarize the workpiece. CMP is a favored process because it achieves global planarization across the entire wafer surface. The CMP process polishes and removes materials from the wafer, and works on multi-material surfaces. Furthermore, the CMP process avoids the use of hazardous gasses, and/or is usually a low-cost process.

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting.

For the sake of brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the fabrication of semiconductor devices are well-known and so, in the interest of brevity, many conventional processes will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. As will be readily apparent to those skilled in the art upon a complete reading of the disclosure, the structures disclosed herein may be employed with a variety of technologies, and may be incorporated into a variety of semiconductor devices and products. Further, it is noted that semiconductor device structures include a varying number of components and that single components shown in the illustrations may be representative of multiple components.

Furthermore, spatially relative terms, such as “over”, “overlying”, “above”, “upper”, “top”, “under”, “underlying”, “below”, “lower”, “bottom”, and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. When a spatially relative term, such as those listed above, is used to describe a first element with respect to a second element, the first element may be directly on the other element, or intervening elements or layers may be present. When an element or layer is referred to as being “on” another element or layer, it is directly on and in contact with the other element or layer.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

is a schematic view of a Chemical Mechanical Polishing (CMP) device or tool. The toolis configured for performing a CMP process on a wafer in a semiconductor manufacturing process. The CMP toolmay include a wafer transportation unit, a cleaning unit, and a polishing unit. Typically, the wafer transportation unittransports a wafer to the polishing unit, where the wafer is polished. Thereafter, the wafer transportation unittransports the wafer to the cleaning unit, wherein the wafer is cleaned.

As shown, a polishing unitmay include four polish locations or moduleswhere the unitmay perform a CMP operation on a wafer. For example, the polishing unitmay include a first main polishing module, a second main polishing module, a first chemical buff module, and a second chemical buff module. In certain embodiments, during operation of the polishing tool, a wafer may be processed in succession by each module. In certain embodiments, during operation of the polishing tool, a first wafer may be processed by the first main polishing moduleand then by the first chemical buff modulewhile a second wafer may be processed by the second main polishing module, and then by the second chemical buff module. Whileillustrates four polishing modules, any suitable number of polishing modulesmay be employed.

is a schematic view of a Chemical Mechanical Polishing (CMP) polishing module. The moduleis configured for performing a CMP process on a waferin a semiconductor manufacturing process. As shown, the moduleincludes a polishing pad, a platen, a platen motor, and a wafer holder assembly, in accordance with some embodiments. The elements of the polishing modulecan be added to or omitted, and the disclosure should not be limited by the embodiments.

The platenis configured to receive and rotate the polishing padabout a center axis. In some embodiments, the platenis circular in shape. The diameter of the platenlies in a range that is substantially larger than the diameter of a waferto be polished.

The platen motorrotates the platenabout the axis. The platen motormay be electrically connected to a control module in the CMP tool and may be actuated and operated by the control module.

In an embodiment, the polishing padis fixed onto the platen. The polishing padmay be a consumable item used in a semiconductor wafer fabrication process. A polishing padmay be a hard, incompressible pad or a soft pad. For oxide polishing, hard and stiffer pads are generally used to achieve planarity. Softer pads are generally used in other polishing processes to achieve improved uniformity and a smooth surface. Hard pad and soft pad components may also be combined in an arrangement for customized applications.

In certain embodiments, the polishing padmay be formed by three-dimensional printing with desired portions formed from a material having a higher thermal conductivity and desired portions formed from material having a lower thermal conductivity, or formed with other desired attributes.

The wafer holder assemblyis used to support the wafer. In some embodiments, the wafer holder assemblymay include a shaft with a driving motor (not shown), a carrier head, and a retention ring. The driving motor may be configured to control rotational movement of the carrier headand retention ringabout a rotation axis. The rotation axisis different from the rotation axis. In some embodiments, the driving motor is an electric motor which converts electrical energy into mechanical energy for driving the rotation of the carrier headand retention ring. In some embodiments, the carrier headand retention ringare driven to rotate about the rotation axisby an external force (e.g., frictional force generated between the polishing padand the wafer).

Embodiments herein involve chemical mechanical polishing (CMP) processes and CMP tools such as the tool of. CMP is a method of planarizing or flattening out a semiconductor wafer surface by polishing away a thin layer of wafer surface. Traditionally, CMP polishing pads include a single material and are formed by a molding fabrication process. However, it has been determined that such unitary molded CMP polishing pads may cause unstable removal rates of material, particularly for temperature sensitive material. In temperature sensitive materials, the removal rate is sensitive to the temperature. Some materials, particularly metal film such as tungsten or copper, are temperature sensitive such that the removal rate increases with an increase in temperature.

Increasing friction between a polishing pad and a wafer being polished leads to higher temperature at the interface of the wafer and the polishing pad surface. A higher temperature may cause a faster chemical reaction between the CMP slurry and the material being polished.

Friction may vary across the surface of the wafer due to the structures thereon. As a result, when removing a temperature sensitive material during a polishing process, varying rates of removal may be encountered over the wafer.

Variation in the removal rate of a temperature sensitive material due to localized temperature differences leads to worse within wafer (WiW) uniformity. In the short term, poor within wafer uniformity may be counteracted by controlling the downforce (DF) setting modification of the CMP tool. Specifically, the downforce on each zone of the wafer may by tuned and differ during a polishing process. However, an unhealthy downforce application may result in an increase in defects on the wafer over the longer term.

In addition, large removal rate variation leads to worse within zone (WiZ) uniformity. Polishing of semiconductor wafers may be analyzed by zones within the wafer surface. For example, a central zone may be circular and include the center of the wafer to a radius of 40 mm. A next zone may be annular and include the area from a radius of 40 mm to a radius of 70 mm. A next zone may be annular and include the area from a radius of 70 mm to a radius of 95 mm. A next zone may be annular and include the area from a radius of 95 mm to a radius of 122 mm. A next zone may be annular and include the area from a radius of 122 mm to a radius of 138 mm. A next zone may be annular and include the area from a radius of 138 mm to a radius of 145 mm. A last zone may be annular and include the area from a radius of 145 mm to a radius of 150 mm, or to the edge of the wafer.

Variation in the removal rate of a temperature sensitive material due to localized temperature differences leads to worse within zone (WiZ) uniformity. While downforce may be tuned to improve within wafer uniformity, within zone thickness uniformity is difficult to control by downforce or other tool settings. Further, within zone uniformity increases in importance when shrinking integrated circuit devices.

As semiconductor technology node advances to five nanometers and beyond, standards for within wafer and within zone thickness uniformity are increasingly stringent. Poor thickness uniformity across a wafer can lead to pattern failure, thus impacting chip yield and electrical characteristics.

Herein, embodiments are provided to mitigate material-induced temperature variation and to better control within wafer thickness uniformity and within zone thickness uniformity during CMP. Certain embodiments use a combination of polishing pad materials to material-induced temperature variation. Certain embodiments use a polishing pad layout designs to achieve uniform temperature distribution across whole wafer. For example, certain embodiments include a polishing pad formed with materials having different thermal conductivities in an arrangement to form a polishing surface of the polishing pad with a desired heat dissipation pattern.

As a result, certain embodiments provide more uniform heat transfer on the polishing pad, allow for healthier down force settings on the CMP tool and lower defect risks, increase within wafer uniformity of planarized wafers, increase within zone uniformity of planarized wafers, and/or increase uniformity between planarized wafers, i.e., wafer-to-wafer (WtW) uniformity. With increased within wafer thickness uniformity and higher polish performance stability, chip yield and integrated circuit device performance may be sharply improved.

Certain embodiments provide a CMP polishing pad with pixel-level material and structural designs to improve heat distribution during polishing, thus increasing within-wafer (WiW) and within-zone (WiZ) uniformity for yield and electrical property improvement. Certain embodiments provide a temperature-controlled three-dimensional (3D) printed polishing pad.

Referring to, the structure of the wafer holder assemblyis shown more clearly. As shown, the carrier headhas a bottom surfaceand an outer perimeter. The retention ringhas an annular shape and is mounted on the outer perimeterof the carrier head. Further, the retention ringhas an inner surface, such as a cylindrical surface, and extends downward to a terminal surfaceat a distance from the bottom surfaceof the carrier head. As a result, a recess or pocketis defined by the wafer holder assembly, below the bottom surfaceof the head, above the terminal surfaceof the retention ring, and inside of the inner surfaceof the retention ring.

Whileillustrate the retention ringlocated outside the periphery of the carrier head, other designs are envisioned. For example, the carrier headmay be formed with an inner cylindrical wall surface and the retention ringmay be positioned inside of such wall surface. Further, a retention ring cushion may be positioned between the retention ringand the carrier headto cushion movement therebetween.

As further shown, the wafer holder assemblymay include a flexible membrane. Flexible membraneis used to provide a flat surface for securing a waferto the carrier head.

Though not shown, the wafer holder assemblymay further include a port or ports to the pocketfor applying a positive pressure to an internal surface of flexible membranein order to help maintain a flat surface for supporting waferand to evenly distribute pressure applied to the wafer.

Further, though not shown, the wafer holder assemblymay include a port or ports for applying a negative pressure to an external surface of flexible membranein order to hold the waferwith the wafer holder assembly. When the waferis to be released from the wafer holder assembly, such as following a polishing process, the negative pressure may be released or a positive pressure may be applied.

Thus, the wafer holder assemblyis configured pick up a wafer, transport the wafer, and hold the waferagainst polishing pad. Carrier headmay be capable of moving in a direction perpendicular to a polishing surface of polishing padin order to adjust a pressure applied to waferduring the polishing process. A membrane support structure may be positioned in the pocketto provide support for membraneduring the polishing process. Retention ringis used to reduce lateral movement of waferduring the polishing process. In order to reduce lateral movement of wafer, retention ringmay be pressed against polishing pad.

In, the wafer holder assemblyis moved in the direction of arrowtoward wafer. As shown waferis supported by a wafer tray. The retention ringof the wafer holder assemblymay be moved into contact with the wafer tray. Then, the membranemay be operated to contact the waferand draw the waferagainst the membrane, such as through the selective application of positive and negative pressure.

In, the wafer holder assemblyis lifted in the direction of arrow. As shown, the waferis removed from the wafer trayand is carried by the wafer holder assembly. With cross-reference to, the wafer holder assemblymay carry the waferto a polishing pad.

In, the wafer holder assemblyis moved in the direction of arrowtoward the polishing pad, and may be moved into contact with the polishing pad.

In, the wafer holder assemblyis in contact with the polishing padand may be rotated about axis, such as in the direction of arrow, during a polishing process. As shown, the retention ringmay contact the polishing padduring the polishing process. Further, the membraneand/or carrier headmay impart a desired pressure to the waferagainst the polishing pad.

Referring now to, a rotatable structureincluding a polishing padand platenis illustrated while supporting a wafer. The polishing padincludes a polishing surfaceand an opposite surfacethat is located on and supported by the platen. Likewise, the platenincludes a top surface, which supports the polishing pad, and an opposite surface.

In some embodiments, the polishing padis formed from pixels or grainsthat are fused during a three-dimensional printing process. Through use of three-dimensional printing, the thermal conductivity, i.e., K value, and other properties of the polishing padmay be controlled at a pixel level. Specifically each grain or material fraction can be manufactured by three-dimensional printing technology providing for pixel-level precision control.

Each grain may independently have a thermal conductivity K value of at least 0.01, at least 0.03, at least 0.05, at least 0.08, at least 0.1, at least 0.12, at least 0.15, at least 0.2, at least 0.25, at least 0.3, at least 0.35, at least 0.4, at least 0.45, at least 0.5, at least 0.6, at least 0.7, at least 0.8, at least 0.9, at least 1.0, at least 1.2, at least 1.5, at least 1.8, at least 2.0, at least 2.2, at least 2.5, at least 2.8, at least 3.0, at least 3.2, at least 3.5, at least 3.8, at least 4, at least 5, at least 6, at least 7, at least 8, at least 9, at least 10, at least 12, at least 15, at least 20, at least 25, at least 30, at least 35, at least 40, or at least 45 W/mK. Also, each grain may independently have a thermal conductivity K value of at most 0.02, at most 0.03, at most 0.05, at most 0.08, at most 0.1, at most 0.12, at most 0.15, at most 0.2, at most 0.25, at most 0.3, at most 0.35, at most 0.4, at most 0.45, at most 0.5, at most 0.6, at most 0.7, at most 0.8, at most 0.9, at most 1.0, at most 1.2, at most 1.5, at most 1.8, at most 2.0, at most 2.2, at most 2.5, at most 2.8, at most 3.0, at most 3.2, at most 3.5, at most 3.8, at most 4, at most 5, at most 6, at most 7, at most 8, at most 9, at most 10, at most 12, at most 15, at most 20, at most 25, at most 30, at most 35, at most 40, at most 45, or at most 50 W/mK.

For example, the grainsmay include material grainshaving a high thermal conductivity, material grainshaving a low or lower thermal conductivity, and, optionally, material grainshaving a low or lowest thermal conductivity. In certain embodiments the K value of the thermal conductivity of the grainsat 25° C. may be from 0.01 to 50 W/mK. Herein, the grainsare formed from a first material, the grainsare formed from a second material, and the grainsare formed from a third material. The first material has a greater or higher thermal conductivity than the second material, and the second material has a greater or higher thermal conductivity than the third material.

For example, the first material may be an acrylic and have a thermal conductivity K value of 0.2 W/mK or a polyimide and have a thermal conductivity K value of 0.12 W/mK; the second material may be a polyimide and have a thermal conductivity K value of 0.12 W/mK or a polyester and have a thermal conductivity K value of 0.05 W/mK; and the third material may be a polyester and have a thermal conductivity K value of 0.05 W/mK or a polyurethane and have a thermal conductivity K value of 0.03 W/mK.

The grainsmay comprise materials suitable for three-dimensional printing, such as polyimides, acrylics, polyesters, polyurethanes and other materials. While three different materials are illustrated and described, it is contemplated that two, three, or more than three different materials are used to form the polishing pad. In certain embodiments, the material grainshave no material and act as pores or voids, i.e., the material grainlocation is vacant.

In certain embodiments, the grainsare arranged to form a desired heat dissipation pattern. The pattern may extend laterally, such as along the surface. In certain embodiments, the pattern extends vertically, such as into the pad. The pattern may include conductive paths, defined by higher thermal conductive material, along which heat may be dissipated from a hot region on the surface. Further, the pattern may include insulative barriers, defined by lower thermal conductive material, at which heat is not as easily conducted.

are overhead views of a portion of the upper surfaceof the polishing padofaccording to different embodiments. As shown in, the pixels or grainsmay be formed with different shapes. For example, in, each grainhas a circular cross-section and may be a sphere, spheroid, or cylindrical. As shown, grainshaving a higher thermal conductivity and grainshaving a lower thermal conductivity are arranged in a desired patterns. Pores or voidsare formed between adjacent grainsthat do not contact one another continuously.

In, each grainhas a square cross-section and may be a cuboid. As shown, grainshaving a higher thermal conductivity and grainshaving a lower thermal conductivity are arranged in a desired patterns. As square grainsandalign with one another without forming voids therebetween, pores or voidsmay be formed at desired locations by not forming a grainat that location.

In, each grainhas a rectangular cross-section and may be a cuboid. As shown, grainshaving a higher thermal conductivity and grainshaving a lower thermal conductivity are arranged in a desired patterns. As rectangular grainsandalign with one another without forming voids therebetween, pores or voidsmay be formed at desired locations by not forming a grainat that location.

In, each grainhas a triangular cross-section and may be a triangular prism or pyramid. As shown, grainshaving a higher thermal conductivity and grainshaving a lower thermal conductivity are arranged in a desired patterns. As triangular grainsandalign with one another without forming voids therebetween, pores or voidsmay be formed at desired locations by not forming a grainat that location.

In, each grainhas a pentagonal cross-section and may be a pentagonal prism. As shown, grainshaving a higher thermal conductivity and grainshaving a lower thermal conductivity are arranged in a desired patterns. Pores or voidsare formed between adjacent grainsthat do not contact one another continuously.

In, each grainhas a hexagonal cross-section and may be a hexagonal prism. As shown, grainshaving a higher thermal conductivity and grainshaving a lower thermal conductivity are arranged in a desired patterns. As hexagonal grainsandalign with one another without forming voids therebetween, pores or voidsmay be formed at desired locations by not forming a grainat that location.

are overhead views schematic views of the upper surfaceof the polishing padofaccording to different embodiments. In, the upper surfaceincludes different regions which are provided with different desired levels of thermal conductivity. The regions may be centered about the axis of rotation of the polishing pad. In certain embodiments, grainsare distributed to form a desired pad region design as shown in.

In, the polishing surfacehas a circular periphery centered on an axis, and the polishing surfaceis formed with radially-arranged regions having different desired thermal conductivities. For example, each region may have an independently selected radial width. For example, each radial width may be from 1 micrometer to 40 millimeters, such as from 1 to 400 micrometers. Further, each region may independently have a thermal conductivity K value of at least 0.01, at least 0.03, at least 0.05, at least 0.08, at least 0.1, at least 0.12, at least 0.15, at least 0.2, at least 0.25, at least 0.3, at least 0.35, at least 0.4, at least 0.45, at least 0.5, at least 0.6, at least 0.7, at least 0.8, at least 0.9, at least 1.0, at least 1.2, at least 1.5, at least 1.8, at least 2.0, at least 2.2, at least 2.5, at least 2.8, at least 3.0, at least 3.2, at least 3.5, at least 3.8, at least 4, at least 5, at least 6, at least 7, at least 8, at least 9, at least 10, at least 12, at least 15, at least 20, at least 25, at least 30, at least 35, at least 40, or at least 45 W/mK. Also, each region may independently have a thermal conductivity K value of at most 0.02, at most 0.03, at most 0.05, at most 0.08, at most 0.1, at most 0.12, at most 0.15, at most 0.2, at most 0.25, at most 0.3, at most 0.35, at most 0.4, at most 0.45, at most 0.5, at most 0.6, at most 0.7, at most 0.8, at most 0.9, at most 1.0, at most 1.2, at most 1.5, at most 1.8, at most 2.0, at most 2.2, at most 2.5, at most 2.8, at most 3.0, at most 3.2, at most 3.5, at most 3.8, at most 4, at most 5, at most 6, at most 7, at most 8, at most 9, at most 10, at most 12, at most 15, at most 20, at most 25, at most 30, at most 35, at most 40, at most 45, or at most 50 W/mK.

In, the upper surfaceof the polishing padis provided with an inner low K design. Specifically, the upper surfacehas a central inner regionthat is formed with a low K material, i.e., a lower thermal conductivity than a radially outer region.