Controlling the Number of Powered Vector Lanes via a Register Field

This U.S. Patent Application is a continuation of U.S. patent application Ser. No. 18/627,428, filed Apr. 4, 2024, which is a continuation of U.S. patent application Ser. No. 17/838,368, filed Jun. 13, 2022, now U.S. Pat. No. 11,989,072, which is a continuation of U.S. patent application Ser. No. 16/983,451, filed Apr. 3, 2020, now U.S. Pat. No. 11,360,536, which is a continuation of U.S. patent application Ser. No. 15/638,407, filed Jun. 30, 2017, now U.S. Pat. No. 10,732,689, which is a continuation-in-part of U.S. patent application Ser. No. 14/326,928, filed Jul. 9, 2014, now U.S. Pat. No. 10,175,981, which claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 61/844,124, filed Jul. 9, 2013, each of which is incorporated by reference herein in its entirety.

The technical field of this invention is digital data processing.

Vector processors consume high amounts of power due to the wide data path width. A normal vector unit can only be turned ON or OFF in its entirety. Such a normal vector unit wastes power when executing smaller data width operations. This invention specifies a method to turn on and off a portion of the vector data path on the fly.

Power consumption may be minimized by dividing the vector data path width into smaller vector lanes. For example, a 256 bit vector data path may be divided into thirty-two 8-bit vector lanes. One or more up to all 32 of these vector lanes may be enabled for any particular instruction. There must be some manner of setting the number and identity of the vector lanes powered for any particular instruction.

Totsuka, U.S. Patent Application Publication No. 2006/0155964 published Jul. 13, 2006, teaches one prior art manner of identifying the vector lanes powered. Totsuka teaches a register stores data having one bit corresponding to each of the vector lanes of the vector data path. For each vector lane, 0 in the corresponding register location turns OFF power to that vector lane. A 1 in the corresponding register location turns ON power to that vector lane. Thus, unused vector lanes may be powered OFF during a particular instruction operation saving power.

In an example, the vector data path is divided into smaller vector lanes. For instance, a 256-bit wide vector data path can be divided into thirty-two smaller 8-bit vector lanes. The invention allows the programmer to control the number of active vector lanes within a vector data path by writing into a control register field the number of active vector lanes.

In an example, a register such as a memory mapped control register stores a number (VLX) indicating which vector lanes are to be powered on. A decoder converts this VLX into a vector lane control word. Each bit of the vector lane control word corresponds to one of the vector lanes of the vector data path. The digital state of each vector lane control word bit controls the ON and OFF state of the corresponding vector lane. A prior art method stores one bit for each vector lane.

This invention provides as much flexibility as generally needed while requiring fewer stored bits than the prior art. In this invention the stored data indicates the number of vector lanes to be powered. This number of contiguous least significant vector lanes of the vector data path are powered. All other vector lanes are unpowered. This permits the stored data to require fewer bits.

An additional refinement realizes that it is not necessary to permit powering of every possible number of vector lanes. Data word sizes are typically on the order of 2, where N is an integer. SIMD operations which may be performed on such vector processors often employ 2(where P is an integer) number of elements. Accordingly, it is often advantageous to control power to the vector processor to an integral power of 2 vector lanes rather than specifying all possible number of vector lanes. In the preferred embodiment the stored data VLX indicates that 2contiguous least significant vector lanes are to be powered. If the number of vector lanes required is not an integral power of 2, this invention powers the next greater integral power of 2 number of vector lanes. Except when more than half of the vector lanes are required, this still results in power saving over powering all vector lanes. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually powering all vector lanes.

illustrates a single core scalar processor according to one embodiment of this invention. Single core processorincludes a scalar central processing unit (CPU)coupled to separate level one instruction cache (L1I)and level one data cache (L1D). Central processing unit corecould be constructed as known in the art and would typically include a register file, an integer arithmetic logic unit, an integer multiplier and program flow control units. Single core processorincludes a level two combined instruction/data cache (L2)that holds both instructions and data. In the preferred embodiment scalar central processing unit (CPU), level one instruction cache (L1I), level one data cache (L1D)and level two combined instruction/data cache (L2)are formed on a single integrated circuit.

In a preferred embodiment this single integrated circuit also includes auxiliary circuits such as power control circuit, emulation/trace circuits, design for test (DST) programmable built-in self test (PBIST) circuitand clocking circuit. External to CPUand possibly integrated on single integrated circuitis memory controller.

CPUoperates under program control to perform data processing operations upon defined data. The program controlling CPUconsists of a plurality of instructions that must be fetched before decoding and execution. Single core processorincludes a number of cache memories.illustrates a pair of first level caches. Level one instruction cache (L1I)stores instructions used by CPU. CPUfirst attempts to access any instruction from level one instruction cache. Level one data cache (L1D)stores data used by CPU. CPUfirst attempts to access any required data from level one data cache. The two level one caches (L1Iand L1D) are backed by a level two unified cache (L2). In the event of a cache miss to level one instruction cacheor to level one data cache, the requested instruction or data is sought from level two unified cache. If the requested instruction or data is stored in level two unified cache, then it is supplied to the requesting level one cache for supply to central processing unit core. As is known in the art, the requested instruction or data may be simultaneously supplied to both the requesting cache and CPUto speed use.

Level two unified cacheis further coupled to higher level memory systems via memory controller. Memory controllerhandles cache misses in level two unified cacheby accessing external memory (not shown in). Memory controllerhandles all memory centric functions such as cacheabilty determination, error detection and correction, address translation and the like. Single core processormay be a part of a multiprocessor system. In that case memory controllerhandles data transfer between processors and maintains cache coherence among processors.

illustrates a dual core processor according to another embodiment of this invention. Dual core processorincludes first CPUcoupled to separate level one instruction cache (L1I)and level one data cache (L1D)and second CPUcoupled to separate level one instruction cache (L1I)and level one data cache (L1D). Central processing unitsandare preferably constructed similar to CPUillustrated in. Dual core processorincludes a single shared level two combined instruction/data cache (L2)supporting all four level one caches (L1I, L1D, L1Iand L1D). In the preferred embodiment CPU, level one instruction cache (L1I), level one data cache (L1D), CPU, level one instruction cache (L1I), level one data cache (L1D)and level two combined instruction/data cache (L2)are formed on a single integrated circuit. This single integrated circuit preferably also includes auxiliary circuits such as power control circuit, emulation/trace circuits, design for test (DST) programmable built-in self test (PBIST) circuitand clocking circuit. This single integrated circuit may also include memory controller.

illustrate single core and dual core processors similar to that shown respectively in.differ fromin showing vector central processing units. As further described below single core vector processorincludes a vector CPU. Dual core vector processorincludes two vector CPUsand. Vector CPUs,andinclude wider data path operational units and wider data registers than the corresponding scalar CPUs,and.

Vector CPUs,andfurther differ from the corresponding scalar CPUs,andin the inclusion of streaming engine() and streaming enginesand(). Streaming engines,andare similar. Streaming enginetransfers data from level two unified cache(L2) to a vector CPU. Streaming enginetransfers data from level two unified cacheto vector CPU. Streaming enginetransfers data from level two unified cacheto vector CPU. In accordance with the preferred embodiment each streaming engine,andmanages up to two data streams.

Each streaming engine,andtransfer data in certain restricted circumstances. A stream consists of a sequence of elements of a particular type. Programs that operate on streams read the data sequentially, operating on each element in turn. Every stream has the following basic properties. The stream data have a well-defined beginning and ending in time. The stream data have fixed element size and type throughout the stream. The stream data have fixed sequence of elements. Thus, programs cannot seek randomly within the stream. The stream data is read-only while active. Programs cannot write to a stream while simultaneously reading from it. Once a stream is opened the streaming engine: calculates the address; fetches the defined data type from level two unified cache; performs data type manipulation such as zero extension, sign extension, data element sorting/swapping such as matrix transposition; and delivers the data directly to the programmed execution unit within the CPU. Streaming engines are thus useful for real-time digital filtering operations on well-behaved data. Streaming engines free these memory fetch tasks from the corresponding CPU enabling other processing functions.

The streaming engines provide the following benefits. They permit multi-dimensional memory accesses. They increase the available bandwidth to the functional units. They minimize the number of cache miss stalls since the stream buffer can bypass L1D cache. They reduce the number of scalar operations required in the loop to maintain. They manage the address pointers. They handle address generation automatically freeing up the address generation instruction slots and the .D unit for other computations.

illustrates construction of one embodiment of the CPU of this invention. Except where noted this description covers both scalar CPUs and vector CPUs. The CPU of this invention includes plural execution units multiply unit(.M), correlation unit(.C), arithmetic unit(.L), arithmetic unit(.S), load/store unit(.D), branch unit(.B) and predication unit(.P). The operation and relationships of these execution units are detailed below.

Multiply unitprimarily performs multiplications. Multiply unitaccepts up to two double vector operands and produces up to one double vector result. Multiply unitis instruction configurable to perform the following operations: various integer multiply operations, with precision ranging from 8-bits to 64-bits; various regular and complex dot product operations; and various floating point multiply operations; bit-wise logical operations; moves; as well as adds and subtracts. As illustrated inmultiply unitincludes hardware for four simultaneous 16 bit by 16 bit multiplications. Multiply unitmay access global scalar register file, global vector register fileand shared .M and .C local registerfile in a manner described below. Forwarding multiplexermediates the data transfer between global scalar register file, global vector register file, the corresponding streaming engine and multiply unit.

Correlation unit(.C) accepts up to two double vector operands and produces up to one double vector result. Correlation unitsupports these major operations. In support of WCDMA “Rake” and “Search” instructions correlation unitperforms up to 512 2-bit PN*8-bit I/Q complex multiplies per clock cycle. Correlation unitperforms 8-bit and 16-bit Sum-of-Absolute-Difference (SAD) calculations performing up to 512 SADs per clock cycle. Correlation unitperforms horizontal add and horizontal min/max instructions. Correlation unitperforms vector permute instructions. Correlation unitincludes 8 256-bit wide control registers. These control registers are used to control the operations of certain correlation unit instructions. Correlation unitmay access global scalar register file, global vector register fileand shared .M and .C local register filein a manner described below. Forwarding multiplexermediates the data transfer between global scalar register file, global vector register file, the corresponding streaming engine and correlation unit.

CPUincludes two arithmetic units: arithmetic unit(.L) and arithmetic unit(.S). Each arithmetic unitand arithmetic unitaccepts up to two vector operands and produces one vector result. The compute units support these major operations. Arithmetic unitand arithmetic unitperform various single-instruction-multiple-data (SIMD) fixed point arithmetic operations with precision ranging from 8-bit to 64-bits. Arithmetic unitand arithmetic unitperform various compare and minimum/maximum instructions which write results directly to predicate register file(further described below). Arithmetic unitand arithmetic unitperform various SIMD floating point arithmetic operations with precision ranging from half-precision (16-bits), single precision (32-bits) to double precision (64-bits). Arithmetic unitand arithmetic unitperform specialized instructions to speed up various algorithms and functions. Arithmetic unitand arithmetic unitmay access global scalar register file, global vector register file, shared .L and .S local register fileand predicate register filein a manner described below. Forwarding multiplexermediates the data transfer between global scalar register file, global vector register file, the corresponding streaming engine and arithmetic unitsand.

Load/store unit(.D) is primarily used for address calculations. Load/store unitis expanded to accept scalar operands up to 64-bits and produces scalar result up to 64-bits. Load/store unitincludes additional hardware to perform data manipulations such as swapping, pack and unpack on the load and store data to reduce workloads on the other units. Load/store unitcan send out one load or store request each clock cycle along with the 44-bit physical address to level one data cache (L1D). Load or store data width can be 32-bits, 64-bits, 256-bits or 512-bits. Load/store unitsupports these major operations: 64-bit SIMD arithmetic operations; 64-bit bit-wise logical operations; and scalar and vector load and store data manipulations. Load/store unitpreferably includes a micro-TLB (table look-aside buffer) block to perform address translation from a 48-bit virtual address to a 44-bit physical address. Load/store unitmay access global scalar register file, global vector register fileand .D local register filein a manner described below. Forwarding multiplexermediates the data transfer between global scalar register file, global vector register file, the corresponding streaming engine and load/store unit.

Branch unit(.B) calculates branch addresses, performs branch predictions, and alters control flows dependent on the outcome of the prediction.

Predication unit(.P) is a small control unit which performs basic operations on vector predication registers. Predication unithas direct access to the vector predication registers. Predication unitperforms different bit operations on the predication registers such as AND, ANDN, OR, XOR, NOR, BITR, NEG, SET, BITCNT, RMBD, BIT Decimate and Expand, etc.

illustrates global scalar register file. There are 16 independent 64-bit wide scalar registers. Each register of global scalar register filecan be read as 32-bits scalar data (designated registers A0 to A15) or 64-bits of scalar data (designated registers EA0 to EA15). However, writes are always 64-bit, zero-extended to fill up to 64-bits if needed. All scalar instructions of all functional units can read or write to global scalar register file. The instruction type determines the data size. Global scalar register filesupports data types ranging in size from 8-bits through 64-bits. A vector instruction can also write to the 64-bit global scalar registerswith the upper 192 bit data of the vector discarded. A vector instruction can also read 64-bit data from the global scalar register file. In this case the operand is zero-extended in the upper 192-bit to form an input vector.

illustrates global vector register file. There are 16 independent 256-bit wide vector registers. Each register of global vector register filecan be read as 32-bits scalar data (designated registers X0 to X15), 64-bits of scalar data (designated registers EXO to EX15), 256-bit vector data (designated registers VX0 to VX15) or 512-bit double vector data (designated DVX0 to DVX7, not illustrated). In the current embodiment only multiply unitand correlation unitmay execute double vector instructions. All vector instructions of all functional units can read or write to global vector register file. Any scalar instruction of any functional unit can also access the low 32 or 64 bits of a global vector register fileregister for read or write. The instruction type determines the data size.

illustrates local vector register file. There are 16 independent 256-bit wide vector registers. Each register of local vector register filecan be read as 32-bits scalar data (designated registers M0 to M15), 64-bits of scalar data (designated registers EM0 to EM15), 256-bit vector data (designated registers VM0 to VM15) or 512-bit double vector data (designated DVM0 to DVM7, not illustrated). In the current embodiment only multiply unitand correlation unitmay execute double vector instructions. All vector instructions of all functional units can write to local vector register file. Only instructions of multiply unitand correlation unitmay read from local vector register file. The instruction type determines the data size.

Multiply unitmay operate upon double vectors (512-bit data). Multiply unitmay read double vector data from and write double vector data to global vector register fileand local vector register file. Register designations DVXx and DVMx are mapped to global vector register fileand local vector register fileas follows.

Each double vector designation maps to a corresponding pair of adjacent vector registers in either global vector registeror local vector register. Designations DVX0 to DVX7 map to global vector register. Designations DVM0 to DVM7 map to local vector register.

Local vector register fileis similar to local vector register file. There are 16 independent 256-bit wide vector registers. Each register of local vector register filecan be read as 32-bits scalar data (designated registers L0 to L15), 64-bits of scalar data (designated registers EL0 to EL15) or 256-bit vector data (designated registers VL0 to VL15). All vector instructions of all functional units can write to local vector register file. Only instructions of arithmetic unitand arithmetic unitmay read from local vector register file.

illustrates local register file. There are 16 independent 64-bit wide registers. Each register of local register filecan be read as 32-bits scalar data (designated registers DO to D15) or 64-bits of scalar data (designated registers ED0 to ED15). All scalar and vector instructions of all functional units can write to local register file. Only instructions of load/store unitmay read from local register file. Any vector instructions can also write 64-bit data to local register filewith the upper 192 bit data of the result vector discarded. Any vector instructions can also read 64-bit data from the 64-bit local register fileregisters. The return data is zero-extended in the upper 192-bit to form an input vector. The registers of local register filecan only be used as addresses in load/store instructions, not as store data or as sources for 64-bit arithmetic and logical instructions of load/store unit.

illustrates the predicate register file. There are sixteen registers 32-bit registers in predicate register file. Predicate register filecontains the results from vector comparison operations and is used by vector selection instructions and vector predicated store instructions. A small subset of special instructions can also read directly from predicate registers, performs operations and write back to a predicate register directly. There are also instructions which can transfer values between the global register files (and) and predicate register file. Transfers between predicate register fileand local register files (,and) are not supported. Each bit of a predication register (designated P0 to P15) controls a byte of a vector data. Since a vector is 256-bits, the width of a predicate register equals 256/8=32 bits. The predicate register file can be written to by vector comparison operations to store the results of the vector compares.

A CPU such as CPU,,,,oroperates on an instruction pipeline. This instruction pipeline can dispatch up to nine parallel 32-bits slots to provide instructions to the seven execution units (multiply unit, correlation unit, arithmetic unit, arithmetic unit, load/store unit, branch unitand predication unit) every cycle. Instructions are fetched instruction packets of fixed length further described below. All instructions require the same number of pipeline phases for fetch and decode, but require a varying number of execute phases.

illustrates the following pipeline phases: program fetch phase, dispatch and decode phasesand execution phases. Program fetch phaseincludes three stages for all instructions. Dispatch and decode phasesinclude three stages for all instructions. Execution phaseincludes one to four stages dependent on the instruction.

Fetch phaseincludes program address generation stage(PG), program access stage(PA) and program receive stage(PR). During program address generation stage(PG), the program address is generated in the CPU and the read request is sent to the memory controller for the level one instruction cache L1I. During the program access stage(PA) the level one instruction cache L1I processes the request, accesses the data in its memory and sends a fetch packet to the CPU boundary. During the program receive stage(PR) the CPU registers the fetch packet.

Instructions are always fetched sixteen words at a time.illustrates this fetch packet.illustrates 16 instructionstoof a single fetch packet. Fetch packets are aligned on 512-bit (16-word) boundaries. The execution of the individual instructions is partially controlled by a p bit in each instruction. This p bit is preferably bitof the instruction. The p bit determines whether the instruction executes in parallel with another instruction. The p bits are scanned from lower to higher address. If the p bit of an instruction is 1, then the next following instruction is executed in parallel with (in the same cycle as) that instruction I. If the p bit of an instruction is 0, then the next following instruction is executed in the cycle after the instruction. All instructions executing in parallel constitute an execute packet. An execute packet can contain up to nine instructions. Each instruction in an execute packet must use a different functional unit. An execute packet can contain up to nine 32-bit wide slots. A slot can either be a self-contained instruction or expand the constant field specified by the immediately preceding instruction. A slot can be used as conditional codes to apply to the instructions within the same fetch packet. A fetch packet can contain up to 2 constant extension slots and one condition code extension slot.

There are up to 11 distinct instruction slots, but scheduling restrictions limit to 9 the maximum number of parallel slots. The maximum nine slots are shared as follows: multiply unit; correlation unit; arithmetic unit; arithmetic unit; load/store unit; branch unitshared with predicate unit; a first constant extension; a second constant extension; and a unit less instruction shared with a condition code extension. The last instruction in an execute packet has a p bit equal to 0.

The CPU and level one instruction cache L1I pipelines are de-coupled from each other. Fetch packet returns from level one instruction cache L1I can take different number of clock cycles, depending on external circumstances such as whether there is a hit in level one instruction cache L1I. Therefore, program access stage(PA) can take several clock cycles instead ofclock cycle as in the other stages.

Dispatch and decode phasesinclude instruction dispatch to appropriate execution unit stage(DS), instruction pre-decode stage(DC1); and instruction decode, operand reads stage(DC2). During instruction dispatch to appropriate execution unit stage(DS) the fetch packets are split into execute packets and assigned to the appropriate functional units. During the instruction pre-decode stage(DC1) the source registers, destination registers, and associated paths are decoded for the execution of the instructions in the functional units. During the instruction decode, operand reads stage(DC2) more detail unit decodes are done, as well as reading operands from the register files.

Execution phasesincludes execution stagesto(E1 to E5). Different types of instructions require different numbers of these stages to complete their execution. These stages of the pipeline play an important role in understanding the device state at CPU cycle boundaries.

During execute 1 stage(E1) the conditions for the instructions are evaluated and operands are operated on. As illustrated in, execute 1 stagemay receive operands from a stream bufferand one of the register files shown schematically as. For load and store instructions, address generation is performed and address modifications are written to a register file. For branch instructions, branch fetch packet in PG phase is affected. As illustrated in, load and store instructions access memory here shown schematically as memory. For single-cycle instructions, results are written to a destination register file. This assumes that any conditions for the instructions are evaluated as true. If a condition is evaluated as false, the instruction does not write any results or have any pipeline operation after execute 1 stage.

During execute 2 stage(E2) load instructions send the address to memory. Store instructions send the address and data to memory. Single-cycle instructions that saturate results set the SAT bit in a control status register (CSR) if saturation occurs. For 2-cycle instructions, results are written to a destination register file.

During execute 3 stage(E3) data memory accesses are performed. Any multiply instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs. For 3-cycle instructions, results are written to a destination register file.

During execute 4 stage(E4) load instructions bring data to the CPU boundary. For 4-cycle instructions, results are written to a destination register file.

During execute 5 stage(E5) load instructions write data into a register. This is illustrated schematically inwith input from memoryto execute 5 stage.

illustrates an example of the instruction coding of instructions used by this invention. Each instruction consists of 32 bits and controls the operation of one of the individually controllable functional units (multiply unit, correlation unit, arithmetic unit, arithmetic unit, load/store unit, branch unitand predication unit). The bit fields are defined as follows. The creg field and the z bit are optional fields used in conditional instructions. These bits are used for conditional instructions to identify the predicate register and the condition. The z bit (bit) indicates whether the predication is based upon zero or not zero in the predicate register. If z=1, the test is for equality with zero. If z=0, the test is for nonzero. The case of creg=0 and z=0 is treated as always true to allow unconditional instruction execution. The creg field and the z field are encoded in the instruction as shown in Table 2.

Note that “z” in the z bit column refers to the zero/not zero comparison selection noted above and “x” is a don't care state. This coding can only specify a subset of the 16 global scalar registers as predicate registers. This selection was made to preserve bits in the instruction coding. Note that unconditional instructions do not have these optional bits. For unconditional instructions these bits (28 to 31) are preferably used as additional opcode bits. However, if needed, an execute packet can contain a unique 32-bit condition code extension slot which contains the 4-bit CREGZ fields for the instructions which are in the same execute packet. Table 3 shows the coding of such a condition code extension slot.

Thus, the condition code extension slot specifies bits decoded in the same way the creg/z bits assigned to a particular functional unit in the same execute packet.

The dst field specifies a register in a corresponding register file as the destination of the instruction results.