Package with Permalloy Core Inductor and Manufacturing Method Thereof

This application is a divisional of U.S. application Ser. No. 17/844,476, filed on Jun. 20, 2022, which application is hereby incorporated herein by reference.

The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged. An example is the integration of inductors in such packaging systems. Inductors can be used for various applications, such as filters in circuits, energy storage components, reactors to depress voltage, switching current limiters or transformers.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Various embodiments provide methods of forming an integrated circuit package that includes an inductor having a magnetic permalloy core. The permalloy core comprises a plurality of vertically stacked alternating layers that include a plurality of permalloy layers and a plurality of epoxy layers, such that each permalloy layer of the plurality of permalloy layers is disposed between two epoxy layers of the plurality of epoxy layers. The permalloy core may be a magnetic bar that is formed to be in the shape of a closed loop (e.g., having a toroidal loop shape, rectangular loop shape, or the like), or may comprise a plurality of closed loops. Advantageous features of one or more embodiments disclosed herein may include increased magnetic permeability of the permalloy core, which results in a higher inductance. The permalloy core comprising a plurality of closed loops also allows for a further inductance increase. Further, the disclosed method may provide more efficient and compact power inductors that can be integrated easily into existing processes and provide improved inductor performance with lower manufacturing costs and improve space utilization.

illustrates a cross-sectional view of an integrated circuit diein accordance with some embodiments. The integrated circuit diewill be packaged in subsequent processing to form an integrated circuit package. The integrated circuit diemay be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), a high-performance computing (HPC) die, an artificial intelligence (AI) die, an automotive die, the like, or combinations thereof.

The integrated circuit diemay be formed in a wafer, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. The integrated circuit diemay be processed according to applicable manufacturing processes to form integrated circuits. For example, the integrated circuit dieincludes a semiconductor substrate, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substratemay include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substratehas an active surface (e.g., the surface facing upwards in), sometimes called a front side, and an inactive surface (e.g., the surface facing downwards in), sometimes called a back side.

Devices (represented by a transistor)may be formed at the front surface of the semiconductor substrate. The devicesmay be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An inter-layer dielectric (ILD)is over the front surface of the semiconductor substrate. The ILDsurrounds and may cover the devices. The ILDmay include one or more dielectric layers formed of materials such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like.

Conductive plugsextend through the ILDto electrically and physically couple the devices. For example, when the devicesare transistors, the conductive plugsmay couple the gates and source/drain regions of the transistors. The conductive plugsmay be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. An interconnect structureis over the ILDand conductive plugs. The interconnect structureinterconnects the devicesto form an integrated circuit. The interconnect structuremay be formed by, for example, metallization patterns in dielectric layers on the ILD. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers. The metallization patterns of the interconnect structureare electrically coupled to the devicesby the conductive plugs.

The integrated circuit diefurther includes pads, such as aluminum pads, to which external connections are made. The padsare on the active side of the integrated circuit die, such as in and/or on the interconnect structure. One or more passivation filmsare on the integrated circuit die, such as on portions of the interconnect structureand pads. Openings extend through the passivation filmsto the pads. Die connectors, such as conductive pillars (for example, formed of a metal such as copper), extend through the openings in the passivation filmsand are physically and electrically coupled to respective ones of the pads. The die connectorsmay be formed by, for example, plating, or the like. The die connectorselectrically couple the respective integrated circuits of the integrated circuit die.

Optionally, solder regions (e.g., solder balls or solder bumps) may be disposed on the pads. The solder balls may be used to perform chip probe (CP) testing on the integrated circuit die. CP testing may be performed on the integrated circuit dieto ascertain whether the integrated circuit dieis a known good die (KGD). Thus, only integrated circuit dies, which are KGDs, undergo subsequent processing and are packaged, and dies, which fail the CP testing, are not packaged. After testing, the solder regions may be removed in subsequent processing steps.

A dielectric layermay (or may not) be on the active side of the integrated circuit die, such as on the passivation filmsand the die connectors. The dielectric layerlaterally encapsulates the die connectors, and the dielectric layeris laterally coterminous with the integrated circuit die. Initially, the dielectric layermay bury the die connectors, such that the topmost surface of the dielectric layeris above the topmost surfaces of the die connectors. In some embodiments where solder regions are disposed on the die connectors, the dielectric layermay bury the solder regions as well. Alternatively, the solder regions may be removed prior to forming the dielectric layer.

The dielectric layermay be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof. The dielectric layermay be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connectorsare exposed through the dielectric layerduring formation of the integrated circuit die. In some embodiments, the die connectorsremain buried and are exposed during a subsequent process for packaging the integrated circuit die. Exposing the die connectorsmay remove any solder regions that may be present on the die connectors.

illustrate cross-sectional views of intermediate steps during a process for forming a first package component, in accordance with some embodiments. A first package regionA and a second package regionB are illustrated, and one or more of the integrated circuit diesare packaged to form an integrated circuit package in each of the package regionsA andB. The integrated circuit packages may also be referred to as integrated fan-out (InFO) packages.

illustrate the formation of a back-side redistribution structureover the carrier substrate. In the embodiment shown, the back-side redistribution structureincludes a dielectric layer, a dielectric layer, and a lower redistribution layer (RDL)(sometimes referred to as a metallization pattern) in the dielectric layer.

In, a carrier substrateis provided, and a release layeris formed on the carrier substrate. The carrier substratemay be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substratemay be a wafer, such that multiple packages can be formed on the carrier substratesimultaneously.

The release layermay be formed of a polymer-based material, which may be removed along with the carrier substratefrom the overlying structures that will be formed in subsequent steps. In some embodiments, the release layeris an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layermay be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layermay be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate, or may be the like. The top surface of the release layermay be leveled and may have a high degree of planarity.

Still referring to, a dielectric layeris formed on the release layer. The dielectric layermay be, for example, a layer of polymer material such as, e.g., polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or other polymer material that is electrically insulating. The dielectric layermay be formed using a process such as lamination, coating, (e.g., spin-coating), chemical vapor deposition (CVD), or the like. In some embodiments, the dielectric layermay comprise a glass, a spin-on glass (SOG), a ceramic, low temperature co-fired ceramic (LTCC), silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like.

In, the lower redistribution layer (RDL)is formed on portions of the dielectric layerby initially forming a first seed layer (not shown) of one or more thin layers of a conductive material that aids in the formation of a thicker layer during subsequent processing steps. The first seed layer may comprise a layer of titanium or copper formed using processes such as sputtering, evaporation, PECVD, or the like. A photoresist (also not shown) may then be formed and patterned to cover the first seed layer using, e.g., a spin coating technique. Once the photoresist has been formed and patterned, a conductive material may be formed on the first seed layer. The conductive material may be a material such as copper, titanium, tungsten, aluminum, another metal, the like, or a combination thereof. The conductive material may be formed through a deposition process such as electroplating, electroless plating, or the like. Once the conductive material has been formed, the photoresist may be removed through a suitable removal process such as ashing or chemical stripping. Additionally, after the removal of the photoresist, those portions of the first seed layer that were covered by the photoresist may be removed through, for example, a suitable wet etch process or dry etch process, which may use the conductive material as an etch mask. The remaining portions of the first seed layer and conductive material form the lower redistribution layer (RDL).

After the formation of the lower RDL, a dielectric layeris formed over the dielectric layerand the lower RDL. The dielectric layermay be, for example, a layer of polymer material such as, e.g., polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or other polymer material that is electrically insulating. The dielectric layermay be formed using a process such as lamination, coating, (e.g., spin-coating), chemical vapor deposition (CVD), or the like. In an embodiment, the dielectric layerand the dielectric layermay comprise different materials. In some embodiments, the dielectric layermay comprise a glass, a spin-on glass (SOG), a ceramic, low temperature co-fired ceramic (LTCC), silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. A planarization step, such as a chemical mechanical polish (CMP), may be performed to remove excess portions of the dielectric layerwhich are over top surfaces of the lower RDL. Accordingly, top surfaces of the lower RDLare exposed, and are level with a top surface of the dielectric layer. In an embodiment, a thickness Tof the lower RDLand the dielectric layermay be in a range from 5 μm to 50 μm.

In, a mask layeris formed over the structure shown in, such as over the dielectric layerand the lower RDL. The mask layermay be a dry-film photoresist, or the like, and may be formed using a spin on process, a lamination process, or the like. In an embodiment, the mask layermay be formed to have a thickness that is less than 300 μm. The mask layermay be patterned using acceptable development and exposure techniques to form openings (or through holes)in which electrically conductive vias are subsequently formed, according to some embodiments. The vias may be alternatively referred to as pillars or through-insulator-vias or TIVs when spanning an insulating layer. The openingsin the mask layer may expose top surfaces of the lower RDLand/or the dielectric layer.

In, a seed layeris formed on the mask layerand in the openingsof the mask layer, such as on bottom surfaces and sidewalls of the openings. The metal seed layermay comprise, for example, a titanium and copper bilayer (e.g., a layer of copper on a layer of titanium), a singular copper layer, or other suitable metal layer, and may be deposited using a CVD process, an ALD process, or the like. Any suitable thickness may be used for the seed layer. For example, in some embodiments, the seed layermay comprise a titanium layer that is at least 1000 Å thick and a copper layer that is at least 5000 Å thick. In other embodiments, the seed layermay comprise other combinations of metals and thicknesses.

In, a conductive materialis formed on the seed layerand in the openingsin order to fill in the openings. The conductive materialmay be a copper layer or other suitable metal formed by an electrochemical plating (ECP) process, or the like. During the ECP process, the conductive materialis deposited both laterally on the sidewalls of the openingsas well as vertically on bottom surfaces of the openings.

In, a planarization step, such as a chemical mechanical polish (CMP), or the like, may be performed to remove portions of the seed layerand excess portions of the conductive materialwhich are over the mask layer. The remaining conductive materialand the seed layerin the openingsform the plurality of conductive vias. Accordingly, after the planarization step, top surfaces of the conductive material, the seed layer, and the mask layerare level.

In, after the planarization step, the mask layermay be removed using a suitable removal process such as ashing or chemical stripping.

In, a dielectric layeris formed over the dielectric layerand the lower RDL. The dielectric layermay be, for example, a layer of polymer material such as, e.g., polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or other polymer material that is electrically insulating. The dielectric layermay be formed using a spin-on process, or the like. The use of the spin-on process to form the dielectric layerallows a material of the dielectric layerto be initially formed in a liquid phase over the dielectric layerand the lower RDLand not on top surfaces of the plurality of conductive vias. The dielectric layermay then be subsequently cured. In an embodiment, a thickness Tof the dielectric layermay be in a range from 2 μm to 12 μm.

In, a plurality of magnetic solenoid permalloy coresand a plurality of integrated circuit diesare attached to a top surface of the dielectric layerusing, for example, a pick and place process, a carrier bonding process, or the like. An example carrier bonding process is illustrated in, but other pick and place processes are also possible for placing the permalloy coresand the integrated circuit dies. In, a carrier substrateis shown. The carrier substratemay comprise silicon-based materials, such as a silicon substrate (e.g., a silicon wafer), a glass material, silicon oxide, or other materials, such as aluminum oxide, the like, or a combination. The carrier substratemay comprise a transparent material such as glass, or the like. An adhesive layeris formed on the carrier substrateto facilitate a subsequent debonding of the carrier substratefrom the first package component. The adhesive layermay comprise a polymer-based material, which may be removed along with the carrier substratefrom the first package component. In some embodiments, the adhesive layermay comprise an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a Light-to-Heat-Conversion (LTHC) release coating. In some embodiments, the adhesive layermay comprise an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV light. After the adhesive layeris formed, a suitable curing process may be performed to harden the adhesive material.

In, a mask layer (e.g., a photoresist) is formed over the adhesive layer. The mask layer is patterned using suitable development and exposure techniques to form openings in the mask layer that expose top surfaces of the adhesive layer. A suitable etching process (e.g., an anisotropic etching process) is then performed to partially etch exposed portions of the adhesive layerusing the mask layer as an etching mask. As a result, the adhesive layermay comprise regions with different thicknesses, and the thicknesses can be controlled by varying the parameters of the etching process. After the etching process is performed on the adhesive layer, the mask layer may then be removed using an acceptable ashing or stripping process. Althoughillustrates an adhesive layerwith two different thicknesses, one or more photolithography and etching processes may be used to pattern an adhesive layerwith any number of different thicknesses.

In, the plurality of magnetic solenoid permalloy coresand the plurality of integrated circuit diesare attached to a top surface of the adhesive layerusing, for example, a pick and place process, or the like. The plurality of integrated circuit diesare attached to the adhesive layersuch that the dielectric layerof each of the plurality of integrated circuit diesfaces the adhesive layer. The plurality of permalloy coresmay be disposed on regions of the adhesive layerthat have larger heights than the regions of the adhesive layeron which the plurality of integrated circuit diesare disposed on. As a result, topmost surfaces of the plurality of permalloy coresand topmost surfaces of the plurality of integrated circuit diesare level. The plurality of integrated circuit diesand the plurality of permalloy coresmay also comprise a die attach films (DAF)that are disposed on top surfaces of the plurality of integrated circuit diesand the plurality of permalloy cores. The DAFmay comprise a polymer material. In, the carrier substrateand the first package componentare then transported to a bond chamber where the carrier substrateis oriented to align the plurality of permalloy coresand the plurality of integrated circuit dieswith the plurality of conductive vias, such that the plurality of permalloy coresand the plurality of integrated circuit diesface the dielectric layer. The plurality of permalloy coresand the plurality of integrated circuit diesare pressed against the dielectric layerto couple the plurality of permalloy coresand the plurality of integrated circuit diesto the dielectric layerusing the die attach films (DAFs). A first anneal process is then performed in the bond chamber to initiate bonding of the DAF filmswith the dielectric layer. As a result, the plurality of permalloy coresand the plurality of integrated circuit diesare adhered to the dielectric layer. The first anneal may be performed at a temperature in a range from 150° C. to 350° C. and for a duration of time that is in a range from 0.5 hours to 4 hours.

In, a de-bonding of the carrier substrateis then performed to detach (or “de-bond”) the carrier substratefrom the plurality of permalloy coresand the plurality of integrated circuit dies. In accordance with some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the adhesive layerso that the adhesive layerdecomposes under the heat of the light. The carrier substratecan then be mechanically removed leaving the plurality of permalloy coresand the plurality of integrated circuit diesbonded to the dielectric layer. After the removal of the carrier, a second anneal may be performed at a temperature in a range from 150° C. to 350° C. and for a duration of time that is in a range from 0.5 hours to 4 hours. The second anneal strengthens the bonding between the plurality of permalloy coresand the dielectric layer. The second anneal also strengthens the bonding between the plurality of integrated circuit diesand the dielectric layer. In other embodiments, the second anneal maybe performed before the removal of the carrier. AlthoughthoughE illustrate that the plurality of permalloy coresand the plurality of integrated circuit diesare bonded to the top surface of the dielectric layersimultaneously using the carrier substrate, the plurality of integrated circuit diesmay be bonded to the top surface of the dielectric layereither prior to or after the plurality of permalloy coresare bonded to the top surface of the dielectric layer. In such a case, the bonding of the plurality of integrated circuit diesto the top surface of the dielectric layermay be performed with a first carrier substrate, and the bonding of the plurality of permalloy coresto the top surface of the dielectric layermay be performed with a second carrier substrate different from the first carrier substrate.

Each of the plurality of permalloy coresmay comprise a magnetic bar having a shape of a closed loop (e.g., having a rectangular shaped loop, square shaped loop, triangle shaped loop or toroidal shaped loop) when seen in a top-view (for example, as illustrated in) and is disposed such that the closed loop encircles the entire perimeter of at least one of the plurality of integrated circuit dies. Each of the plurality of permalloy coresis disposed such that inner sidewalls and outer sidewalls of the permalloy coreare surrounded by the plurality of conductive vias. In addition, each of the plurality of permalloy coresis sandwiched between the lower RDLbelow the permalloy coreand subsequently formed upper RDL(shown in) above the permalloy core.

illustrates a detailed view of a regionof theand illustrates a portion of one of the plurality of permalloy cores. As illustrated in, each of the plurality of permalloy coresincludes a magnetic bar comprising a plurality of alternating layers that are vertically stacked. The plurality of alternating layers include permalloy layersand epoxy layers, such that each permalloy layeris disposed between two epoxy layers. In an embodiment, each of the plurality of permalloy corescomprises at least eight permalloy layers. In other embodiments, each of the plurality of permalloy corescomprises any number of permalloy layers. A topmost layer and a bottommost layer of the plurality of alternating layers is an epoxy layer, and the plurality of permalloy coresare attached to the dielectric layerusing the die attach film (DAF). The plurality of permalloy corescan also subsequently be referred to as a plurality of “laminated permalloy cores”. Each of the plurality of permalloy coresmay comprise a magnetic bar that is formed to be in the shape of a closed loop (e.g., having a toroidal shaped loop, rectangular shaped loop, square shaped loop, triangle shaped loop, or the like), or may comprise a plurality of closed loops. In some embodiments, the term “permalloy” may be replaced by “Mo-permalloy”, “Mumetal”, “Ultraperm” or “Super-malloy”. In some embodiments, each of the plurality of permalloy coreshas high magnetic permeability. For example, in some embodiments, a magnetic permeability of each of the plurality of permalloy coresis in a range from 1000 μm to 1,000,000 μm. In some embodiments, the permalloy layerscomprises Ni, Fe, Co, Mo, Si, Nb, B, or a combination thereof. For example, each permalloy layermay be an alloy formed by at least two of these elements. In other embodiments, each permalloy layermay be an alloy formed by at least one of the materials listed above and other materials not listed. In an embodiment, each permalloy layermay comprise CoFeB. The epoxy layersmay comprise polymers such as epoxy resins, or the like, which have undergone a curing process. In an embodiment, a thickness Tof the die attach filmis at least 5 μm. In an embodiment, a thickness Tof each permalloy layeris in a range from 1 μm to 50 μm. In an embodiment, a thickness Tof each epoxy layeris in a range from 1 μm to 10 μm. In an embodiment, each of the plurality of permalloy coresmay have a height Hthat is in a range from 50 μm to 500 μm. Advantages can be achieved by each permalloy layerof the plurality of permalloy coreshaving the thickness Tthat is in a range from 1 μm to 50 μm, and each epoxy layerof the plurality of permalloy coreshaving a thickness Tthat is in a range from 1 μm to 10 μm. These include an increased magnetic permeability of each of the plurality of permalloy cores, which allows for a higher inductance.

illustrates a top view of one of the plurality of permalloy coresin accordance with various embodiments.is illustrated in a way that identifies a first direction (e.g., the x-direction), and a second direction (e.g., the −y direction), wherein the second direction is orthogonal to the first direction. The second direction (e.g., the y-direction) is along a similar line to the line A-A shown in.shows that each of the plurality of permalloy coresmay comprise a magnetic bar in the form of a closed loop having a rectangular shaped loop when seen in a top-down view. The closed loop is disposed such that it encircles the entire perimeter of the integrated circuit die. In other embodiments (not shown in the Figures), the closed loop may have a circular, ovular, triangular, or square shape. In an embodiment, the closed loop may have a width Win the first direction (e.g., along the x-direction) between a first outermost sidewall of the closed loop and a second outermost sidewall of the closed loop, wherein the width Wis in a range from 15 μm to 2400 μm. The closed loop may have a width Win the first direction (e.g., the x-direction) between a first inner sidewall of the closed loop and a second inner sidewall of the closed loop, wherein the width Wis in a range from 5 μm to 2000 μm. The closed loop may have a width Win the second direction (e.g., along the y-direction) between a third outermost sidewall of the closed loop and a fourth outermost sidewall of the closed loop, wherein the width Wis in a range from 15 μm to 1400 μm. The closed loop may have a width Win the second direction (e.g., the y-direction) between a third inner sidewall of the closed loop and a fourth inner sidewall of the closed loop, wherein the width Wis in a range from 5 μm to 1000 μm. In an embodiment, a width Win the first direction between the first outermost sidewall and a nearest inner sidewall to the first outermost sidewall of the closed loop is in a range from 5 μm to 200 μm. A width in the first direction between the second outermost sidewall and a nearest inner sidewall to the second outermost sidewall of the closed loop is equal to W. A width in the second direction between the third outermost sidewall and a nearest inner sidewall to the third outermost sidewall of the closed loop is equal to W. A width in the second direction between the fourth outermost sidewall and a nearest inner sidewall to the fourth outermost sidewall of the closed loop is equal to W. The plurality of conductive viasdisposed within an inner perimeter of the closed loop of the permalloy coreand the plurality of conductive viasdisposed outside an outer perimeter of the closed loop of the permalloy coreform part of a conductive trace of a 3D inductor(shown subsequently in) that is wound around the permalloy core. In an embodiment, a width Wof each of the plurality of conductive viasmay be in a range from 5 μm to 15 μm. In an embodiment, a width Wbetween an inner sidewall of the permalloy coreand a closest sidewall of one of the plurality of conductive viasdisposed within an inner perimeter of the closed loop of the permalloy coremay be in a range from 5 μm to 15 μm. In an embodiment, a width between an outer sidewall of the permalloy coreand a closest sidewall of one of the plurality of conductive viasdisposed outside an outer perimeter of the closed loop of the permalloy coremay be in a range from 5 μm to 15 μm.

illustrates a top view of one of the plurality of permalloy cores, andillustrates a perspective view of the one of the plurality of permalloy cores, in accordance with other embodiments. Unless specified otherwise, like reference numerals in this embodiment (and subsequently discussed embodiments) represent like components in the embodiment shown informed by like processes.shows that each of the plurality of permalloy coresmay comprise a magnetic bar in the form of a closed loop having a rectangular shape when seen in a top-view, wherein outer corners and inner corners of the closed loop may be rounded. In other embodiments, the closed loop may have a toroidal shape.

In, an electrically insulating molding material (or molding compound)is formed over the structure shown in, such as on top surfaces and sidewalls of the plurality of conductive vias, top surfaces and sidewalls of the plurality of permalloy cores, top surfaces and sidewalls of the plurality of integrated circuit dies, sidewalls of the die attach film (DAF), and top surfaces of the dielectric layer. The molding materialcan comprise a dielectric material, such as silicon based material, an epoxy molding compound that includes silica, or the like, that provides electrical isolation between each of the plurality of conductive viasand other structures of the first package component. In an embodiment, a width Wof the molding materialbetween a sidewall of each of the plurality of permalloy coresand a sidewall of a nearest one of the plurality of conductive viasis at least 5 μm. The molding materialcan be formed according to various formation techniques, such as a spin-on process, a deposition process, an injection process, or the like. Excess portions of the molding materialmay then be planarized by grinding and CMP to remove a portion of the molding materialand expose top surfaces of the plurality of conductive vias. During the planarization, a portion of the dielectric layerof each of the plurality of integrated circuit diesmay also be removed so as to expose top surfaces of the die connectors. As illustrated in, the planarization may result in the top surfaces of the plurality of conductive viasand the die connectorsbeing level with a top surface of the molding material. However, top surfaces of the plurality of permalloy coresmay remain covered by the molding materialafter planarization. In an embodiment, after the planarization, a height Hof each of the plurality of conductive viasmay be in a range from 50 μm to 500 μm. In an embodiment, after the planarization, a thickness Tof the molding materialmay be in a range from 50 μm to 500 μm. In an embodiment, after the planarization, a thickness Tof the molding materialabove a top surface of each of the plurality of permalloy coresmay be at least 10 μm. The molding materialhaving a thickness that is smaller than 10 μm above the top surface of each of the plurality of permalloy coreswill lead to insufficient insulation between the plurality of permalloy coresand a subsequently formed upper RDLof a 3D inductor(shown in). This will result in reduced performance and reduced inductance values of the 3D inductor.

Still referring to, a seed layeris formed on top surfaces of the molding material, top surfaces of the plurality of conductive vias, and top surfaces of the plurality of integrated circuit dies. The metal seed layermay comprise, for example, a titanium and copper bilayer (e.g., a layer of copper on a layer of titanium), a singular copper layer, or other suitable metal layer, and may be deposited using a PVD process, a CVD process, an ALD process, or the like. Any suitable thickness may be used for the seed layer. For example, in some embodiments, the seed layermay comprise a titanium layer that is at least 500 Å thick and a copper layer that is at least 3000 Å thick. In other embodiments, the seed layermay comprise other combinations of metals and thicknesses. The seed layeris part of a subsequently formed front-side redistribution structure(see) over the molding material, top surfaces of the plurality of conductive vias, and top surfaces of the plurality of integrated circuit dies.

In, a mask layeris formed on the seed layer. The mask layermay be a photoresist, or the like, and may be formed using a spin coating or deposition process. The mask layeris then patterned using acceptable development and exposure techniques to form openings that expose portions of the seed layerthat overlap the plurality of conductive viasand the plurality of permalloy cores. A conductive material layeris then deposited on the portions of the seed layerthat are exposed by the openings of the mask layer. The conductive materialmay be copper, or the like, that is deposited using a plating process, for example, electroplating, electroless plating, immersion plating, or the like. In an embodiment, a timed electroplating process is used to deposit the conductive material.

In, the mask layermay be removed through a stripping process, an etching process, and/or a cleaning process. In an embodiment, the mask layermay be removed using a solution that comprises dimethyl sulfoxide (DMSO), water (HO), and tetramethyl ammonium hydroxide (TMAH). The TMAH compounds are able to break the cross-linkage of molecules within the mask layer, and the DMSO compounds then dissolve the molecules within the mask layerand facilitate its removal.

Still referring to, after the removal of the mask layer, portions of the seed layerthat were covered by the mask layerare exposed. The exposed portions of the seed layerare removed through an etching process. In some embodiments, the etching process may include an anisotropic etching process such as a dry etch or an isotropic etching process such as a wet etch. In some embodiments, an etchant for the wet etch comprises a combination of hydrogen fluoride (HF), copper (Cu), and ammonia (NH). In other embodiments, the etchant for the wet etch comprises a combination of HF and TMAH. The remaining portions of the seed layerand the overlying conductive materialform an upper redistribution layer (RDL)(which also maybe referred to as a metallization pattern). In an embodiment, a thickness Tof the upper RDLmay be in a range from 5 μm to 50 μm. Portions of the upper RDLare each electrically connected to respective ones of the plurality of conductive vias, and the respective ones of the plurality of conductive viasare electrically connected to a respective portion of the lower RDL, so as to yield a plurality of 3D inductors. Each of the plurality of 3D inductorscomprises a conductive trace that forms a coil that is wound around a top surface, a bottom surface, outer sidewalls and inner sidewalls of each of the plurality of permalloy cores. The conductive trace of each of the plurality of 3D inductorscomprises a portion of the lower RDL, respective ones of the plurality of conductive vias, and a respective portion of the upper RDL.

Advantages can be achieved as a result of the first package componentcomprising a 3D inductorthat includes the permalloy core. The permalloy corecomprises the plurality of vertically stacked alternating layers that include the permalloy layersand the epoxy layers, such that each permalloy layeris disposed between two epoxy layers. The permalloy corecomprises at least eight permalloy layers, wherein the thickness of each permalloy layeris in a range from 1 μm to 50 μm, and the thickness of each epoxy layeris in a range from 1 μm to 10 μm. The permalloy coreis a magnetic bar that is formed to be in the shape of a closed loop (e.g., having a toroidal loop shape, rectangular loop shape, square loop shape, or the like), or may comprise a plurality of closed loops. These advantages include an increased magnetic permeability of the permalloy core, which results in a higher inductance. The permalloy corecomprising a plurality of closed loops also allows for the achievement of increased inductances. Further, the disclosed method may provide a more efficient and more compact 3D inductorthat can be integrated easily into existing processes and provide improved inductor performance with lower manufacturing costs and reduced spacing needs.

In, Additional exemplary processing will now be described for providing additional redistribution layers of the front-side redistribution structure, and conductive connectorsto provide for input/output (I/O) to die circuitry and electrical I/O to each of the plurality of 3D inductors.

In, a dielectric layeris formed over the upper RDLand the molding material, such that the upper RDLis embedded in the dielectric layer. The dielectric layermay be formed using similar processes and comprise similar materials as the dielectric layerthat was described earlier in. In an embodiment, a thickness Tof the dielectric layermay be in a range from 5 μm to 50 μm. A first mask layer (e.g., a photoresist) may be formed over the dielectric layerand subsequently patterned to expose top surfaces of the dielectric layer. A suitable etching process is then performed using the first mask layer as an etching mask to form openings in the dielectric layerthat expose top surfaces of the upper RDLand the die connectors. A first seed layer (not shown in) that may comprise, for example, a titanium and copper bilayer (e.g., a layer of copper on a layer of titanium), a singular copper layer, or other suitable metal layer, and may be deposited using a CVD process, an ALD process, or the like,, may be deposited in the openings, such as on sidewalls of the openings and on the exposed top surfaces of the upper RDLand the die connectors. A first conductive material may then be deposited on the first seed layer in the openings using a plating process, such as electroplating or electroless plating. The first conductive material may comprise copper, titanium, or the like. The first mask layer may then be removed using an acceptable ashing or stripping process.

After the removal of the first mask layer, a planarization step, such as a chemical mechanical polish (CMP), may be performed to remove excess portions of the first seed layer and the first conductive material that are over top surfaces of the dielectric layer. The remaining first seed layer and the first conductive material in the openings forms the vias. The vias may be alternatively referred to as through-insulator-vias or TIVs. Accordingly, top surfaces of the dielectric layerare level with top surfaces of the vias.

A second mask layer (e.g., a photoresist) may then be formed over the dielectric layerand the vias. The second mask layer may be patterned to form openings that expose top surfaces of the vias. A second seed layer is formed in the openings in the second mask layer. The second seed layer may comprise, for example, a Ti/Cu bilayer, a copper layer, or other suitable metal layer, and may be deposited using a PVD process (e.g., sputtering) or the like. A second conductive material may then be deposited on the second seed layer to form redistribution layer (RDL)(sometimes referred to as a metallization pattern). The second conductive material may comprise copper, titanium, or the like, and may be formed using a plating process, such as electroplating or electroless plating. The second mask layer may then be removed using an acceptable ashing or stripping process. The RDLis electrically connected to the plurality of integrated circuit diesand the upper RDLthrough the vias.

Referring further to, a dielectric layeris formed over the dielectric layerand the RDL, such that the RDLis embedded in the dielectric layer. The dielectric layermay be formed using a similar process and similar materials as those described above for the formation of the dielectric layer. Viasare then formed in the dielectric layer, and a redistribution layer (RDL)is formed on the dielectric layerusing similar processes and similar materials as described above for the formation of the viasand the RDL.

After the formation of the RDLand the vias, a dielectric layeris formed over the RDLand the dielectric layer, such that the RDLis embedded in the dielectric layer. The dielectric layermay be formed using similar processes and comprise similar materials as the dielectric layerand the dielectric layerthat were described above. The front-side redistribution structureis shown as an example having three layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the front-side redistribution structure. If fewer dielectric layers and metallization patterns are to be formed, steps and process discussed above may be omitted. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed above may be repeated.

In, the dielectric layeris patterned using acceptable photolithography and etching techniques to form openings in the dielectric layerthat expose top surfaces of the RDL. A conductive metal such as copper, titanium, or the like, is deposited over the dielectric layerand in the openings in the dielectric layerusing for example, sputtering, evaporation, PECVD, or the like. Suitable photolithographic masking and etching process are then used to remove portions of the conductive metal, and the remaining portions of the conductive metal form the under ball metal (UBM) pads. Conductive connectorsare formed on the UBM pads. The conductive connectorsmay be solder balls, metal pillars, metal vias, or the like. The conductive connectorsmay include a conductive material such as solder, or the like. In some embodiments, the conductive connectorsare formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. The conductive connectorsprovide for electrical input/output (I/O) to circuitry of each of the plurality of integrated circuit diesand each of the plurality of 3D inductors.

In, a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substratefrom the back-side redistribution structure, e.g., the dielectric layer. In accordance with some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the release layerso that the release layerdecomposes under the heat of the light and the carrier substratecan be removed. The dielectric layerprovides protection at the bottom side of the first package component. After the carrier substrateis de-bonded from the back-side redistribution structure, a singulation process is then performed by sawing along scribe line regions, e.g., between the first package regionA and the second package regionB. The sawing singulates the first package regionA from the second package regionB. The resulting, singulated device stack is from one of the first package regionA or the second package regionB.

illustrates a top-down view of a cross-section of the first package componentalong a line B-B shown in. As illustrated in, the permalloy coreis separated from the integrated circuit dieand the plurality of conductive viasby the molding material. The plurality of conductive viasdisposed within an inner perimeter of the closed loop of the permalloy coreand the plurality of conductive viasdisposed outside an outer perimeter of the closed loop of the permalloy coreform part of a conductive trace of a 3D inductorthat is wound around the permalloy core.

illustrates a perspective view of a portion of the first package componentshown in. A 3D inductoris shown that comprises a conductive trace that forms a coil that is wound around top surfaces, bottom surfaces, outer sidewalls and inner sidewalls of a permalloy core. The conductive trace of the 3D inductorcomprises portions of the lower RDL, the upper RDL, and the plurality of conductive viaselectrically connected as shown to form an electrically conductive coil that is wound around the permalloy core. The integrated circuit dieis disposed such that a perimeter of the integrated circuit dieis encircled by the closed loop of the permalloy. Electrically conducting inductor connections (ports)andprovide electrical I/O connection to the 3D inductor. The density of coils per unit length of the conductive coil may be selected as desired to provide to provide desired values of inductance.