Modification of Program Voltage Level with Read or Program-Verify Adjustment for Improving Reliability in Memory Devices

This patent application is a continuation of U.S. patent application Ser. No. 18/421,893, filed on Jan. 24, 2024, which claims priority of Provisional Patent Application No. 63/445,812, titled “MODIFICATION OF PROGRAM VOLTAGE LEVEL WITH READ OR PROGRAM-VERIFY ADJUSTMENT FOR IMPROVING RELIABILITY IN MEMORY DEVICES,” filed on Feb. 15, 2023. Both above-referenced applications are incorporated by reference herein.

Embodiments of the disclosure are generally related to memory sub-systems, and more specifically, are related determining voltage offsets for read and program-verify operations.

A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices.

Embodiments of the present disclosure are directed to methods and systems for adjusting voltage offsets of read, program, and program-verify operations based on values of a chosen media endurance metric (e.g., number of program-erase cycles (PEC)) of a memory device. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory sub-system can utilize one or more memory devices, including any combination of the different types of non-volatile memory devices and/or volatile memory devices, to store the data provided by the host system. In some embodiments, non-volatile memory devices can be provided by not-and (NAND) type flash memory devices. Other examples of non-volatile memory devices are described below in conjunction with. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. Planes can be grouped into logic units (LUN). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. A “block” herein shall refer to a set of contiguous or non-contiguous memory pages. An example of a “block” is an “erasable block,” which is a minimal erasable unit of memory, while “page” is a minimal writable unit of the memory device. Each page includes of a set of memory cells. A memory cell is an electronic circuit that stores information.

Data operations can be performed by the memory sub-system. The data operations can be host-initiated operations. For example, the host system can initiate a data operation (e.g., write, read, erase, etc.) on a memory sub-system. The host system can send access requests (e.g., write command, read command) to the memory sub-system, such as to store data on a memory device at the memory sub-system and to read data from the memory device on the memory sub-system. The data to be read or written, as specified by a host request, is hereinafter referred to as “host data.” A host request can include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location the host system associates with the host data. The logical address information (e.g., LBA, namespace) can be part of metadata for the host data. Metadata can also include error handling data (e.g., error correction code (ECC), parity code), data version (e.g., used to distinguish age of data written), valid bitmap (which LBAs or logical transfer units contain valid data), etc. For example, upon reading data from a memory device, the memory sub-system controller can perform an error detection and correction operation. The error detection and correction operation includes identifying one or more errors (e.g., bit flip errors) in the read data. The memory sub-system can have the ability to correct a certain number of errors per management unit (e.g., using an error correction code (ECC)). As long as the number of errors in the management unit is within the ECC capability of the memory sub-system, the errors can be corrected before the data is provided to the requestor (e.g., the host system). The fraction of bits that contain incorrect data before applying ECC is called the raw bit error rate (RBER). The fraction of bits that contain incorrect data after applying ECC is called the uncorrectable bit error rate (UBER).

A memory device includes multiple memory cells, each of which can store, depending on the memory cell type, one or more bits of information. A memory cell can be programmed (written to) by applying a certain voltage to the memory cell, which results in an electric charge being held by the memory cell, thus allowing modulation of the voltage distributions produced by the memory cell. Moreover, precisely controlling the amount of the electric charge stored by the memory cell allows the establishment of multiple threshold voltage levels corresponding to different logical levels, thus effectively allowing a single memory cell to store multiple bits of information. For example, a memory cell operated with 2different threshold voltage levels is capable of storing n bits of information. Thus, the read operation can be performed by comparing the measured voltage exhibited by the memory cell to one or more reference read voltage levels in order to distinguish between two logical levels for single-level cells and between multiple logical levels for multi-level cells. The read reference voltages and the state widths of the threshold voltage distributions determine the edge margins available. The even edges determine the margin for program disturb and over-program, while the odd edges determine the margin for charge loss. The sum of all edge margins is usually defined as the read window budget (RWB). Therefore, a larger window allows larger margins, e.g., to read the cell correctly in the event of charge loss or disturb/over-program.

The reliability of a NAND device, however, decreases with increase in program-erase cycles (PEC). In order to maintain the reliability, some NAND devices employ a step decrease in program voltage based on the number of PEC performed on the memory device. For example, memory blocks with lower number of PEC may employ a larger program voltage offset while memory blocks with higher number of PEC may employ a lower program voltage offset to maintain reliability. Additionally, larger program voltage offsets result in wider threshold voltage distributions and smaller program voltage offset result in tighter threshold voltage distributions, thereby improving reliability of blocks with a high number of PECs. However, this increases the time needed to perform the program operation because more program pulses would be needed to perform the same amount of programming. Additionally, a step decrease in program voltage may also result in an edge sum gain of RWB and lower ideal RBER. For example, the threshold voltage distribution may be aligned at the left edge rather than the center, resulting in even larger edge margin on the left side and slightly smaller edge margin on the right side. This imbalance between even and odd edges may also cause reliability and data retention issues.

Embodiments of the present disclosure address the above-noted and other deficiencies by implementing a memory sub-system that applies a read level adjustment in addition to a step decrease in program voltage associated with a media endurance metric (e.g., the number of PEC) of the memory device. The voltage offset values used for adjusting the read level voltage and/or the program voltage can be stored in the metadata of the memory device, which may be initialized during manufacture of the memory device. In one implementation, the voltage offset values used for adjusting the read level voltage and/or the program voltage can be stored in a look-up table (LUT) that may be stored in the metadata of the memory device. The voltage offset values used for adjusting the read level voltage and/or the program voltage can be determined using threshold voltage (Vt) data that may be collected by performing program operations on the wordlines of the memory device, and generating corresponding threshold voltage (Vt) curves, which may be used to determine the voltage offset values. The values may then be stored in the metadata of the memory device, which may be initialized during the manufacturing process.

In some embodiments, the memory sub-system applies a program-verify level adjustment in addition to a step decrease in program voltage associated with a media endurance metric (e.g., the number of PEC) of the memory device. The voltage offset values used for adjusting the program-verify level voltage and/or the program voltage can be stored in the metadata of the memory device, which may be initialized during manufacture of the memory device. In one implementation, the voltage offset values used for adjusting the program-verify level voltage and/or the program voltage can be stored in a look-up table (LUT) that may be stored in the metadata of the memory device. The voltage offset values used for adjusting the program-verify level voltage and/or the program voltage can be determined using threshold voltage (Vt) data that may be collected by performing one or more program operations on one or more wordlines of the memory device, and generating corresponding threshold voltage (Vt) curves, which may be used to determine the voltage offset values. The values may then be stored in the metadata of the memory device, which may be initialized upon manufacture.

Therefore, advantages of the systems and methods implemented in accordance with some embodiments of the present disclosure include, but are not limited to, improving RBER and reliability for memory blocks with high PECs. The methods disclosed can also improve system performance by reducing folding activities after data retention. The systems and methods disclosed can also slow the process of degradation such that memory blocks reach higher voltage bins slower when compared to the current method of using only step decrease in program voltage.

illustrates an example computing systemthat includes a memory sub-systemin accordance with some embodiments of the present disclosure. The memory sub-systemcan include media, such as one or more volatile memory devices (e.g., memory device), one or more non-volatile memory devices (e.g., memory device), or a combination of such.

A memory sub-systemcan be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory module (NVDIMM).

The computing systemcan be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device (e.g., a processor).

The computing systemcan include a host systemthat is coupled to one or more memory sub-systems. In some embodiments, the host systemis coupled to different types of memory sub-systems.illustrates one example of a host systemcoupled to one memory sub-system. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

The host systemcan include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host systemuses the memory sub-system, for example, to write data to the memory sub-systemand read data from the memory sub-system.

The host systemcan be coupled to the memory sub-systemvia a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, Small Computer System Interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), etc. The physical host interface can be used to transmit data between the host systemand the memory sub-system. The host systemcan further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices) when the memory sub-systemis coupled with the host systemby the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-systemand the host system.illustrates a memory sub-systemas an example. In general, the host systemcan access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections.

The memory devices,can include any combination of the different types of non-volatile memory devices and/or volatile memory devices. The volatile memory devices (e.g., memory device) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device) include negative-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of the memory devicescan include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the memory devicescan include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devicescan be grouped as pages that can refer to a logical unit of the memory device used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.

Although non-volatile memory devices such as 3D cross-point array of non-volatile memory cells and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory devicecan be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-or (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

A memory sub-system controller(or controllerfor simplicity) can communicate with the memory devicesto perform operations such as reading data, writing data, or erasing data at the memory devicesand other such operations. The memory sub-system controllercan include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controllercan be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

The memory sub-system controllercan include a processor(e.g., processing device) configured to execute instructions stored in a local memory. In the illustrated example, the local memoryof the memory sub-system controllerincludes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system, including handling communications between the memory sub-systemand the host system.

In some embodiments, the local memorycan include memory registers storing memory pointers, fetched data, etc. The local memorycan also include read-only memory (ROM) for storing micro-code. While the example memory sub-systeminhas been illustrated as including the controller, in another embodiment of the present disclosure, a memory sub-systemdoes not include a controller, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

In general, the memory sub-system controllercan receive commands or operations from the host systemand can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices. The memory sub-system controllercan be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices. The memory sub-system controllercan further include host interface circuitry to communicate with the host systemvia the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devicesas well as convert responses associated with the memory devicesinto information for the host system.

In some implementations, memory sub-systemcan use a striping scheme, according to which every the data payload (e.g., user data) utilizes multiple dies of the memory devices(e.g., NAND type flash memory devices), such that the payload is distributed through a subset of dies, while the remaining one or more dies are used to store the error correction information (e.g., parity bits). Accordingly, a set of blocks distributed across a set of dies of a memory device using a striping scheme is referred herein to as a “superblock.”

The memory sub-systemcan also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-systemcan include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the controllerand decode the address to access the memory devices.

In some embodiments, the memory devicesinclude local media controllersthat operate in conjunction with memory sub-system controllerto execute operations on one or more memory cells of the memory devices. An external controller (e.g., memory sub-system controller) can externally manage the memory device(e.g., perform media management operations on the memory device). In some embodiments, a memory deviceis a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

The memory sub-systemincludes a memory access manager, which can be used to implement techniques for applying a read level adjustment in addition to a step decrease in program voltage based on the number of PEC performed on the memory device. In some embodiments, the memory access managermay implement a counter (e.g., a PEC counter), which may be incremented every time a program-erase operation is performed on one or more blocks of the memory device. The counter may be stored in the metadata of the memory device, and may be updated each time a program-erase operation is performed on one or more blocks of the memory device. In some embodiments, the memory access managermay receive a request for performing a program operation on one or more blocks of memory device. The memory access managermay then determine, using the counter, the number of PECs that have been performed on the blocks of memory device. Depending on the number of PECs, the memory access managermay assign a voltage offset for performing the program operation. In one implementation, the memory access managermay assign a larger program voltage offset to memory blocks with lower number of PECs and assign a lower program voltage offset to memory blocks with larger number of PECs. In some embodiments, the memory access managermay access an offset look-up table (LUT) that may be stored on one or more memory devices. In some implementations, at least part of the offset LUT can be cached in the local memoryof the memory sub-system controller. The offset LUT can be indexed by a trim, which may include one or more blocks sharing a common characteristic (e.g., a wordline group or a voltage bin number), and a record of the offset LUT specifies a read operation threshold voltage offset associated with a media endurance metric (e.g., a number of PECs) of the memory blocks. In one implementation, the offset LUT may categorize memory blocks based on the number of PECs performed on the block. For example, the offset LUT may categorize memory blocks having PECs of less than Q cycles (e.g., 3000 PECs) in a first column of the offset LUT, between Q cycles and R cycles in a second column, between R cycles and S cycles in a third column, between S cycles and T cycles in a fourth column, and some more than T cycles (e.g., 5000 PECs) in a fifth column, and so on and so forth. The memory access managermay use this offset LUT for adjusting program and read voltage offsets in the memory device.

In some embodiments, the memory access managermay receive a request for performing a program operation on one or more blocks of the memory device. The memory access managermay then identify, based on the PEC counter stored in the metadata of the memory device, the number of PECs that have been performed on the blocks of the memory device, and based on the number of PECs, the memory access managermay assign a voltage offset for performing the program operation on a wordline group. The memory access managermay chose a value for the voltage offset from the offset LUT, which may be in the form of a matrix defined by the number of PECs (columns) and the trim (rows). The “trim” may include one or more blocks sharing a common characteristic (e.g., wordline group or voltage bin). In other words, each voltage offset value in the offset LUT is a vector defined by the trim (e.g., wordline group or voltage bin) (row) and the number of PECs (column). The memory access managermay then perform the program operation on the memory blocks of the wordline groupusing a program voltage adjusted for the voltage offset identified using the offset LUT. For example, if the program voltage is 1.0V and the offset value according to the LUT is −0.5V, then the adjusted program voltage that is used for performing the program operation is 0.5V (1.0V-0.5V). In some embodiments, the memory access managermay, using the LUT, identify a read level associated with a voltage bin of the memory blocks in memory device. Based on the read level of the voltage bin (e.g., Read levels 0-7) and the number of PECs performed on the memory blocks, the memory access managermay assign a read voltage offset (from the LUT) in addition to the program voltage offset. The memory access managermay then perform the read operation on the memory blocks of memory device using a read voltage adjusted for the assigned read voltage offset.

In some embodiments, the voltage offset values used for adjusting the read level voltage and/or the program voltage can be stored in the metadata of the memory device, which may be initialized during manufacture of the memory device. The voltage offset values can be determined using threshold voltage (Vt) data that may be collected by performing one or more program operations on one or more wordlines of the memory device, and generating corresponding threshold voltage (Vt) curves, which may be used to determine the voltage offset values. The values may then be stored in the metadata of the memory device, which may be initialized upon manufacture.

In one implementation, the read voltage offset may be determined by computing, during or upon manufacture of the memory device, a distance between a first edge of a first threshold voltage distribution valley associated with the voltage bin and a second edge of a subsequent threshold voltage distribution valley, and determining the read voltage offset based on a difference between the read level associated with the voltage bin and a center of the distance between the first edge and the second edge.

In some embodiment, the memory access managermay implement techniques for applying a program-verify level adjustment in addition to a step decrease in program voltage based on the number of PEC performed on the memory device. The memory access managermay receive a request for performing a program operation on one or more blocks of memory device. The memory access managermay then determine, using the counter, the number of PECs that have been performed on the blocks of memory device. Depending on the number of PECs, the memory access managermay assign a voltage offset for performing the program operation. In some embodiments, the memory access managermay access an offset look-up table (LUT) that may be stored on one or more memory devices. In some implementations, at least part of the offset LUT can be cached in the local memoryof the memory sub-system controller. The offset LUT can be indexed by a trim (e.g., a wordline group or a voltage bin number), and a record of the offset LUT specifies a program-verify operation threshold voltage offset associated with a media endurance metric (e.g., a number of PECs) of the memory blocks. In one implementation, the offset LUT may categorize memory blocks based on the number of PECs performed on the block. The memory access managermay use this offset LUT for adjusting program and program-verify voltage offsets in the memory device.

In some embodiments, the memory access managermay receive a request for performing a program operation on one or more blocks of the memory device. The memory access managermay then identify, based on the PEC counter stored in the metadata of the memory device, the number of PECs that have been performed on the blocks of the memory device, and based on the number of PECs, the memory access managermay assign a voltage offset for performing the program operation on a wordline group. The memory access managermay chose a value for the voltage offset from the offset LUT, which is vectorized by number of PECs and the trim (e.g., wordline group or voltage bin). In other words, each voltage offset value in the offset LUT is a vector defined by the trim (e.g., wordline group or voltage bin) and the number of PECs. The memory access managermay then perform the program operation on the memory blocks of the wordline groupusing a program voltage adjusted for the voltage offset identified using the offset LUT. In some embodiments, the memory access managermay, using the LUT, identify a program-verify level associated with a voltage bin of the memory blocks in memory device. Based on the program-verify level of the voltage bin (e.g., Program-verify levels 0-7) and the number of PECs performed on the memory blocks, the memory access managermay assign a program-verify voltage offset in addition to the program voltage offset. The memory access managermay then perform the program-verify operation on the memory blocks of memory device using a program-verify voltage adjusted for the assigned program-verify voltage offset.

In some embodiments, the voltage offset values used for adjusting the program-verify level voltage and/or the program voltage can be stored in the metadata of the memory device, which may be initialized during manufacture of the memory device. The voltage offset values can be determined using threshold voltage (Vt) data that may be collected by performing one or more program operations on one or more wordlines of the memory device, and generating corresponding threshold voltage (Vt) curves, which may be used to determine the voltage offset values. The values may then be stored in the metadata of the memory device, which may be initialized upon manufacture. In one implementation, the program-verify voltage offset can be determined by aligning a first center of a first threshold voltage distribution valley applying the program voltage offset with a second center of the first threshold voltage distribution valley without applying the program voltage offset, and determining the program-verify voltage offset based on a difference between the program-verify voltage level associated with the voltage bin and a second edge of the first threshold voltage distribution valley applying the program voltage offset.

schematically illustrates example metadata maintained by the memory sub-system controllerfor associating blocks and/or partitions with voltage bins, in accordance with embodiments of the present disclosure. As schematically illustrated by, the memory sub-system controller can maintain the superblock table, the block table, and the offset table. Each record of the superblock tablespecifies the block associated with the specified superblock and partition combination. In some implementations, the superblock table records can further include time and temperature values associated with the specified superblock and partition combination.

The block tableis indexed by the block number, such that each record of the block tablespecifies, for the block referenced by the index of the record, a set of voltage bins associated with respective dies of the block. In other words, each record of the block tableincludes a vector, each element of which specifies the voltage bin associated with the die referenced by the index of the vector element.

Finally, the offset tableis indexed by the bin number. A record of the offset tablespecifies a set of read operation threshold voltage offsets (e.g., for TLC, MLC, and/or SLC) associated with a voltage bin. Another record specifies a set of bin determination threshold voltage offsets (e.g., for TLC, MLC, and/or SLC) associated with the voltage bin. The metadata tables-can be stored on one or more memory devicesof. In some implementations, at least part of the metadata tables can be cached in the local memoryof the memory sub-system controllerof.

In operation, upon receiving a read command, the memory sub-system controller determines the physical address corresponding to the logical block address (LBA) specified by the read command. Components of the physical address, such as the physical block number and the die identifier, are utilized for performing the metadata table walk: first, the superblock tableis used to identify the block identifier corresponding to the physical block number; then, the block identifier is used as the index to the block tablein order to determine the voltage bin associated with the block and the die; finally, the identified voltage bin is used as the index to the offset tablein order to determine the read operation threshold voltage offset and the bin determination threshold voltage offset corresponding to the bin. The memory sub-system controller can then additively apply the identified read operation threshold voltage offset to the base voltage read level in order to perform the requested read operation.

In the illustrative example of, the superblock tablemaps partition 0 of the superblock 0 to block 4, which is utilized as the index to the block tablein order to determine that die 0 is mapped to voltage bin 3. The latter value is used as the index to the offset table in order to determine the threshold voltage offset values for voltage bin 3.

illustrates an example method of calibrating voltage bins of a memory device based on threshold voltage offset of blocks approaching a transition boundary between voltage bins, in accordance with one or more aspects of the present disclosure. Methodmay be performed by processing logic that includes hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processor to perform hardware simulation), or a combination thereof. In some embodiments, the methodis performed by memory access managerof. In one implementation, graphschematically illustrates a set of voltage bins (e.g., bin 0 to bin 3), in accordance with embodiments of the present disclosure for a selected read level. Threshold voltage offset curveillustrates the dependency of the threshold voltage offset, on the y-axis, on the time after program (which can be time normalized with respect to a particular temperature), the period of time elapsed since the block had been programmed, on the x-axis for the selected read level. In one implementation, blocks of the memory device that have been programmed within a specified time window are assigned to a voltage bin that corresponds to the time after program of the blocks. As noted herein above, given that wear-leveling can keep program/erase cycles similar on all blocks, the time elapsed after programming and temperature of the memory device are the main factors affecting the temporal voltage shift. Using normalized time takes into account the temperature profile and hence temperature information is incorporated. Accordingly, all blocks programmed within a specific time window (i.e., normalized time window) are presumed to exhibit similar distributions of threshold voltages in memory cells, and thus can be assigned to the same voltage bin and can utilize the same voltage offsets for read operations.

In one implementation, a newly programmed block can be associated with bin 0. Then, the memory sub-system controller can periodically perform a foreground or background calibration process in order to associate each die of every block with one of the predefined threshold voltage bins (e.g., bins 0-3 in the illustrative example of), which is in turn associated with the voltage offsets to be applied for read operations. The associations of blocks with voltage bins and dies can be stored in respective metadata tables maintained by the memory sub-system controller, as explained in more details herein with respect to. The threshold voltage offset ofare associated with a single valley. The threshold voltage offset value become more negative going down the y-axis, which corresponds to higher SCL. For each voltage bin, a separate threshold voltage offset can be assigned to each valley.

As schematically illustrated by, graphcan be subdivided into multiple voltage bins, such that each voltage bin corresponds to a predetermined range of threshold voltage offsets based on a corresponding range of TAP of the voltage bin. While the illustrative example ofdefines four voltage bins, in other implementations, various other numbers of voltage bins can be employed (e.g., 7 bins or even 10 bins). Based on a periodically performed calibration process, the memory sub-system controller associates each die of every block with a voltage bin, which defines a set of threshold voltage offsets to be applied to the base voltage read level in order to perform read operations of data of the block, as described in more detail herein below.

Graphofillustrates the process of calibrating voltage bins by assigning a threshold voltage offset to a voltage bin based on a threshold voltage offset of blocks approaching a transition boundary between voltage bins. In an implementation, a processing logic executing methodcan determine a time after program (TAP)corresponding to a transition boundary between bin 1 and bin 2. In an implementation, TAPcan be a specific value of time elapsed since programming a block. In other implementations, TAPcan be a range of values, such that a block having a TAP value that is within the TAPrange can be transitioned from voltage bin 1 to voltage bin 2.

In certain implementations, the processing logic can determine a set of blocks assigned to voltage bin 1 that are approaching boundary TAPbetween voltage bin 1 and voltage bin 2. As an example, the processing logic can determine the set of blocks having a TAP value that is within a predetermined distance from TAP. When the set of blocks approaching the transition boundary corresponding to TAPare determined, the processing logic can determine a threshold voltage offset that is efficient for read operations of the determined set of blocks, to be used as an initial threshold voltage offset for the selected read level of voltage bin 2. In an implementation, a set of efficient threshold voltage offsets (one for each valley) of the set of blocks can be determined by performing read operations of data stored at the set of blocks and determining a set of threshold voltage offsets that result in a minimum bit error rate of the read operations. When the set of threshold voltage offsets of the set of blocks is determined, the processing logic can assign the determined threshold voltage offset set as an initial value of the threshold voltage offsets of the selected read level of voltage bin 2. In an implementation, the processing logic can then assign blocks to voltage bin 2 and can utilize the initial value of the threshold voltage offsets to perform read operations of the newly assigned blocks that are associated with the selected read level. For each voltage bin, the set of read offsets includes one offset per valley, such as 7 offsets for TLC wordlines, for example. Page reads correspond to different valleys and as such can use corresponding read offsets. Read operations used to determine the set of read offsets can use different page types to cover all valleys.

Similarly, the processing logic can determine a TAPcorresponding to a transition boundary between voltage bin 2 and voltage bin 3. In an implementation, TAPcan be a specific value of time elapsed since programming a block. In other implementations, TAPcan be a range of values, such that a block having a TAP value that is within the TAPrange can be transitioned from voltage bin 2 to voltage bin 3. In certain implementations, the processing logic can determine a set of blocks assigned to voltage bin 2 that are approaching boundary TAPbetween voltage bin 2 and voltage bin 3. As an example, the processing logic can determine the set of blocks having a TAP value that is within a predetermined distance from TAP. When the set of blocks approaching the transition boundary corresponding to TAPare determined, the processing logic can determine a set of threshold voltage offsets that are efficient for read operations of the determined set of blocks, to be used as an initial set of threshold voltage offsets for the selected read level of voltage bin 3. When the se of threshold voltage offsets of the set of blocks is determined, the processing logic can assign the determined threshold voltage offset set as an initial value of the threshold voltage offset of the selected read level of voltage bin 3. In an implementation, the processing logic can then assign blocks to voltage bin 3 and can utilize the initial values of the threshold voltage offset to perform read operations of the newly assigned blocks that are associated with the selected read level.

illustrates example methods,for adjusting program voltage based on the number of PECs performed on the memory device, in accordance with one or more aspects of the present disclosure. Methods,may be performed by processing logic that includes hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processor to perform hardware simulation), or a combination thereof. In some embodiments, methods,are performed by the memory access managerof. In one implementation, the method,may include using a counter that may be incremented every time a program-erase operation (e.g., program-erase cycle (PEC)) is performed on one or more memory blocks of the memory device. The methodmay further include assigning a program voltage offsetdepending on the number of PECs already performed on the memory device. For example, blocks with low number of PECs (e.g., 3000 PEC or less) may be assigned a higher program voltage offset. Similarly, in method, blocks with high number of PECs (e.g., more than 3000 PEC) may be assigned a smaller program voltage offset. As illustrated in, blocks with lower number of PECs tend to have wider threshold voltage (Vt) distributions, and blocks with higher number of PECs tend to have tighter threshold voltage (Vt) distributions. The program level adjustment can be determined using threshold voltage (Vt) data collected by performing one or more program operations on one or more wordlines or a portion of a wordline, and generating corresponding threshold voltage (Vt) curves. This process may be repeated several times over one or more wordlines in order to gather sufficient threshold voltage data, generate the threshold voltage distributions, and arrive at the voltage offset values.

illustrates an offset look-up table (LUT), stored in the metadata of the memory device, for adjusting program and read voltage offsets based at least on the number of program-erase cycles (PEC) performed on memory blocks of a memory device, in accordance with some embodiments of the present disclosure. The offset LUTmay be vectorized by number of PECsand the trim(e.g., wordline group or voltage bin). In other words, each voltage offset valuein the offset LUTis a vector defined by the trim(e.g., wordline group or voltage bin) and the number of PECs. The LUTmay categorize the memory blocks based on the number of PECs. For example, the LUTmay include memory blocks with PECs of less than Q (e.g., 3000) PECs, between Q and R, between R and S, between S and T, and some more than T (e.g., 5000) PECs. The memory sub-system controller may use this LUT for adjusting program and read voltage offsets in the memory device. In some embodiments, the memory access managermay receive a request for performing a program operation on one or more blocks of the memory device. The memory access managermay then identify the number of PECsthat have been performed on the blocks of memory device. Based on the number of PECs, the memory access managermay assign a voltage offsetfor performing the program operation on a wordline group. For example, the memory access managermay assign a larger program voltage offset to memory blocks of a wordline group with lower number of PECs and assign a lower program voltage offset to memory blocks of a wordline group with larger number of PECs. The memory access managermay then perform the program operation on the memory blocks of the wordline groupusing a program voltage adjusted for the assigned program voltage offset.

In some embodiments, the memory access managermay, using the LUT, identify a read levelassociated with a voltage bin of the memory blocks in memory device. Based on the read levelof the voltage bin (e.g., Read levels 0-7) and the number of PECsperformed on the memory blocks, the memory access managermay assign a read voltage offsetin addition to the program voltage offset. The memory access managermay then perform the read operation on the memory blocks of memory device using a read voltage adjusted for the assigned read voltage offset.

illustrates example operations in a methodfor determining a voltage offset for performing a program operation on memory blocks of a memory device, in accordance with one or more aspects of the present disclosure. The curves illustrated inand the voltage offset values used for adjusting the read level voltage and/or the program voltage can be stored in the metadata of the memory device, which may be initialized during manufacture of the memory device. The voltage offset values can be determined using threshold voltage (Vt) data that may be collected by performing one or more program operations on one or more wordlines of the memory device, and generating corresponding threshold voltage (Vt) curves, which may be used to determine the voltage offset values. The values may then be stored in the metadata of the memory device, which may be initialized upon manufacture. In one implementation, methodincludes generating threshold voltage distribution valleysusing a program voltage offset (e.g., offset), and generating threshold voltage distribution valleyswithout using a program voltage offset (e.g., offset). First valleyhas a first edgeand a second edge, and second valleyhas a first edge and a second edge. However, when only a program voltage offset is used, the read level voltageis not synchronized with the program level voltage change. As a result, the margin eincreases on one side of the read level and margin eshrinks on the other side of the read level. This may cause reliability and date retention issued in the memory device.