Radical-Activated Etching of Metal Oxides

This application is a continuation application of U.S. patent application Ser. No. 17/694,158, filed on Mar. 14, 2022, titled “Radical-Activated Etching of Metal Oxides,” which is a divisional application of U.S. patent application Ser. No. 17/081,709, filed on Oct. 27, 2020, titled “Radical-Activated Etching of Metal Oxides,” the disclosures of which are incorporated herein by reference in their entireties.

Dry etching is a semiconductor manufacturing process that removes a masked pattern of material by exposing the material to a bombardment of ions. Before etching, a wafer can be coated with photoresist or a hard mask (e.g., oxide or nitride) and exposed to a circuit pattern during a photolithography operation. The etching process can remove material from the pattern traces. This sequence of patterning and etching can be repeated multiple times during the semiconductor manufacturing process.

Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.

In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., +1%, +2%, +3%, +4%, +5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein.

Dry etching is a process used in semiconductor manufacturing. Before etching, a wafer can be coated with a photoresist or a hard mask (e.g., oxide or nitride) and a circuit pattern can be transferred on the photoresist or the hard mask using photolithographic processes (e.g., photo exposure, post exposure bake, develop, hard bake, etc.). An etching process can be subsequently used to remove material from the surface of the wafer that is not covered by the patterned photoresist or hard mask. This sequence of patterning and etching can be repeated multiple times during the semiconductor manufacturing process.

Plasma etching is performed by applying electromagnetic energy (e.g., radio frequency (RF)) to a gas that contains a chemically-reactive element, such as nitrogen trifluoride and hydrogen, to form a plasma. The plasma releases positively-charged ions that can bombard the surface of a wafer to remove, or etch, material. At the same time, chemically-reactive radicals (e.g., atoms or groups of atoms with unpaired electrons) can react with the surface of the wafer to modify surface properties. To improve etch throughput, higher etch rates (e.g., several A/min or nm/min) are desirable.

Process chemistries can differ depending on the types of films to be etched. For example, etch chemistries used in dielectric etch applications can be fluorine-based. Silicon and metal etch applications can use chlorine-based chemistries. An etch operation can include etching one or more film layers from the surface of a wafer. When multiple layers are on the surface of the wafer, for example during the removal of a metal oxide, the etch process is required to remove the metal oxide but preserve other layers (e.g., silicon, silicon oxide, silicon nitride, etc.), the selectivity of the etch process becomes an important parameter. Selectivity of an etch chemistry or an etch process can be defined as the ratio of two etch rates:the rate for the layer to be removed to the rate for the layer to be preserved. In an etch process, high selectivity ratios (e.g., greater than 10:1) are desirable. The ions in the plasma etching can have higher kinetic energies than the radicals. Accordingly, the ions can have a higher etch rate than the radicals. However, the ions can have a lower etch selectivity than the radicals. The term “etch selectivity” can refer to the ratio of the etch rates of two different materials under the same etching conditions. A higher etch rate with higher etch selectivity can be an objective in an etch process.

Various embodiments of the present disclosure provide an exemplary radical-activated thermal atomic layer etching (ALE) process. In some embodiments, the radical-activated thermal ALE process can activate a ligand exchange reaction on a surface of a metal oxide on a wafer using radicals with increased kinetic energies, thereby increasing an etch rate of the metal oxide and increasing the etch selectivity between the metal oxide and adjacent materials on the wafer. The metal oxide can include hafnium oxide, aluminum oxide, zirconium oxide, and other suitable metal oxide dielectric materials.

Atomic layer etching, or ALE, is a technique that can remove thin layers of material from the surface of a wafer using sequential reaction cycles (e.g., duty cycles), for example, during the removal of a metal oxide on one or more dielectric layers. The sequential reaction cycles of an ALE process can be “quasi self-limiting.” In some embodiments, quasi self-limiting reactions may refer to those reactions that slow down as a function of time (e.g., asymptotically), or as a function of species dosage. A radical-activated thermal ALE process can include three sequential reaction cycles: (i) a surface modification cycle, (ii) a material removal cycle, and (iii) a surface cleaning cycle. In some embodiments, a time elapsed between sequential cycles (e.g., between the surface modification cycle and the material removal cycle) is referred to as a “transition time.” During the transition time, reactants/byproducts from a current cycle are removed away from the surface of the wafer, prior to the release of new reactants. Prompt delivery of reactants into the chamber can reduce the transition time between cycles and the cycle duration (cycle time). In a radical-activated thermal ALE process, the reactants can be, for example, delivered by one or more gases, a plasma, a vapor, or other suitable sources.

The surface modification cycle can form a reactive surface layer with a defined thickness from a material on the surface of a wafer that has been exposed to radicals in the surface modification process. In some embodiments, the radical-activated thermal ALE process can modify the surface of the metal oxide layer with radicals generated from a plasma during the surface modification cycle. The modified material layer (reactive surface layer) can be subsequently removed during the next cycle (e.g., material removal cycle). Any unmodified material, which is not exposed to the surface modification chemistry during the surface modification cycle, will not be removed. The modified material, for example, can have a gradient in chemical composition and/or physical structure.

The material removal cycle can include a ligand exchange reaction, which can be performed under a thermal condition. In some embodiments, radicals generated from ions of a plasma having increased kinetic energies can increase the ligand exchange kinetic energies and the speed of the ligand exchange reaction, thus increasing removal of the modified surface of the metal oxide layer and the etching rate of the metal oxide layer. In some embodiments, one or more plates with evenly distributed holes or openings can distribute the gases and plasmas uniformly across the wafer. In some embodiments, the radical-activated thermal ALE system can include a grid system to increase kinetic energies of ions from the plasma and a neutralizer to neutralize the ions and form radicals. The grid system can include a screen grid to screen ions having appropriate angles, an accelerator grid to increase kinetic energies of the ions, and a decelerator grid to reduce divergence of the beam of the ions and block electrons generated by the neutralizer from entering the grid system. The neutralizer can generate electrons and neutralize the ions to form radicals with increased kinetic energies. The material removal cycle can remove the modified material layer while keeping the unmodified material(s) or layers intact. The total amount of material removed can be controlled by the number of repeated cycles (e.g., surface modification cycle, material removal cycle, and surface cleaning cycle).

The surface cleaning cycle can remove surface residues and byproducts from the material removal cycle on the surface of the wafer with a flush of radicals and reset the surface to a near-pristine state for the next etching cycle. The radical flush can further increase the etching rate of the radical-activated thermal ALE process. The radical-activated thermal ALE technique can be used in a variety of etching schemes including, but not limited to, directional or isotropic etching (e.g., formation of air spacers) and selective or nonselective etching (e.g., removal of dielectric layers from an exposed surface).

illustrates a cross-sectional view of an exemplary radical-activated thermal atomic layer etching (ALE) system, in accordance with some embodiments. By way of example and not limitation, radical-activated thermal ALE systemcan include a chamber, a shower headand a wafer holderin chamber, a first gas lineand a second gas lineconnected to chamber, and an electrical sourceconnected to wafer holder. In some embodiments, an inner surface of chambercan be covered with yttrium oxide (YO) to protect chamberfrom plasmas and etch chemistries in the radical-activated ALE process. Shower headcan connect to first gas lineand release gases from first gas lineinto chamber. A pressure in chambercan range from about 3 mTorr to about 4 Torr. In the surface modification cycle, the pressure in chambercan range from about 1 Torr to about 4 Torr. If the pressure is less than about 1 Torr or greater than about 4 Torr, a thickness of modified surface layer may be thinner or thicker than required, respectively. In the material removal cycle, the pressure in chambercan range from about 100 mTorr to about 1000 mTorr. If the pressure is less than about 100 mTorr, the ligand exchange precursors may be decomposed. If the pressure is greater than about 1000 mTorr, the ligand exchange precursors may be condensed on chamber. In the surface cleaning cycle, the pressure in chambercan range from about 20 mTorr to about 200 mTorr. If the pressure is less than about 20 mTorr, metal oxide surfaces may be damaged. If the pressure is greater than about 200 mTorr, byproducts and residues may not be completely cleaned.

Wafer holdercan be an electrostatic wafer chuck and configured to hold a wafer. Wafercan be patterned and have areas of a metal oxide layer on a surface of waferexposed for etching. In some embodiments, the metal oxide layer can include hafnium oxide, aluminum oxide, zirconium oxide, and other suitable metal oxide dielectric materials. Wafer holdercan include a heater (not shown) to heat wafer. In some embodiments, wafercan be heated to a temperature ranging from about 150° C. to about 300° C. for the radical-activated thermal ALE process. If the temperature is less than about 150° C., the ligand exchange reaction may not initiate and the metal oxide layer may not be removed. If the temperature is greater than about 300° C., the radical-activated thermal ALE process may have less etch selectivity between the metal oxide layer and adjacent structures and cause surface damage to the adjacent structures. In some embodiments, wafer holdercan be biased by electrical sourceto provide vertical profile control for a directional etch process. For example, in the surface modification cycle and the surface cleaning cycle, a small amount of ions (e.g., less than about 5%) in radicalscan provide a vertical etch profile and a faster etch rate with bias control by electrical source.

First gas linecan connect to a gas panel, which can provide a gasto chamberto generate radicals for the radical-activated thermal ALE process. In some embodiments, gas panelcan provide gases including fluorine (F), hydrogen fluoride (HF), nitrogen trifluoride (NF), carbon tetrafluoride (CF), trifluoromethane (CHF), hexafluorobutadiene (CF), octafluorocyclobutane (CF), sulfur hexafluoride (SF), hydrogen (H), helium (He), and argon (Ar). In some embodiments, gascan include F, HF, NF, CF, CHF, CF, CF, and SFto generate plasmas and fluorine radicals for modifying the surface of the metal oxide layer. In some embodiments, gascan include inert gases, such as He and Ar, to generate radicals with increased kinetic energies for activing ligand exchange precursors and speeding up ligand exchange reaction. In some embodiments, gascan include Hand He to generate radicals for cleaning the surface of the metal oxide layer after the ligand exchange reaction. In some embodiments, gascan include He for a transition cycle after each cycle of the radical-activated thermal ALE process to pump and purge chamber, preventing intermixing of gases and plasmas of different cycles. In some embodiments, the transition cycle can last from about 30 s to about 60 s. In some embodiments, the plasma and radicals of He can be more effectively pumped and purged than H. In some embodiments, a plasma generator (shown in) can generate plasmas from gasprovided to shower headfrom gas panelthrough first gas line. In some embodiments, plasmas of gascan be generated outside chamberand first gas linecan direct plasmas of gasto shower headin chamber.

Second gas linecan connect to a vaporizerand control a gas flow of a vaporflowing from vaporizerinto chamber. Vaporizercan convert a ligand exchange precursor from liquid to vapor, which can be drawn to chamberby the vacuum in chamber. In some embodiments, a flow rate of vaporcan range from about 50 sccm to about 900 sccm. If the flow rate of vaporis less than about 50 sccm, the modified surface may not be fully removed. If the flow rate of vaporis greater than about 900 sccm, ligand residues may form on the surface of wafer.

Radical-activated thermal ALE systemcan further include a gas distribution plate, a grid system, and a neutralizerin chamber. In some embodiments, gas distribution platecan have evenly distributed openings or concentric openings to uniformly distribute gasdelivered into chamber. Plasma regioncan be formed between gas distribution plateand grid systemby a plasma generator shown in. When gasis delivered to chamberthrough first gas lineand shower head, plasma regioncan be formed including ions and radicals of gas. Grid systemcan include a screen grid, an accelerator grid, and a decelerator grid. Grid systemcan increase kinetic energies of the ions from the plasmas of plasma region. Neutralizercan neutralize the ions with increased kinetic energies and generate radicalswith increased kinetic energies. Radicalswith increased kinetic energies can transfer the kinetic energies to vaporof ligand exchange precursors and generate activated gas regionto react with modified surface of the metal layer on wafer.

illustrates a cross-sectional view of grid systemand neutralizerof radical-activated thermal ALE system, in accordance with some embodiments. As shown in, plasma regioncan be generated between plates of plasma generatorusing a power supply. In some embodiments, power supplycan be a direct current (DC) power supply. Referring to, grid systemcan have screen grid, accelerator grid, and decelerator gridaligned in the path of the ions towards wafer. Screen gridcan be in contact with plasma region. Screen gridcan be biased at a positive voltage relative to a ground to separate ions from plasma regionhaving appropriate angles (e.g., about 90 degrees relative to screen grid). In some embodiments, screen gridcan be biased at a positive voltage ranging from about 500 V to about 2000 V by power supply. Accelerator gridcan be disposed between screen gridand decelerator grid. Accelerator gridcan be biased at a negative voltage related to a ground to accelerate the ions screened by screen grid. In some embodiments, accelerator gridcan be biased at a negative voltage ranging from about −50 V to about −400 V by power supply. A voltage different between accelerator gridand screen gridcan create an electric field to accelerate the ions, thereby increasing kinetic energies of the ions. Decelerator gridcan be disposed between decelerator gridand neutralizer. Decelerator gridcan connect to a ground(e.g., 0 V) through a resistor. Decelerator gridcan reduce divergence of a beam of the accelerated ions and form ion beamwith increased kinetic energies. A voltage different between decelerator gridand accelerator gridcan create another electric field to prevent electrons generated by neutralizer from entering grid system.

Referring to, neutralizercan be disposed after decelerator gridon the path of the ions from plasma region. Neutralizercan generate electronsto neutralize the ions in ion beam. As ion beamincludes ions with increased kinetic energies from grid system, neutralizercan neutralize the ions with electronsand form radicalswith increased kinetic energies. In some embodiments, neutralizercan generate electronsat a rate that balances positive charges of the ions in ion beam.

illustrate top-down views of grid systemof radical-activated thermal ALE system, in accordance with some embodiments.illustrate side views of apertures and ion beams in grid system, in accordance with some embodiments. As shown in, the grids in grid systemcan have apertures evenly distributed on the grids. In some embodiments, as shown in, a diameter Ds of apertureson screen gridcan be larger than a diameter Da of apertureson accelerator grid. And a diameter Dd of the apertures on decelerator gridcan be larger than diameter Da of apertureson accelerator grid. As a result, aperturescan be seen inside aperturesfrom top-down views inwhile the apertures on decelerator gridmay not be seen from top-down views. In some embodiments, diameter Ds can range from about 4 mm to about 7 mm. Diameter Da can range from about 2 mm to about 5 mm. Diameter Dd can range from about 3 mm to about 7 mm. For example, diameter Ds can be about 5 mm, diameter Da can be about 3.5 mm, and diameter Dd can be about 4.5 mm. In some embodiments, a difference δbetween diameters Ds and Da can range from about 0.5 mm to about 4 mm. In some embodiments, as shown in, a different δbetween diameters Dd and Da can range from about 0.5 mm to about 2.5 mm. For example, difference δcan be about 1.5 mm and difference δcan be about 1 mm. Screen gridwith diameter Ds greater than diameter Da of accelerator gridcan increase the number of ions in ion beam. Accelerator gridwith diameter Da less than diameter Ds can accelerate and focus ions in ion beam. In some embodiments, diameter Ds can be greater than, less than, or the same as diameter Dd. In some embodiments, screen gridcan have a thickness Ts along a Z-axis ranging from about 0.3 mm to about 0.8 mm. In some embodiments, accelerator gridcan have a thickness Ta along a Z-axis ranging from about 0.4 mm to about 1 mm. In some embodiments, decelerator gridcan have a thickness Td along a Z-axis ranging from about 0.4 mm to about 1.2 mm. For example, thickness Ts can be about 0.4 mm, thickness Ta can be about 0.5 mm, and thickness Td can be about 0.7 mm. In some embodiments, as shown in, a separation space Sbetween screen gridand accelerator gridalong a Z-axis can range from about 0.4 mm to about 0.6 mm. And a separation space Sbetween accelerator gridand decelerator gridalong a Z-axis can range from about 0.5 mm to about 0.7 mm. For example, separation space Scan be about 0.5 mm and separation space Scan be about 0.6 mm. With the configurations of screen grid, accelerator grid, and decelerator gridas shown in, ions in plasmacan be focused through these grids without direct interception and form ion beam. Misalignment of these grids and out of range for the diameters and thicknesses can lead to direct interception of ion beamon the grids, which can cause erosion to the grids by ions in ion beamwith increased kinetic energies. In some embodiments,illustrate a surface modification cycle and a material removal cycle, respectively, of an exemplary radical-activated thermal ALE process, which are described in detail below.

illustrates methodof radical-activated thermal ALE of a metal oxide, in accordance with some embodiments. Additional operations may be performed between various operations of methodand may be omitted merely for clarity and ease of description. Additional operations can be provided before, during, and/or after method; one or more of these additional processes are briefly described herein. Therefore, methodmay not be limited to the operations described below.

Methodcan be performed by exemplary radical-activated thermal ALE systemshown inand other suitable radical-activated thermal ALE systems. For illustrative purposes, the operations inwill be described with reference to exemplary radical-activated thermal ALE systemshown in. As shown in, radical-activated thermal ALE systemcan include first gas lineto deliver gasfrom gas panelto chamberand second gas lineto deliver vaporto chamber. Shower headcan release gases from first gas lineto chamber. Wafer holdercan hold and heat waferhaving the metal oxide layer on the surface exposed for etching. Plasma generatorcan generate a plasma from gas.

Referring to, methodbegins with operationand the process of generating a plasma from a gas. As shown in, plasma generatorcan generate a plasma in plasma regionfrom a gas. Gascan be delivered from gas panelto shower headin chamberthrough first gas line. Gascan include F, HF, NF, CF, CHF, CF, CF, SF, He, Ar, H, and He to generate plasmas for different cycles of the radical-activated thermal ALE process. Gas distribution platecan have evenly distributed openings or concentric openings to uniformly distribute gasdelivered into chamber. Plasma generatorcan generate a plasma from gasin plasma regionusing power supply.

Referring to, methodcontinues with operationand the process of generating radicals from the plasma with a grid system and a neutralizer. The grid system can include a screen grid, an accelerator grid, and a decelerator grid. As shown in, grid systemcan generate ion beamwith increased kinetic energies from the plasma in plasma region. Neutralizercan generate electronsto neutralize the ions in ion beamand form radicalswith increased kinetic energies. Grid systemcan include screen grid, accelerator grid, and decelerator grid. Screen gridcan be biased at a positive voltage relative to a ground to separate ions from plasma regionhaving appropriate angles (e.g., about 90 degrees relative to screen grid). Accelerator gridcan be biased at a negative voltage related to a ground to accelerate the ions screened by screen grid. After accelerator grid, the ions can have increased kinetic energies. Decelerator gridcan connect to a groundthrough a resistorto reduce divergence of a beam of the accelerated ions and form ion beamhaving increased kinetic energies. In addition, decelerator gridcan prevent electrons generated by neutralizerfrom entering grid system.

Referring to, methodcontinues with operationand the process of activating a ligand exchange reaction on a surface of a metal oxide with the radicals. As shown in, radicalswith increased kinetic energies can transfer kinetic energies to vaporand activate vaporof ligand exchange precursor to form activated gas region. The activated ligand exchange vapors in gas regioncan remove the modified surface of the metal oxide layer on waferand speed up the ligand exchange reaction. In some embodiments, without radicals having increased kinetic energies, the ligand exchange reaction can remove the metal oxide at an etch rate ranging from about 0.1 Å per cycle to about 0.6 Å per cycle. In some embodiments, with radicalshaving increased kinetic energies, the ligand exchange reaction can remove the metal oxide at an etch rate ranging from about 1 Å per cycle to about 5 Å per cycle. In some embodiments, radicalshaving increased kinetic energies can increase the etch rate of the metal oxide by about 3 to about 10 times.

In some embodiments, radicals with increased kinetic energies can be generated in each cycle of the radical-activated thermal ALE process. In the surface modification cycle, the surface of the metal oxide layer on wafercan be fluorinated by fluorine radicals, as shown in. The fluorine radicals can be generated from the plasma of gasthrough grid systemand neutralizer, as shown in. In some embodiments, the metal oxide layer on wafercan include aluminum oxide and gascan include NF, F, HF, CF, CHF, CF, CF, or SFfor the surface modification cycle. In some embodiments, NFplasma can be generated at a pressure ranging from about 1 Torr to about 4 Torr with a power ranging from about 400 W to about 700 W. NFgas flow rate can range from about 100 sccm to about 500 sccm. A gas flow rate of Hor He can range from about 1000 sccm to about 3000 sccm. A temperature of wafer holdercan range from about 250° C. to about 300° C. for the surface modification cycle. In some embodiments, a plasma of F, HF, CF, CHF, or SFcan be generated at a pressure ranging from about 0.1 Torr to about 2 Torr with a flow rate ranging from about 100 sccm to about 500 sccm. The plasma power can range from about 500 W to about 800 W. A gas flow rate of Hor He can range from about 500 sccm to about 4000 sccm. In some embodiments, a plasma of CFor CFcan be generated at a pressure ranging from about 30 mTorr to about 200 mTorr with a flow rate ranging from about 10 sccm to about 50 sccm. The plasma power can range from about 500 W to about 900 W. A gas flow rate of Hor He can range from about 500 sccm to about 200 sccm.

Grid systemcan generate ions with increased kinetic energy and neutralizercan generate electrons to neutralize the ions and form radicalswith increased kinetic energy for the surface modification cycle. In some embodiments, screen gridcan be biased at about 1.2 kV. Accelerator gridcan be biased at a voltage ranging from about −100 V to about −400 V. Decelerator gridcan be connected to ground. Neutralizercan generate electrons with a discharge current ranging from about 0.2 amperes (A) to about 0.5 A and a mass flow rate ranging from about 0.2 mg/s to about 0.25 mg/s to neutralize the ions and form radicalswith increased kinetic energies. As radicals can have higher etch selectivity than ions, radicalswith increased kinetic energies can increase etch selectivity between the metal oxide and adjacent structures (e.g., a mask layer) and prevent surface damage to the adjacent structures.

An etch time of the surface modification cycle can range from about 10 s to about 30 s and a depth of fluorinated metal oxide on the surface of the metal oxide layer can range from about 3 Å to about 30 Å after the surface modification cycle. If the depth of fluorinated metal oxide is less than about 3 Å, the surface of the metal oxide layer may not be fully fluorinated for the ligand exchange reaction. If the depth of fluorinated metal oxide is greater than about 30 Å, the fluorinated metal oxide may not be fully removed by the ligand exchange reaction and ligand residues and byproducts may remain on the surface after the ligand exchange reaction. In some embodiments,illustrates a surface modification cycle of an exemplary radical-activated thermal ALE process using fluorine radicals to fluorinate the surface of the metal oxide layer on wafer.

The surface modification cycle can be followed by the material removal cycle. The fluorinated metal oxide on the surface of the metal oxide layer can be removed by a ligand exchange reaction, as shown in. In some embodiments, gascan include Hor an inert gas, such as He and Ar, at a flow rate ranging from about 1000 sccm to about 5000 sccm. In some embodiments, a plasma of H, He, or Ar can be generated at a pressure ranging from about 100 mTorr to about 1000 mTorr. The plasma can be generated by a plasma source with a pulsing power ranging from about 250 W to about 500 W and a duty cycle from about 10% to about 80%.

Grid systemcan generate ions with increased kinetic energy from gasand neutralizercan generate electrons to neutralize the ions and form radicalswith increased kinetic energy for the ligand exchange reaction. In some embodiments, screen gridcan be biased at about 1.2 kV. Accelerator gridcan be biased at a voltage ranging from about −50 V to about −600 V. Decelerator gridcan be connected to ground. Neutralizercan generate electrons with a discharge current ranging from about 0.2 A to about 0.5 A and a mass flow rate ranging from about 0.2 mg/s to about 0.25 mg/s to neutralize the ions and form radicalswith increased kinetic energies. Radicalswith increased kinetic energies can transfer kinetic energies to vaporof ligand exchange precursor and form activated gas region, speeding up the ligand exchange reaction at the surface of the metal oxide layer.

In some embodiments, the ligand exchange reaction can be performed at a temperature ranging from about 250° C. to about 300° C. and a temperature of wafer holdercan range from about 250° C. to about 300° C. In some embodiments, vaporcan include metal precursors, such as trimethyl-aluminum chloride (Al(CH)or TMA), diethyl-aluminum chloride ((AlCl(CH)or DMAC), tin (II) acetylacetonate (Sn(acac)), silicon tetrachloride (SiCl), and boron trichloride (BCl). In some embodiments, vaporcan have a flow rate ranging from about 50 sccm to about 900 sccm. In some embodiments, a time of the ligand exchange reaction in material removal cycle can range from about 10 s to about 50 s and the ligand exchange reaction can remove the fluorinated metal oxide on the surface of the metal oxide layer with a thickness ranging from about 3 Å to about 30 Å. If the time of the ligand exchange reaction is less than about 10 s, some of the fluorinated metal oxide may not be removed. If the time of the ligand exchange reaction is greater than about 50 s, ligand residues and byproducts may be formed on the surface of the metal layer after the fluorinated metal oxide are removed. In some embodiments,illustrates a material removal cycle of an exemplary radical-activated thermal ALE process using hydrogen radicals to increase kinetic energies of ligand exchange precursor.

The material removal cycle can be followed by the surface cleaning cycle. The surface cleaning cycle can remove ligand residues and byproducts on the surface of the metal oxide layer with hydrogen or helium radicals and create a fresh surface for the next etching cycle, as shown in. In some embodiments, gascan include Hor He at a flow rate ranging from about 100 sccm to about 1000 sccm. In some embodiments, a plasma of Hor He can be generated at a pressure ranging from about 20 mTorr to about 200 mTorr. The plasma can be generated by a plasma source with a pulsing power ranging from about 150 W to about 400 W and a duty cycle from about 10% to about 80%. In some embodiments, a temperature of wafer holdercan range from about 250° C. to about 300° C. for the surface cleaning cycle. In some embodiments, a time of the surface cleaning cycle can range from about 10 s to about 30 s to remove the ligand residues and byproducts on the surface of the metal oxide layer by the hydrogen or helium radicals with increased kinetic energies. If the time of the surface cleaning cycle is less than about 10 s, the ligand residues and byproducts may remain on the surface of the metal oxide layer and they can block the next cycle of surface modification. If the time of the surface cleaning cycle is greater than about 30 s, exposed areas of other materials (e.g., silicon oxide, silicon nitride, silicon, etc.) may be damaged.

Grid systemcan generate ions with increased kinetic energy from gasand neutralizercan generate electrons to neutralize the ions and form radicalswith increased kinetic energy for the surface cleaning cycle. In some embodiments, screen gridcan be biased at about 1.2 kV. Accelerator gridcan be biased at a voltage ranging from about −50 V to about-200 V. Decelerator gridcan be connected to ground. Neutralizercan generate electrons with a discharge current ranging from about 0.2 A to about 0.5 A and a mass flow rate ranging from about 0.2 mg/s to about 0.25 mg/s to neutralize the ions and form radicalswith increased kinetic energies. As radicals can have higher etch selectivity than ions, radicalswith increased kinetic energies can increase etch selectivity between the metal oxide and adjacent structures (e.g., a mask layer) and prevent surface damage to the adjacent structures. As a result, radicalscan remove the ligand residues and byproducts on the surface of metal oxide layer and create a fresh surface without damaging the adjacent structures.

illustrates an isometric view of semiconductor deviceafter the formation of epitaxial fin structures, in accordance with some embodiments.illustrate partial cross-sectional views along line B-B of semiconductor deviceinat various stages of its fabrication process to form air spacersusing the radical-activated thermal ALE process described above, in accordance with some embodiments. Semiconductor devicecan include planar metal oxide semiconductor field-effect transistors (MOSFETs) or fin field effect transistors (finFETs). As shown in, semiconductor devicecan be formed on a substrateand can include finFETsA-C. In some embodiments, finFETsA-C can be all p-type finFETs (PFETs) or n-type finFETs (NFETs) or a combination of each type of finFETs. Though three finFETs are shown in, and subsequent figures, semiconductor devicecan have any number of finFETs. The discussion of elements of finFETsA-C with the same annotations applies to each other, unless mentioned otherwise. In addition, semiconductor devicecan be incorporated into an integrated circuit through the use of other structural components, such as gate contact structures, conductive vias, conductive lines, dielectric layers, and passivation layers, which are not shown for the sake of clarity.

As shown in, semiconductor devicecan further include shallow trench isolation (STI) region, fin structures, epitaxial fin structures, sacrificial gate structures, hard mask layer, and gate spacersdisposed on opposite sides of sacrificial gate structures. STI regioncan be configured to provide electrical isolation between finFETsA-C from each other and from neighboring finFETs with different fin structures (not shown) on substrateand/or neighboring active and passive elements (not shown) integrated with or deposited on substrate. Fin structuresof semiconductor devicecan extend along an X-axis and through finFETsA-C. Fin structurescan include fin bottom portionA and fin top portionB disposed on fin bottom portionA. Epitaxial fin structurescan be grown on portions of fin bottom portionA that are not underlying sacrificial gate structures. Sacrificial gate structurescan be formed on fin structuresover substrate. Gate spacerscan be disposed on sidewalls of sacrificial gate structuresto protect sacrificial gate structuresduring the formation of epitaxial fin structures. In some embodiments, gate spacerscan include a first gate spacerand a second gate spacer. A hard mask layercan be disposed on sacrificial gate structuresto protect sacrificial gate structuresduring various processing operations (e.g., during formation of gate spacersand/or epitaxial fin structures). In some embodiments, hard mask layercan include a nitride layerand an oxide layerfor profile control of sacrificial gate structures. In some embodiments, protective oxide layerscan be disposed between fin structuresand sacrificial gate structures.

The formation of epitaxial fin structurescan be followed by removal of gate spacersand deposition of a third gate spacer, as shown in. According to some embodiments, gate spacerscan be damaged (e.g., partially etched off) during the formation of epitaxial fin structures. As a result, gate spacerscan be removed after the formation of epitaxial fin structuresand third gate spacercan be deposited on sidewalls of sacrificial gate structureshaving improved structural integrity and few defects than damaged gate spacers. In some embodiments, third gate spacercan have a thickness ranging from about 2 nm to about 3 nm and include dielectric materials similar to first gate spacer. The deposition of third gate spacercan be followed by deposition of an aluminum oxide layer, as shown in. Aluminum oxide layercan be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or other suitable deposition methods. In some embodiments, aluminum oxide layercan be deposited by ALD at a temperature ranging from about 180° C. to about 300° C. using aluminum precursors, such as TMA. In some embodiments, aluminum oxide layercan have a thickness ranging from about 2 nm to about 4 nm.

The deposition of aluminum oxide layercan be followed by removal of a portion of aluminum oxide layer, as shown in. Referring to, a portion of aluminum oxide layercan be removed by the radical-activated thermal ALE process discussed above using radical-activated thermal ALE systemshown in. The radical-activated thermal ALE process can be a directional etching process and remove aluminum oxide layerover hard mask layerand epitaxial fin structuresto form aluminum oxide layer*. After the radical-activated thermal ALE process, aluminum oxide layer* can remain on sidewalls of sacrificial gate structures. In some embodiments, the radical-activated thermal ALE process can remove the portion of aluminum oxide layerat a higher etching rate ranging from about 1 Å to about 5 Å per etching cycle. In addition, the radical-activated thermal ALE process can prevent third gate spacerfrom surface damage during the removal of the portion of aluminum oxide layer.

The removal of a portion of aluminum oxide layercan be followed by the formation of etch stop layerand inter-layer dielectric (ILD), as shown in. The formation of etch stop layerand ILDcan include deposition of an etch stop layer and inter-layer dielectric materials followed by a chemical mechanical polishing (CMP) process to coplanarize top surfaces of etch stop layer, ILD, aluminum oxide layer*, third gate spacer*, and nitride layer*. In some embodiments, the CMP process can stop on nitride layer*. The formation of etch stop layerand ILDcan be followed by removal of a portion of ILDand etch stop layer, as shown in.

The removal of a portion of ILDand etch stop layercan be followed by removal of a portion of aluminum oxide layer* on sidewalls of sacrificial gate structures, as shown in, according to some embodiments. Referring to, a portion of aluminum oxide layer* can be removed by the radical-activated thermal ALE process discussed above using radical-activated thermal ALE systemshown in. The radical-activated thermal ALE process can remove exposed aluminum oxide layer* on sidewalls of sacrificial gate structuresto form aluminum oxide layer**. In some embodiments, the radical-activated thermal ALE process can remove the portion of aluminum oxide layer* at a higher etching rate ranging from about 1 Å to about 5 Å per etching cycle. In addition, the radical-activated thermal ALE process may prevent etch stop layer*, ILD*, third gate spacer*, and nitride layer* from surface damage during the removal of the portion of aluminum oxide layer*.

The removal of the portion of aluminum oxide layer* on sidewalls of sacrificial gate structurescan be followed by formation of a hard mask layer, as shown in. The formation of hard mask layercan include blanket deposition of dielectric materials for hard mask layerfollowed by a CMP process. The CMP process can stop on sacrificial gate structures* and coplanarize top surfaces of sacrificial gate structures*, third gate spacer**, and hard mask layer. The formation of hard mask layercan be followed by removal of a portion of sacrificial gate structures*, third gate spacer**, and aluminum oxide layer**. In some embodiments, a portion of sacrificial gate structures* can be removed by an etching process (e.g., a Frontier etching process) and sacrificial gate structuresof the remaining portion can have a height along a Z-axis ranging from about 10 nm to about 15 nm after the etching process. In some embodiments, a portion of third gate spacer** and aluminum oxide layer** can be removed from sidewalls and form third gate spacerand aluminum oxide layerhaving top surfaces aligned with sacrificial gate structures.

In some embodiments, the portion of aluminum oxide layer** can be removed by the radical-activated thermal ALE process discussed above using radical-activated thermal ALE systemshown in. The radical-activated thermal ALE process can remove the portion of aluminum oxide layer** on sidewalls to form aluminum oxide layer. After the radical-activated thermal ALE process, aluminum oxide layercan have top surfaces aligned with sacrificial gate structures. In some embodiments, the radical-activated thermal ALE process can remove the portion of aluminum oxide layer** at a higher etching rate ranging from about 1 Å to about 5 Å per etching cycle. In addition, the radical-activated thermal ALE process may prevent third gate spacer, sacrificial gate structures, etch stop layer*, and hard mask layerfrom surface damage during the removal of aluminum oxide layer**.

The removal of a portion of third gate spacer** and aluminum oxide layer** from sidewalls can be followed by a deposition of an oxide layer, as shown in. In some embodiments, oxide layercan be blanket deposited by an ALD process on top surfaces of the structures in. The deposition of oxide layercan be followed by a removal of a portion of oxide layerand removal of sacrificial gate structures, as shown in. In some embodiments, the removal of a portion of oxide layercan include a directional etching process and oxide layer* on sidewalls can remain after the directional etching process. Sacrificial gate structurescan be exposed for subsequent removal after the directional etching process. In some embodiments, the removal of sacrificial gate structurescan include an etching process (e.g., a Selis etching process) with a nitrogen-based chemistry. Openingscan be formed after the removal of sacrificial gate structures.

The removal of sacrificial gate structurescan be followed by the formation of gate structures, as shown in. Gate structurescan be formed on fin structuresin openings. In some embodiments, each of gate structurescan include a gate dielectric layerand a gate electrode. Gate electrodecan further include a work function layerand a metal fill. In some embodiments, gate dielectric layercan include an interfacial layer and a high-k dielectric layer. In some embodiments, work function layercan include a stack of work function layers. In some embodiments, the formation of gate structurescan include deposition of each layer of gate structuresfollowed by a CMP process and an etching back process.

The formation of gate structurescan be followed by blanket deposition of aluminum oxide layerand amorphous silicon, as shown in. A CMP process can coplanarize top surfaces of aluminum oxide layer, amorphous silicon, etch stop layer*, and ILD*. A cut process can separate gate structuresas required by a design. Amorphous siliconcan be removed following the cut process to form openingsshown in.illustrates an enlarged view of region B in. The removal of amorphous siliconcan be followed by removal of aluminum oxide layerand aluminum oxide layer. Air gapscan be formed after the removal of aluminum oxide layer.

In some embodiments, aluminum oxide layerand aluminum oxide layercan be removed by the radical-activated thermal ALE process discussed above using radical-activated thermal ALE systemshown in. The radical-activated thermal ALE process can remove aluminum oxide layerafter the removal of amorphous silicon. The radical-activated thermal ALE process can further remove aluminum oxide layerbetween etch stop layer** and third gate spacerto form air gaps. In some embodiments, the radical-activated thermal ALE process can remove aluminum oxide layerand aluminum oxide layerat a higher etching rate ranging from about 1 Å to about 5 Å per etching cycle. In addition, the radical-activated thermal ALE process may prevent third gate spacer, ILD** and etch stop layer** from surface damage during the removal of aluminum oxide layerand aluminum oxide layer.

The removal of aluminum oxide layerand aluminum oxide layercan be followed by formation of capping structures, as shown in.illustrates an enlarged view of region B in. The formation of capping structurescan include deposition of dielectric materials capping on gate structuresand sealing air gapsto form air spacers. In some embodiments, air spacerscan have a width along an X-axis ranging from about 2 nm to about 4 nm and a depth along a Z-axis ranging from about 16 nm to about 25 nm. An aspect ratio of the height to the width for air spacerscan range from about 4 to about 12. The formation of capping structuresand air spacerscan be followed by formation of source/drain (S/D) contact structuresin contact with epitaxial fin structures, as shown in. Referring to, S/D contact structurescan include a silicide layer, a metal liner, and a metal contact. In some embodiments, an epitaxial fin structuresof a finFET may not be connected to an S/D contact structure and ILD** can remain on epitaxial fin structures, as shown in. In some embodiments, ILD** can be removed and epitaxial fin structuresof a finFET can be connected to S/D contact structures, as shown in. In some embodiments, air spacerscan reduce parasitic capacitances between gate structuresand S/D contact structuresand improve device performance of semiconductor device.