Novel Self-Aligned via Structure by Selective Deposition

This application is a continuation of U.S. patent application Ser. No. 18/361,567, filed Jul. 28, 2023, which is a continuation of U.S. patent application Ser. No. 17/193,595, filed Mar. 5, 2021, the entire contents of which are incorporated herein by reference for all purposes.

The present disclosure generally relates to semiconductor devices, and particularly to interconnect structures and methods for their fabrication.

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. As technology has progressed, the demand for smaller semiconductor devices with improved performance has increased. As feature densities increase, the widths of the conductive lines and the spacing between the conductive lines of back-end of line (BEOL) multi-layer interconnect structures also need to scale smaller.

Multi-layer metal interconnects are often formed using damascene processes rather than by direct etching. Damascene processes are typically either single or dual damascene, which includes forming openings by patterning and etching inter-metal dielectric (IMD) layers and vias and filling the openings with metal. However, as critical dimension and pitch continue to scale down, there are some challenges in aligning the connecting vias with the metal lines.

To accommodate these smaller scale of the back-end of line, there is a need for an improved metal interconnect, and a method of forming thereof.

As critical dimensions (CD) shrink, new methods of forming multi-layer interconnects are needed. For instant, as pitch shrinks and CD dielectric spacing shrinks below 12 nm, optical overlay control within 6 nm ceases to be effective. Lack of control can result in problems such as overlay (OVL) shift and CD enlargement.

In cases where via landing deviates due to problems such as OVL shift and CD enlargement, performance may be negatively affected. Such problems as degradation of via-to-line breakdown, line-to-line breakdown, line-to-line leakage, and time-dependent gate oxide breakdown (TDDB) are likely to occur. In order to mitigate such problems using conventional schemes, more and more complicated etch processes with dry-wet-dry-wet etch are needed. Hence, improved structures and methods of via alignment are necessary for shrinking multilayer interconnects. Disclosed herein are novel structures and methods for forming self-aligned via structures by selective deposition.

The resulting structure may exhibit self-alignment of the via structure to the bottom metal layer. The self-aligned via structure may have the advantages of increased reliability, lower RC performance and lower capacitance. In the case of lithography misalignment, the upper portion of the via may remain self-aligned with the top conductive region while the bottom portion of the via may remain self-aligned with the lower conductive region. As such, the structure may be more tolerant of lithography misalignment.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The present disclosure provides various embodiments of a semiconductor device formed by a multi-level interconnect structure and methods of producing the same. The multi-level interconnect structure, which may include a metal such as copper, may be formed by a damascene process. The semiconductor device may be included in a microprocessor, memory cell, and/or other integrated circuit (IC). It is noted that the method ofdoes not produce a completed semiconductor device. A completed semiconductor device may be fabricated using complementary metal-oxide-semiconductor (CMOS) technology processing. Accordingly, it is understood that additional processes may be provided before, during, and after the methodof, and that some other processes may only be briefly described herein. Also,are simplified for a better understanding of the present disclosure. For example, although the figures illustrate the semiconductor device, it is understood the IC may comprise a number of other devices comprising transistors, resistors, capacitors, inductors, fuses, etc.

is a flowchart illustrating a methodfor fabricating a semiconductor device, according to various aspects of the present disclosure.show schematic cross-sectional views of the semiconductor device at various stages of fabrication according to an embodiment of the methodof.

Referring to, the methodproceeds to stepin which a semiconductor substrateincluding a metal (n)conductive region formed in a dielectricmaterial is secured. The semiconductor substrateis a substrate as employed in a semiconductor integrated circuit fabrication, and integrated circuits may be formed therein and/or thereupon. The term “semiconductor substrate” as used herein refers to as any construction comprising semiconductor material, for example, a silicon substrate with or without an epitaxial layer, a silicon-on-insulator substrate containing a buried insulator layer, or a substrate with a silicon germanium layer. The term “integrated circuits” as used herein refers to electronic circuits having multiple individual circuit elements, such as transistors, diodes, resistors, capacitors, inductors, and other active and passive semiconductor devices.

As shown, a conductive regionmay be part of the semiconductor substrate(e.g., in the semiconductor substrateexposed by recessing to form the conductive region). The conductive regionmay be formed in and/or on the dielectric layer. The dielectric layermay be formed on substratein some embodiments. The conductive regionmay be a portion of conductive routes and have exposed surfaces that may be treated by a planarization process, such as chemical mechanical polishing (CMP). Suitable materials for the conductive regionmay include, but are not limited to, for example copper, aluminum, copper alloy, or other mobile conductive materials. The semiconductor substratecontaining such a metal conductive regionmay be the first or any subsequent metal interconnect level of the semiconductor device. The conductive region may be capped. The cap may enhance reliability.

The dielectric layermay be a single layer or a multi-layered structure. In some embodiments, the dielectric layerthickness varies with the applied technology, for example a thickness of about 1000 angstroms to about 30000 angstroms. In some embodiments, the dielectric layeris silicon oxide, carbon-doped silicon oxide, a comparatively low dielectric constant (k value) dielectric material with a k value less than about 4.0, or combinations thereof. In some embodiments, the dielectric layeris formed of a material, including low-k dielectric material, extreme low-k dielectric material, porous low-k dielectric material, and combinations thereof. The term “low-k” is intended to define a dielectric constant of a dielectric material of 3.0 or less. The term “extreme low-k (ELK)” means a dielectric constant of 2.5 or less, and preferably between 1.9 and 2.5. The term “porous low-k” refers to a dielectric constant of a dielectric material of 2.0 or less, and preferably 1.5 or less. A wide variety of low-k materials may be employed in accordance with embodiments, for example, spin-on inorganic dielectrics, spin-on organic dielectrics, porous dielectric materials, organic polymer, organic silica glass, FSG (SiOF series material), HSQ (hydrogen silsesquioxane) series material, MSQ (methyl silsesquioxane) series material, or porous organic series material. In some embodiments, the dielectric layeris deposited through any of a variety of techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), remote plasma enhanced chemical vapor deposition (RPECVD), liquid source misted chemical deposition (LSMCD), coating, spin-coating or another process that is adapted to form a thin film layer over the substrate.

In embodiments, the dielectric layeris a nitrogen-containing layer, a carbon-containing layer, or a carbon-containing and nitrogen-containing layer. In one embodiment, the dielectric layeris a silicon-containing and nitrogen-containing dielectric layer. In another embodiment, the dielectric layeris a silicon-containing and carbon-containing dielectric layer. In yet another embodiment, the dielectric layeris a silicon-containing, nitrogen-containing, and carbon-containing dielectric layer. In one embodiment, the dielectric layerhas a ratio by weight of carbon to silicon about equal or greater than 0.5. In another embodiment, the dielectric layerhas a ratio by weight of nitrogen to silicon about equal or greater than 0.3. In yet another embodiment, the dielectric layerhas a ratio by weight of carbon to silicon about equal or greater than 0.5 and a ratio by weight of nitrogen to silicon about equal or greater than 0.3.

Referring to, the methodproceeds to stepin which an inhibitormay be selectively deposited on conductive region. The conductive regionmay be metal and the inhibitor may be deposited on the metal. The metal may be capped with a metal capping layer. The capping layer may be formed by ion implantation, plasma treatment, gas soak, or many others. The capping layer may be an alloy of the conductive region or consist of molecules made of elements such as Cu, Si, N, C, O, or many other commonly used capping layers. The inhibitor may be deposited on the metal capping layer. The inhibitormay form an inhibitor blocking layer.

The inhibitor blocking layermay be a self-assembled monolayer (SAM). The self-assembled monolayer may have one or more of an anchor group, a tail, and a functional end group. The anchor group may include phosphorous, sulfur, silicon, carbon, or nitrogen. The anchor group may include thiols, silanes, or phosphonates. The inhibitor blocking layermay be made up of molecules such as benxotriazole (BTA).

The inhibitor blocking layermay be deposited using a dry technique such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or vapor ALD. The inhibitor blocking layermay be deposited using a catalyzed growth technique. The inhibitor blocking layermay be deposited using any of LPCVD (low-pressure chemical vapor deposition), APCVD (atmospheric-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), sputtering, and future-developed deposition procedures.

The inhibitor blocking layermay be deposited using wet techniques such as spin-on, dipping, or spraying approaches. For instance, the inhibitor blocking layermay be a composition that will bind to exposed groups on the conductive region. For instance, the inhibitor blocking layermay include a thiol functional group that may bind selectively to the conductive region. In some cases the surface of the conductive regionmay be pretreated to form groups to selectively bind to groups on the inhibitor blocking layer. In some cases, the wafer may be washed after deposition on the inhibitor blocking layersuch that the inhibitor blocking layeronly remains in the regions over the conductive region

In some embodiments the surface of the conductive regionmay be treated to allow for deposition of the inhibitor blocking layer. In some embodiments, the treatment process can be configured to treat or otherwise modify a top boundary of the conductive region. The treatment gas may react with atoms of the conductive region. For example, the treatment process can include a hydrogen (H) plasma process, used to supply hydrogen for the bonds between the conductive regionand hydrogen, by flowing hydrogen gas or precursor into a vacuum (airtight) chamber. In another example, the treatment process can include a nitrogen (N) plasma process, used to supply nitrogen for the bonds between the conductive regionand nitrogen, by flowing nitrogen gas or precursor into a vacuum (airtight) chamber. In yet another example, the treatment process can include an ammonia (NH) plasma process, used to supply nitrogen and/or hydrogen for the bonds between conductive regionand nitrogen and/or hydrogen, by flowing nitrogen gas or precursor into a vacuum (airtight) chamber. In yet another example, the treatment process can include an oxygen (O) plasma treatment, used to supply oxide bonds. In yet another example, the treatment process may include a soaking process, used to soak the conductive region, by flowing corresponding gas or precursor into a vacuum (airtight) chamber, without forming plasma. In some embodiments, the gas soak may be a gas such as H, N, NH, CO, O, air, or mixtures of these. In some embodiments the deposition or treatment may be at room temperature. In some embodiments the deposition or treatment may be at a temperature above room temperature.

Treatments for the inhibitor blocking layermay include dry approaches such gas soak or plasma treatment. In some embodiments treatment may include wet approaches such as an acid clean, solution clean, or wet etch.

Referring to, the methodproceeds to stepin which a dielectricmay be selectively deposited in the region where the inhibitoris not deposited. The dielectricmay be deposited over the dielectricand not deposited over the conductive regionover which has been deposited the inhibitor. The dielectricmay be a single layer or a multi-layered structure. In some embodiments, the dielectricthickness may be about 5 angstroms. In some embodiments, the dielectricthickness may between about 5 angstroms to about 70 nanometers. In some embodiments, the dielectricis silicon oxide, carbon-doped silicon oxide, a comparatively low dielectric constant (k value) dielectric material with a k value less than about 4.0, or combinations thereof. In some embodiments, the dielectric layeris formed of a material, including low-k dielectric material, extreme low-k dielectric material, porous low-k dielectric material, and combinations thereof. A wide variety of materials may be employed in accordance with embodiments, for example, lower dielectric constant materials composed of Si, O, oxide, nitride, or carbide composite films. Examples of possible embodiments may include spin-on inorganic dielectrics, spin-on organic dielectrics, porous dielectric materials, organic polymer, organic silica glass, FSG (SiOF series material), HSQ (hydrogen silsesquioxane) series material, MSQ (methyl silsesquioxane) series material, or porous organic series material. In some embodiments, the dielectricis deposited through any of a variety of techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), remote plasma enhanced chemical vapor deposition (RPECVD), liquid source misted chemical deposition (LSMCD), coating, spin-coating or another process that is adapted to form a thin film layer.

Referring to, the methodproceeds to stepin which the inhibitor may be removed. The inhibitor may be removed by a dry processing approach. Examples of dry processing approaches include a gas soak. Gases such as H, N, NH, CO, O, air, or mixtures thereof may be used for the gas soak. The gas soak may occur at ambient or elevated temperatures. Other examples of a dry processing approach is plasma treatment in a vacuum environment or in the presence of any of H, N, NH, CO, O, air, or mixtures thereof at ambient or elevated temperatures. Examples of wet processing approach include an acid clean, acid etch, solution clean, or solution etch at ambient or elevated temperatures.

Referring to, the methodproceeds to stepin which an inhibitor may be selectively deposited on the dielectric. The inhibitor may be a self-assembled monolayer or other molecules. The self-assembled monolayer may have one or more of an anchor group, a tail, and a functional end group. The anchor group may include one of silicon, carbon, and nitrogen.

The inhibitor blocking layermay be deposited using a dry techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or vapor ALD. The inhibitor blocking layermay be deposited using a catalyzed growth technique. The inhibitor blocking layermay be deposited using any of LPCVD (low-pressure chemical vapor deposition), APCVD (atmospheric-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), sputtering, and future-developed deposition procedures. The inhibitor blocking layermay be deposited using wet techniques such as spin-on, dipping, or spraying approaches.

In some embodiments the surface of the dielectric regionmay be treated to allow for deposition of the inhibitor blocking layer. In some embodiments, the treatment process can be configured to treat or otherwise modify a top boundary of the dielectric region. The treatment gas may react with atoms of the dielectric region. For example, the treatment process can include a hydrogen Hplasma process, used to supply hydrogen for the bonds between the dielectric regionand hydrogen, by flowing hydrogen gas or precursor into a vacuum (airtight) chamber. In another example, the treatment process can include a nitrogen (N) plasma process, used to supply nitrogen for the bonds between the dielectric regionand nitrogen, by flowing nitrogen gas or precursor into a vacuum (airtight) chamber. In yet another example, the treatment process can include an ammonia (NH) plasma process, used to supply nitrogen and/or hydrogen for the bonds between dielectric regionand nitrogen and/or hydrogen, by flowing nitrogen gas or precursor into a vacuum (airtight) chamber. In yet another example, the treatment process can include an oxygen (O) plasma treatment, used to supply oxide bonds. In yet another example, the treatment process may include a soaking process, used to soak the dielectric region, by flowing corresponding gas or precursor into a vacuum (airtight) chamber, without forming plasma. In some embodiments, the gas soak may be a gas such as H, N, NH, CO, O, air, or mixtures of these. In some embodiments the deposition or treatment may be at room temperature. In some embodiments the deposition or treatment may be a temperature above room temperature.

Treatments for the inhibitor blocking layermay include dry approaches such gas soak of gasses such as H, N, NH, CO, O, air or mixtures. Another example of a dry approach is plasma treatment in environments such as H, N, NH, CO, O, air or mixtures. In some embodiments treatment may include wet approaches such as an acid clean, solution clean, or wet etch. The foregoing dry and wet approaches may be carried out at room temperature. The foregoing dry and wet approaches may be carried out at elevated temperatures.

Referring to, the methodproceeds to stepin which a dielectricmay be deposited on the region where the inhibitor is not present. The dielectricmay be deposited over the conductive region. The dielectricmay be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular layer deposition (MLD), spin-on deposition or other processes. The dielectricmay have a higher etching selectivity allowing for a faster etch rate when compared with dielectric. The dielectricmaterial may be Al, Zr, Y, Hf or Ti in oxide, nitride, or carbide composite films. The thickness of the dielectricmay range from less than 5 angstroms to about 70 nm.

Referring to, the methodproceeds to stepin which the inhibitor may be removed. The inhibitor may be removed by a dry processing approach. Examples of dry processing approaches include a gas soak in a gas such as H, N, NH, CO, O, air, or mixtures thereof at ambient or elevated temperatures. Other examples of a dry processing approach include plasma treatment in a vacuum environment or in the presence of any of H, N, NH, CO, O, air, or mixtures thereof at room or elevated temperatures. Examples of wet processingapproaches include an acid clean, acid etch, solution clean, or solution etch at ambient or elevated temperatures.

Referring to, the methodproceeds to stepwhere an etch stop layermay be deposited. The etch stop layermay be deposited over the top of the surface. The etch stop layermay cover the dielectricand dielectric. The etch stop layerfunctions for controlling the end point during subsequent etching processes. In some embodiments, the etch stop layeris formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or combinations thereof. In some embodiments, the etch stop layerhas a thickness of about 10 angstroms to about 1000 angstroms. The etch stop layeris formed through any of a variety of deposition techniques, including, LPCVD (low-pressure chemical vapor deposition), APCVD (atmospheric-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), sputtering, and future-developed deposition procedures.

Referring to, the methodproceeds to stepwhere a dielectric layermay be deposited. The dielectric layermay be deposited over the etch stop layer. The dielectric layermay be a single layer or a multi-layered structure. In some embodiments, the dielectric layerthickness varies with the applied technology, for example a thickness of about 1000 angstroms to about 30000 angstroms. In some embodiments, the dielectric layeris silicon oxide, carbon-doped silicon oxide, a comparatively low dielectric constant (k value) dielectric material with a k value less than about 4.0, or combinations thereof. In some embodiments, the dielectric layeris formed of a material, including low-k dielectric material, extreme low-k dielectric material, porous low-k dielectric material, and combinations thereof. The term “low-k” is intended to define a dielectric constant of a dielectric material of 3.0 or less. The term “extreme low-k (ELK)” means a dielectric constant of 2.5 or less, and preferably between 1.9 and 2.5. The term “porous low-k” refers to a dielectric constant of a dielectric material of 2.0 or less, and preferably 1.5 or less.

A wide variety of low-k materials may be employed in accordance with embodiments, for example, spin-on inorganic dielectrics, spin-on organic dielectrics, porous dielectric materials, organic polymer, organic silica glass, FSG (SiOF series material), HSQ (hydrogen silsesquioxane) series material, MSQ (methyl silsesquioxane) series material, or porous organic series material. In some embodiments, the dielectric layeris deposited through any of a variety of techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), remote plasma enhanced chemical vapor deposition (RPECVD), liquid source misted chemical deposition (LSMCD), coating, spin-coating or another process that is adapted to form a thin film layer over the substrate.

In embodiments, the dielectric layeris a nitrogen-containing layer, a carbon-containing layer, or a carbon-containing and nitrogen-containing layer. In some embodiments, the dielectric layeris a silicon-containing and nitrogen-containing dielectric layer. In some embodiments, the dielectric layeris a silicon-containing and carbon-containing dielectric layer. In yet another embodiment, the dielectric layeris a silicon-containing, nitrogen-containing, and carbon-containing dielectric layer. In one embodiment, the dielectric layerhas a ratio by weight of carbon to silicon about equal or greater than 0.5. In another embodiment, the dielectric layerhas a ratio by weight of nitrogen to silicon about equal or greater than 0.3. In yet another embodiment, the dielectric layerhas a ratio by weight of carbon to silicon about equal or greater than 0.5 and a ratio by weight of nitrogen to silicon about equal or greater than 0.3.

Referring to, the methodproceeds to stepwhere the trench for conductive region (n+1) and via (n to n+1) may be patterned. The trench and via may be etched for via landing. The trench and via may be etched using a dual damascene process. The trench is patterned in the dielectric layerand the etch stop layerto define a contact region on the semiconductor substrate. Although the embodiments illustrate dual damascene openings, a single damascene process may also be used. In dual damascene techniques including a “via-first” patterning method or a “trench-first” patterning method, the trenchand the viamay be formed using a typical lithographic with masking technologies and anisotropic etch operation (e.g. plasma etching or reactive ion etching). In alternative embodiments, a bottom etch stop layer (not shown), a middle etch stop layer (not shown), a polish stop layer (not shown), or an anti-reflective coating (ARC) layer (not shown) is deposited on or intermediately in the dielectric layer, providing a clear indicator of when to end a particular etching process. Those skilled in the art will recognize that in some embodiments additional layers may also be present as detailed in the art.

Referring to, the methodproceeds to stepwhich may include a wet clean process for post etch. The wet clean process may also remove the dielectric. The via may self-align due to the etching selectivity of dielectric. Dielectricmay have a superior etching selectivity to the etching selectivity of dielectricand dielectric. The etching selectivity may prevent etch punch into dielectric. The selective dielectricmay be converted to be removed by the wet cleaning using a selective etching process. The wet clean may be an acid clean, acid etch, solution clean, or solution etch. The wet clean may use an RCA process. The wet clean may occur at room, low, or elevated temperatures. The wet clean may be isotropic or anisotropic. Example of wet clean chemicals include hydrochloric acid, hydrogen peroxide, hydrofluoric acid, sulfuric acid, standard clean-1 (SC-1), ammonia hydrogen peroxide mixture (APM), hydrochloric acid hydrogen peroxide mixture (HPM), sulfuric acid hydrogen peroxide mixture (SPM) and many others commonly known in the industry. This list is representative and those skilled in the art are aware of the many chemicals currently used and which may in the future be used in the wet etch process.

Referring to, the methodproceeds to stepwhere the trenchand viamay be filled. The trenchand viamay be filled with a conductive material. The trenchand viamay be filled using a metallization for metal gap-filling. In some embodiments, the trenchand viaconductive material may also include a selective barrier. In some embodiments, the conductive material is formed as an interconnect structure in the dielectric layer. In some embodiments, the conductive material is deposited by an electro-chemical plating (ECP) process, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), or other well-known deposition techniques. In some embodiments, the conductive material at least contains a main metal element, e.g., copper (Cu). In some embodiments, the conductive material further contains an additive metal element. In some embodiments, the additive metal element in the conductive material is tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), chromium (Cr), titanium (Ti), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al), or zirconium (Zr). In some embodiments a portion of the conductive material in the conductive regionover the dielectric layeris removed. In some embodiments, the removing process is chemical mechanical polishing (CMP) process performed to remove the excess portions of the conductive material outside the conductive region, thus exposing the dielectric layerand achieving a planarized surface.

In some embodiments, the conductive material may include a first conductive layer formed to line the sidewalls and bottoms of the trenchand via. The first conductive layer may include a metal material such as, for example, tantalum (Ta), titanium (Ti), and tungsten (W). In some embodiments, the first conductive layer includes a compound or an alloy of the above-identified metal materials such as, for example, tantalum nitride (TaN), tantalum nitride silicon (TaNSi), titanium tungsten (TiW), and titanium nitride silicon (TiNSi). In some embodiments, the first conductive layer has a thickness of about 10 angstroms to about 250 angstroms. In some embodiments, the first conductive layer may be deposited by using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), or otherwell-known deposition techniques.

illustrates exemplary cross-sectional representations of all method steps in method. In stepa semiconductor substrateincluding a metal (n)conductive region formed in a dielectricmaterial may be secured. In stepan inhibitormay be selectively deposited on conductive region. In step, a dielectricmay be selectively deposited in the region where the inhibitoris not deposited. In step, an inhibitor may be selectively deposited on the dielectric. In step, a dielectricmay be deposited on the region where the inhibitor is not present. In, the inhibitor may be removed. In step, an etch stop layermay be deposited. In step, a dielectric layermay be deposited. In stepa trench for conductive region (n+1) and via (n ton+1) may be patterned. In step, a wet clean process may occur post etch which may also remove the converted dielectric. Finally, in stepthe trenchand viamay be filled.

illustrates an alternate embodiment of the present invention and presents a second embodiment for the method leading to the production of a self-aligned via. In contrast with the previously presented method, in the alternate embodiment the inhibitor is first deposited on the dielectric regionrather than on the conductive region. The details of the steps correspond to those outlined for the method inand are omitted here except where it deviates from the details outline in.

At step(corresponding tostep), a substrate is provided where the upper surface contains conductive metal separated by a dielectric. At step(corresponding tostep), an inhibitor may be selectively deposited on the dielectric surface. At step(corresponding tostep), a dielectric may be deposited on the surface of the wafer in the regions where the inhibitor is not deposited. Stepmay result in the dielectric deposited on the conductive regions of the surface. At step(corresponding tostep), the inhibitor is removed. At step(corresponding tostep), the inhibitor may be selectively deposited over the conductive region. At step(corresponding tostep), dielectric may be deposited in the region where the inhibitor is not present. At step(corresponding tostep), the inhibitor is removed. At step(corresponding tostep), an etch stop layer may be deposited over the surface of the wafer. At step((corresponding tostep), an interlayer dielectric may be deposited over the etch stop layer. At step(corresponding tostep), upper conductive trenches and connecting vias may be patterned. At step, (corresponding tostep), upper conductive trenches and connecting vias may be etched. At step(corresponding tostep), the trench and vias may be filled with conductive material such as metal.

illustrates cross-sectional representations of the structures formed during steps-of the second embodiment method. At step, a substrate is provided where the upper surface contains conductive metal separated by a dielectric. At step, an inhibitor may be selectively deposited on the dielectric surface. At step, a dielectric may be deposited on the surface of the wafer in the regions where the inhibitor is not deposited. Stepmay result in the dielectric deposited on the conductive regions of the surface. At step, the inhibitor is removed.

illustrates an alternate embodiment of the present invention and presentsa third embodiment for the method leading to the production of a self-aligned via. In contrast with the first embodiment method, stepsandare omitted. Unlike the first embodiment, in the third embodiment the inhibitor is only deposited on the conductive region. No inhibitor is deposited on the dielectric region.

The details of the steps which correspond to embodiment 1 and correspond to those outlined for the method inare omitted here except where they deviate from the details outlined in.

At step(corresponding tostep), a substrate is provided where the upper surface contains conductive metal separated by a dielectric. At step(corresponding tostep), an inhibitor may be selectively deposited on the conductive regions of the surface. At step(corresponding tostep), a dielectric may be deposited on the surface of the wafer in the regions where the inhibitor is not deposited. Stepmay result in the dielectric deposited on the dielectric regions of the surface. At step(corresponding tostep), the inhibitor is removed.

At step, a dielectricmay be deposited on the surface of the wafer. The dielectricmay coat the entire surface of the wafer. At step(corresponding tostep), an etch stop layer may be deposited over the surface of the wafer. At step((corresponding tostep), an interlayer dielectric may be deposited over the etch stop layer. At step(corresponding tostep), upper conductive trenches and connecting vias may be patterned. At step, (corresponding tostep), upper conductive trenches and connecting vias may be etched. At step(corresponding tostep), the trench and vias may be filled with conductive material such as metal.

illustrates cross-sectional representations of the structures formed duringsteps-of the second embodiment method. At step, a substrate is provided where the upper surface contains conductive metal separated by a dielectric. At step, an inhibitor may be selectively deposited on the conductive surface. At step, a dielectric maybe deposited on the surface of the wafer in the regions where the inhibitor is not deposited. Stepmay result in the dielectric deposited on the dielectric regions of the surface. At step, the inhibitor may be removed. At stepa dielectric may be deposited across the surface of the wafer. The dielectricmay be deposited by spin-on wet processes resulting in gap-fill. The dielectricmay be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin-on which may result in a conformal coating of the dielectricacross the surface of the wafer.

illustrate one advantage of the present self-aligned via structure in the case of overlay (OVL) shift, for instance, in lithographic patterning. This shift may be due, for instance, to misalignment of the lithographic mask. In the case of OVL shift, the dielectricand dielectricincreases the critical dimension between the viaand an adjacent first level conductive region. This is due to the difference in the material in the regions formed by the disclosed method. The increase in the critical dimension decreases the viato first level conductive regionbreakdown and leakage current.

illustrate one advantage of the present self-aligned via structure in the case of punch through in the case of overlay (OVL) shift for instance in lithographic patterning. In the case of OVL shift with punch through, the dielectricand dielectricincreases the criticaldimension between the viaand an adjacent first level conductive region. The increase in the critical dimension decreases the viato first level conductive regionbreakdown and leakage current.

illustrate one advantage of the present self-aligned via structure in thecase of via critical dimension (CD) enlargement, for instance in lithographic patterning. In the case of via CD enlargement, the dielectricand dielectricincreases the critical dimension between the via and an adjacent first level conductive region. The increase in the critical dimension decreases the via to first level conductive region breakdown and leakage current.