Ic Structure with High Thermal Conductivity Layer on Semiconductor Devices

This Application is a Continuation of U.S. application Ser. No. 18/591,282, filed on Feb. 29, 2024, which claims the benefit of U.S. Provisional Application No. 63/589,715, filed on Oct. 12, 2023. The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety.

Modern day integrated circuits (ICs) contain millions of semiconductor devices. The semiconductor devices are electrically interconnected by way of conductive interconnects that are formed above and/or below the semiconductor devices on an IC. The conductive interconnects are disposed within a dielectric structure and are configured to selectively provide power to the semiconductor devices.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotateddegrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

An integrated circuit (IC) structure may include a plurality of semiconductor devices (e.g., transistors) on a frontside of a device layer (e.g., a silicon substrate). A first interconnect structure is disposed on the frontside of the device layer. The first interconnect structure is bonded to a carrier substrate and a second interconnect structure is disposed on a backside of the device layer. The first and second interconnect structures facilitate electrically coupling the semiconductor devices together and/or to other devices. The second interconnect structure comprises a dielectric structure on the device layer and a plurality of conductive interconnects in the dielectric structure. During operation, the semiconductor devices and/or the plurality of conductive interconnects may generate heat (e.g., due to Joule heating). Dissipation of the heat generated during operation of the IC structure has become increasingly important as devices are scaled down and/or more densely packed together. The dielectric structure generally comprises a low dielectric constant material (e.g., silicon dioxide or the like) that increases electrical isolation between the conductive interconnects. However, the low dielectric constant material of the dielectric structure has low thermal conductivity (i.e., has a low ability to dissipate heat).

During formation of the IC structure the semiconductor devices are formed on the device layer and the first interconnect structure is formed on the semiconductor devices. A thinning process is performed on the device layer after bonding the first interconnect structure to the carrier substrate. This removes all of or a substantial portion of the device layer from over the semiconductor devices, where the device layer has a relatively high thermal conductivity (e.g., greater than 10 Watt per meter-Kelvin (W/m-K)). Subsequently, the second interconnect structure is formed on the backside of the device layer. A challenge with the IC structure is high localized heat accumulation across the IC structure. For example, the dielectric structure of the second interconnect structure contacts portions of the semiconductor devices and/or may be disposed relatively close to the semiconductor devices. The low dielectric constant material of the dielectric structure has a relatively low thermal conductivity (e.g., about 0.9 watts per meter-kelvin (W/m-K) or the like). The low thermal conductivity can cause high localized heat accumulation at or around the semiconductor devices. The high localized heat accumulation across the IC structure can cause breakdown of the semiconductor devices and/or delamination of layers in the IC structure. Accordingly, the IC structure has low thermal dissipation performance (e.g., has low dissipation of heat generated by the semiconductor devices) that can reduce a reliability and overall performance of the IC structure.

Various embodiments of the present application are directed towards an IC structure comprising a high thermal conductivity layer disposed on a plurality of semiconductor devices and configured to increase dispersion of heat away from the semiconductor devices. In some embodiments, the IC structure comprises a plurality of semiconductor devices disposed on a device layer and a first interconnect structure on a frontside of the device layer. The first interconnect structure is bonded to a carrier substrate and a second interconnect structure is disposed on a backside of the device layer. The second interconnect structure comprises a dielectric structure and a plurality of conductive interconnects disposed in the dielectric structure. The dielectric structure comprises one or more high thermal conductivity layers disposed on the plurality of semiconductor devices. The one or more high thermal conductivity layers each have a relatively high thermal conductivity (e.g., greater than about 10 W/m-K) and are configured to dissipate heat away from the semiconductor devices and/or the plurality of conductive interconnect structures. As a result, heat may be efficiently transferred away from regions of the IC structure that are prone to high localized heat accumulation (e.g., heat may be efficiently transferred away from the semiconductor devices). Thus, the one or more high thermal conductivity layers increases a thermal dissipation performance of the IC structure and decreases or eliminates high localized heat accumulation across the IC structure. This increases a reliability and overall performance of the IC structure.

illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) structurecomprising an interconnect structure having one or more high thermal conductivity layers disposed on a plurality of semiconductor devices.

The IC structureincludes a first interconnect structuredisposed on a frontsideof a device layer. An insulating layeris disposed on the first interconnect structureand a carrier substrateoverlies the insulating layer. A plurality of semiconductor devicesare disposed within and/or on the device layer. The first interconnect structurecomprises a first dielectric structureand a plurality of first conductive interconnects,,disposed in the first dielectric structure. The plurality of first conductive interconnects,,includes a plurality of first conductive contacts, a plurality of first conductive wires, and a plurality of first conductive vias. The plurality of first conductive interconnects,,are electrically coupled to the semiconductor devices.

In some embodiments, the semiconductor devicesare configured as a transistor and comprise a gate dielectricdisposed over the device layer, a gate electrodeover the gate dielectric, one or more semiconductor channels, and a pair of source/drain structuresdisposed on opposing sides of the one or more semiconductor channels. Source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context. In various embodiments, the one or more semiconductor channelsare part of the device layerand/or comprise a same material (e.g., silicon) as the device layer. In some embodiments, the pair of source/drain structuresmay be doped regions of the device layeror may be or comprise doped epitaxial silicon. The gate electrodeoverlies the one or more semiconductor channels. In some embodiments, the gate electrodeoverlies a top surface of the one or more semiconductor channelsand extends along sidewalls of the one or more semiconductor channels. In various embodiments, during use of the semiconductor devices, the gate electrodeof each semiconductor devicemay be selectively biased to vary a conductivity of the one or more semiconductor channelsbetween the pair of source/drain structures. The semiconductor devicesmay, for example, be planar metal-oxide-semiconductor (MOS) field-effect transistors (FETs), gate-all-around (GAA) FETs, fin FETs (FinFETs), nanowire FETs, nanoring FETs, nanosheet (NS) FETs (NSFETs), some other type of semiconductor device and/or transistor, or any combination of the foregoing.

The IC structurefurther includes a second interconnect structuredisposed on a backsideof the device layer. The second interconnect structureincludes a second dielectric structureand a plurality of second conductive interconnects,,disposed in the second dielectric structure. The plurality of second conductive interconnects,,includes a plurality of second conductive contacts, a plurality of second conductive wires, and a plurality of second conductive vias. The plurality of second conductive interconnects,,are electrically coupled to the semiconductor devicesand/or the first interconnect structure. In various embodiments, one or more of the second conductive contactsdirectly contact one or more structures of the semiconductor devices. For example, an individual second conductive contactdirectly contacts a source/drain regionof an individual semiconductor devicein the plurality of semiconductor devices.

The second dielectric structurecomprises a plurality of high thermal conductivity layersstacked with a plurality of dielectric layers. The plurality of high thermal conductivity layerscomprises a first high thermal conductivity layerdisposed along the backsideof the device layer. The plurality of dielectric layerscomprise a low dielectric constant material with a relatively low thermal conductivity (e.g., less than about 1 W/m-K). The high thermal conductivity layerscomprise a dielectric material having a relatively high thermal conductivity (e.g., greater than about 10 W/m-K) and are configured to efficiently transfer heat away from the plurality of semiconductor devicesand/or the plurality of second conductive interconnects,,. In various embodiments, the thermal conductivity of the high thermal conductivity layersis greater than thermal conductivities of the first dielectric structure, the device layer, the insulating layer, and/or the plurality of dielectric layers.

During operation of the IC structure, current running through conductive structures of the first and/or second interconnect structures,and/or through the semiconductor devicescauses a generation of heat. In various embodiments, this can result in heat accumulating at or around the semiconductor devices. By virtue of the second dielectric structurecomprising the high thermal conductivity layers, heat may be efficiently dissipated away from regions of the IC structurethat are prone to high localized heat accumulation (e.g., heat is efficiently transferred away from the semiconductor devices). The effective dissipation of heat increases a thermal dissipation performance of the IC structureand decreases or eliminates high localized heat accumulation across the IC structure. As a result, a performance of the semiconductor devicesis increased and damage to the semiconductor devicesand/or the conductive structures of the first and/or second interconnect structures,is decreased. Thus, a reliability and overall performance of the IC structureare increased.

illustrate various cross-sectional views of some embodiments of an IC structurecomprising an interconnect structure having one or more high thermal conductivity layers.illustrates a cross-sectional view of some embodiments of the IC structuretaken along a first plane (e.g., the z-x plane).illustrates a cross-sectional view of some embodiments of the IC structuretaken along a second plane (e.g., the z-y plane) perpendicular to the first plane.

As illustrated in, the IC structureincludes a first interconnect structureon a frontside FS of a plurality of semiconductor devicesand a second interconnect structureon a backside BS of the plurality of semiconductor devices. The frontside FS of the semiconductor devicescorresponds to an upper surface of the semiconductor devicesand faces the first interconnect structure. The backside BS of the semiconductor devicescorresponds to a lower surface of the semiconductor devicesand faces the second interconnect structure. The frontside FS is opposite the backside BS. In various embodiments, the semiconductor devicesare disposed within and/or on a device layer, where the frontside FS corresponds to a first surface of the device layerand the backside BS corresponds to a second surface of the device layeropposite the second surface.

An insulating layeris disposed on the first interconnect structureand a carrier substrateoverlies the insulating layer. The insulating layermay, for example, be or comprise an oxide such as silicon dioxide or some other suitable material. The carrier substrateis a semiconductor substrate or some other suitable substrate. In some embodiments, the carrier substrateis or comprises silicon, germanium, some other suitable material, or any combination of the foregoing. In various embodiments, the insulating layeris configured to facilitate bonding between the carrier substrateand the first interconnect structure.

The semiconductor devicesare gate-all-around (GAA) field-effect transistors (FETs). In other embodiments, the semiconductor devicesmay alternatively be planar metal-oxide-semiconductor (MOS) FETs (MOSFETs), fin FETs (FinFETs), nanowire FETs, nanoring FETs, nanosheet (NS) FETs (NSFETs), some other type of semiconductor device and/or transistor, or any combination of the foregoing. The semiconductor devicesrespectively comprise a plurality of semiconductor channels, a gate dielectric structure, a gate electrode, a spacer layer, and corresponding source/drain regions. The semiconductor channelsfor each of the semiconductor devicesare vertically stacked with one another. The gate electrodeoverlies the semiconductor channelsand is spaced vertically between adjacent semiconductor channels. The gate dielectric structureis spaced between the gate electrodeand the semiconductor channels. In various embodiments, the gate dielectric structureand the gate electrodeboth continuously extend around bottom and top surfaces of at least two or more of the semiconductor channels. A gate structure of the semiconductor devicesincludes the gate electrodeand the gate dielectric structure.

In various embodiments, the semiconductor channelsare part of and/or are formed from the device layerand comprise a semiconductor material (e.g., silicon) of the device layer. In some embodiments, the semiconductor channelsare nanostructures, nanosheets, some other suitable structure, or the like. The semiconductor channelscontinuously extend between two of the source/drain regions. In various embodiments, the source/drain regionsdirectly contact corresponding semiconductor channels. The spacer layeris disposed between the source/drain regionsand the gate dielectric structure. In various embodiments, two of the semiconductor devicesin the plurality of semiconductor devicesshare one of the source/drain regions. In alternative embodiments, the semiconductor devicesdo not share a source/drain regionand instead each have a discrete pair of source/drain regions and are laterally separated from one another by a non-zero distance (not shown). By applying suitable bias conditions to the gate electrodeand the source/drain regions, a conductivity of the semiconductor channelsby be controlled (e.g., may be switched between one or more conducting states and a non-conducting state).

In some embodiments, the gate electrodemay, for example, be or comprise polysilicon, titanium, aluminum, tungsten, titanium, tantalum, gallium, carbon, some other suitable material, or any combination of the foregoing. In various embodiments, the gate dielectric structuremay, for example, be or comprise silicon dioxide, aluminum oxide, hafnium oxide, silicon oxynitride, a high-k dielectric material, some other suitable dielectric, or any combination of the foregoing. In further embodiments, the source/drain regionsmay, for example, be or comprise silicon, germanium, silicon germanium, an epitaxial semiconductor material (e.g., epitaxial silicon, epitaxial germanium, epitaxial silicon germanium, etc.), some other suitable material, or any combination of the foregoing. Further, the source/drain regionsare doped. In some embodiments, the source/drain regionscomprise silicon or epitaxial silicon doped with phosphorus, where a doping concentration of phosphorus in the source/drain regionsis about 1*10atoms/cmor greater. In yet further embodiments, the source/drain regionscomprise epitaxial silicon germanium doped with boron, where a doping concentration of boron in the source/drain regionsis about 5*10atoms/cmor greater. In yet further embodiments, the spacer layermay, for example, be or comprise silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, some other dielectric material, or any combination of the foregoing. In various embodiments, the spacer layercomprises silicon oxycarbonitride, where an atomic percentage of carbon in the spacer layeris about 6 percent or less.

The first interconnect structureis electrically coupled to the plurality of semiconductor deviceson the frontside FS of the semiconductor devices. The first interconnect structurecomprises a first dielectric structureand a plurality of first conductive interconnects,,that includes a plurality of first conductive contacts, a plurality of first conductive wires, and a plurality of first conductive vias. A topmost layer of the plurality of first conductive wiresis separated from the insulating layerby at least a portion of the first dielectric structure. In further embodiments, the topmost layer of the plurality of first conductive wiresdirectly contacts at least a portion of a bottom surface of the insulating layer. In various embodiments, the first dielectric structurecomprises a plurality of inter-level dielectric (ILD) layersand one or more etch stop layersdisposed between corresponding ILD layers. The plurality of ILD layersmay, for example, be or comprise an oxide (e.g., silicon dioxide), borosilicate glass, silicon oxycarbide, silicon oxycarbonitride, a low-k dielectric material, or the like. The one or more etch stop layersmay, for example, be or comprise silicon nitride, silicon carbon nitride, some other dielectric material, or the like. In some embodiments, a thermal conductivity of the one or more ILD layersis relatively low (e.g., less than about 1 W/m-K).

The second interconnect structureis electrically coupled to the plurality of semiconductor deviceson the backside BS of the semiconductor devices. The second interconnect structureincludes a second dielectric structureand a plurality of second conductive interconnects,,disposed in the second dielectric structure. The plurality of second conductive interconnects,,includes a plurality of second conductive contacts, a plurality of second conductive wires, and a plurality of second conductive vias. In various embodiments, the second conductive contactsdirectly contact a source/drain regionof a corresponding semiconductor device. The plurality of second conductive interconnects,,may, for example, be or comprise titanium nitride, aluminum, tungsten, copper, ruthenium, molybdenum, titanium aluminum, tantalum nitride, some other conductive material, or any combination of the foregoing.

The second dielectric structurecomprises a plurality of high thermal conductivity layers-and a plurality of dielectric layers-. The plurality of dielectric layers-includes a first dielectric layerand a second dielectric layerThe plurality of high thermal conductivity layers-are configured to increase a transfer of heat within the second dielectric structurealong a horizontal direction. The plurality of high thermal conductivity layers-include a first high thermal conductivity layerdisposed along the backside BS of the plurality of semiconductor devicesand a second high thermal conductivity layerdisposed on the first high thermal conductivity layerIn some embodiments, the plurality of second conductive contactsrespectively comprise a vertical segmentand a body segment. In various embodiments, the vertical segmentmay be configured as a contact or via and the body segmentmay be configured as a wire. In some embodiments, the vertical segmentis disposed in the first and second high thermal conductivity layers-and the body segmentis disposed in the first dielectric layerIn further embodiments, a third high thermal conductivity layerof the plurality of high thermal conductivity layers-continuously extends along bottom surfaces of the second conductive contacts. The first and second high thermal conductivity layers-directly contact opposing sidewalls of the vertical segmentand/or directly contact a top surface of the body segment. Further, the third high thermal conductivity layerdirectly contacts opposing sidewalls of the second conductive vias. In various embodiments, the second conductive contactsmay be configured as a conductive plug. In further embodiments, the second conductive contactsare configured as or directly electrically coupled to a power rail, where the second conductive contactsmay deliver high power to the semiconductor devices.

In some embodiments, the plurality of high thermal conductivity layers-comprise a material having a thermal conductivity greater than about 10 W/m-K, within a range of about 10 to 2,500 W/m-K, or some other suitable value. In some embodiments, the plurality of high thermal conductivity layers-may, for example, be or comprise aluminum nitride (AlN), boron nitride (BN), yttrium oxide (YO), yttrium aluminum garnet (YAlO), aluminum oxide (AlO), beryllium oxide (BeO), silicon carbide (SiC), graphene, diamond like carbon (DLC), diamond (e.g., near isotropic diamond grains), another suitable material, or any combination of the foregoing. In some embodiments, the plurality of high thermal conductivity layers-may be poly-crystalline, single crystalline, amorphous, or the like. For example, the high thermal conductivity layers-may be or comprise poly-crystal silicon carbide, single-crystal silicon carbide, or amorphous silicon carbide. In yet further embodiments, the high thermal conductivity layers-have a cubic crystal structure, a hexagonal crystal structure, a tetragonal crystal structure, an orthorhombic crystal structure, a monoclinic crystal structure, a triclinic crystal structure, or the like. In various embodiments, the high thermal conductivity layers-have a cubic crystal structure that may be different from a crystal structure of the dielectric layers-, the ILD layers, and/or the one or more etch stop layers. For example, the dielectric layers-and/or the ILD layersmay comprise silicon dioxide having a hexagonal crystal structure and the one or more etch stop layersmay comprise silicon nitride having a hexagonal crystal structure, where the high thermal conductivity layers-have a cubic crystal structure. The high thermal conductivity layers-having the cubic crystal structure increases an ability for the high thermal conductivity layers-to dissipate heat. In further embodiments, the high thermal conductivity layers-have a higher thermal conductivity than that of the plurality of semiconductor channels, the source/drain regions, and/or the gate dielectric structure.

In yet further embodiments, the high thermal conductivity layers-are further configured to operate as an etch stop layer for the second interconnect structure, where the high thermal conductivity layers-comprise a material that is more resistant to etching than the plurality of dielectric layers-. For example, the high thermal conductivity layers-are etched at a first rate that is less than a second rate that the plurality of dielectric layers-are etched when exposed to an etchant (e.g., such as a dry etchant comprising fluorine). In some embodiments, a top surface of the first high thermal conductivity layeris aligned with a top surface of the plurality of second conductive contacts. In various embodiments, a thickness of the first high thermal conductivity layeris less than a thickness of the second high thermal conductivity layerFurther, the thickness of the second high thermal conductivity layeris greater than a thickness of the first dielectric layerIn some embodiments, thicknesses of the high thermal conductivity layers-are each greater than a thickness of the one or more etch stop layers. The high thermal conductivity layers-comprise a material different from that of the one or more etch stop layers. In various embodiments, the high thermal conductivity layers-may be or comprise different materials from one another. In yet further embodiments, the high thermal conductivity layers-may each be or comprise a same material.

By virtue of the high thermal conductivity layers-being disposed in the second interconnect structureand along the backside BS of the semiconductor devices, heat may be efficiently dissipated away from the semiconductor devicesand/or conductive interconnects of the second interconnect structure. As a result, a performance and reliability of the IC structureis increased.

It will be appreciated that the high thermal conductivity layers-may be disposed at different locations within the IC structure, and the IC structuremay have a different number of high thermal conductivity layers disposed in the second interconnect structure.illustrate various cross-sectional views of the high thermal conductivity layers being disposed at different locations within the second interconnect structureand/or the second interconnect structurehaving different numbers of high thermal conductivity layers.

As illustrated in, the plurality of semiconductor devicesare disposed in an array comprising at least two rows and at least two columns. For instance, the cross-sectional view ofis taken along a first column of the plurality of semiconductor devicesand the cross-sectional view ofis taken along the source/drain regionsof a first row of the plurality of semiconductor devices. In some embodiments, the first dielectric structureextends along a top surface of the source/drain regionsto the second dielectric structure. In various embodiments, a bottom surface of the first dielectric structuredirectly contacts a top surface of the second dielectric structure.

illustrates an isometric view of some embodiments of an individual semiconductor deviceof the IC structureof.

As illustrated in, the semiconductor devicecomprises a gate structuredisposed over and around the plurality of semiconductor channels. In various embodiments, the gate structurecomprises the gate electrode (of) and the gate dielectric structure (of). The plurality of semiconductor channelscontinuously laterally extend between the source/drain regions. In various embodiments, a vertical segment of an individual second conductive contactis disposed in the first and second high thermal conductivity layers-. In some embodiments, the first high thermal conductivity layercontinuously extends long bottom surfaces of the source/drain regions.

illustrate various cross-sectional views of some other embodiments of the IC structureof. Figures with a suffix of “A” illustrate a cross-sectional view taken along the z-x plane and figures with a suffix of “B” illustrate a cross-sectional view taken along the z-y plane.

illustrate various cross-sectional views of some embodiments of an IC structure, in which the second conductive contactsextend above a bottom surface of the source/drain regionsby a non-zero distance d. In various embodiments, a liner layeris disposed along opposing sidewalls of each of the second conductive contacts. The liner layermay, for example, be or comprise silicon nitride, silicon carbide, some other suitable material, or any combination of the foregoing. In yet further embodiments, the liner layeris omitted (not shown) and the source/drain regionsdirectly contact opposing sidewalls of a corresponding second conductive contact.

illustrate various cross-sectional views of some embodiments of an IC structure, in which a width of each second conductive contactis greater than a width of a corresponding source/drain region. In various embodiments, each second conductive contactcontinuously extends along an entire bottom surface of a corresponding source/drain region.

illustrate various cross-sectional views of some embodiments of an IC structure, in which the plurality of second conductive contactsare disposed in the first high thermal conductivity layerand the second high thermal conductivity layer. Further, the second high thermal conductivity layercontinuously extends along a top surface of the third high thermal conductivity layerAs a result, an ability for the IC structureto dissipate heat away from the second conductive contactsand/or the semiconductor devicesis increased, thereby increasing an overall performance of the IC structure.

illustrate various cross-sectional views of some embodiments of an IC structurecorresponding to some other embodiments of the IC structureof, in which the source/drain regionsextend below a top surface of the first high thermal conductivity layer

Further, in some embodiments as shown ina lower etch stop layeris disposed along a bottom surface of the first dielectric structureand an isolation structureis disposed along a lower portion of the source/drain regionsand an upper portion of the second conductive contacts. The lower etch stop layermay, for example, be or comprise silicon nitride, silicon oxynitride, some other suitable dielectric, or any combination of the foregoing. In various embodiments, the lower etch stop layerhas a thermal conductivity less than that of the high thermal conductivity layers-. In various embodiments, the first dielectric layerextends from a bottom surface of the first high thermal conductivity layerto opposing sidewalls of the first high thermal conductivity layerIn some embodiments, the isolation structuremay be configured as a shallow trench isolation (STI) structure. The isolation structuremay, for example, be or comprise silicon dioxide, silicon nitride, some other dielectric material, or any combination of the foregoing. In yet further embodiments, the isolation structurehas a thermal conductivity less than that of the high thermal conductivity layers-

illustrate various cross-sectional views of some embodiments of an IC structurecorresponding to some other embodiments of the IC structureof, in which the first high thermal conductivity layercontinuously extends from the source/drain regionsto a point aligned with a bottom surface of the second conductive contacts. As shown in, in some embodiments, the isolation structureextends from sidewalls of the source/drain regionsto sidewalls of the second conductive contacts.

illustrate various cross-sectional views of some embodiments of an IC structurecorresponding to some other embodiments of the IC structureof, in which conductive interconnects of the first and second interconnect structures,respectively comprise a conductive core structuresurrounded by a conductive liner layer. In some embodiments, the conductive core structuremay, for example, be or comprise tungsten, aluminum, copper, ruthenium, tantalum, titanium, some other conductive material, or any combination of the foregoing. In various embodiments, the conductive liner layermay, for example, be or comprise titanium nitride, tantalum nitride, some other suitable material, or any combination of the foregoing. In some embodiments, the conductive liner layeris configured as a barrier layer and is disposed between the conductive core structureand corresponding dielectric layer(s) of the first or second dielectric structures,.

In various embodiments, an upper surface of the conductive liner layerof each of the second conductive contactsis disposed along a bottom surface of the first high thermal conductivity layerIn yet further embodiments, the top surface of the conductive liner layerof each of the second conductive contactsis disposed along a corresponding source/drain regionand is aligned with a top surface of the first high thermal conductivity layer

It will be appreciated that while the IC structureillustrates another embodiment of the IC structureof, any one of the IC structures of, andA-B throughA-B may comprise the conductive liner layerand the conductive core structureas illustrated and/or described in. Further, it will be appreciated that while a single via level and a single wire level are shown in the second interconnect structureof, more via levels and/or wire levels are amenable.

illustrates a cross-sectional view of some other embodiments of an IC structurecomprising an interconnect structure having one or more high thermal conductivity layers.

The IC structurecomprises the first interconnect structuredisposed on an upper surface the plurality of semiconductor devicesand the second interconnect structuredisposed on a lower surface of the plurality of semiconductor devices. A bottommost layerof the plurality of second conductive wiresof the second interconnect structuremay, for example, be configured as redistribution wires, bond pads, or the like. A plurality of solder bumpsare disposed on the bottommost layerof the plurality of second conductive wiresand are configured to couple and/or bond the IC structureto another semiconductor structure (e.g., to a package substrate, a semiconductor die, or the like).

illustrate various cross-sectional views of some embodiments of a method for forming an IC structure comprising an interconnect structure having one or more high thermal conductivity layers. Althoughare described in relation to a method, it will be appreciated that the structures disclosed in the method are not limited to the method, but instead may stand alone as structures independent of the method. Further, althoughare described as a series of acts, it will be appreciated that these acts are not limited in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part. In addition, figures with a suffix of “A” illustrate a cross-sectional view taken along the z-x plane and figures with a suffix of “B” illustrate a cross-sectional view taken along the z-y plane.

As shown in cross-sectional viewof, a base substrateis provided and a stack of layersis formed over the base substrate. The base substratemay, for example, be or comprise silicon, germanium, silicon germanium, some other semiconductor body, or the like. In some embodiments, the stack of layersincludes an etch stop layeron the base substrate, a lower semiconductor layeron the etch stop layer, a first high thermal conductivity layera plurality of first semiconductor layers, and a plurality of second semiconductor layers. The plurality of first semiconductor layersand the plurality of second semiconductors layersare alternatingly stacked with one another. In various embodiments, the plurality of second semiconductor layersare part of or define a device layer.

In some embodiments, a process for forming the etch stop layerincludes depositing or growing the etch stop layerover the base substrateby, for example, a chemical vapor deposition (CVD) process, an epitaxial process, or some other suitable deposition or growth process. The lower semiconductor layermay be formed over the etch stop layerby, for example, a CVD process, an epitaxial process, or some other suitable deposition or growth process. The first high thermal conductivity layermay be formed over the lower semiconductor layerby, for example, a CVD process, a thermal CVD process, a hybrid physical-CVD (HPCVD) process, a plasma-enhanced CVD (PECVD) process, a microwave-plasma CVD (MWCVD) process, a physical vapor deposition (PVD) process, a thermal atomic layer deposition (ALD) process, a plasma-enhanced ALD (PEALD) process, or some other suitable deposition or growth process. Further, the first semiconductor layersand the second semiconductor layersare each formed over the first high thermal conductivity layerby an epitaxial process or some other suitable deposition or growth process. In various embodiments, the individual epitaxial process to form any one of the etch stop layer, the lower semiconductor layer, the first semiconductor layers, and the second semiconductor layersmay, for example, be or comprise molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), some other suitable epitaxial process, or any combination of the foregoing.

In various embodiments, the first high thermal conductivity layeris deposited at a low processing temperature that is, for example, less than about 400 degrees Celsius, within a range of about 100 to 400 degrees Celsius, or some other suitable temperature. The first high thermal conductivity layermay, for example, be or comprise aluminum nitride, boron nitride, yttrium oxide, yttrium aluminum garnet, aluminum oxide, beryllium oxide, silicon carbide, graphene, diamond like carbon, diamond, another suitable material, or any combination of the foregoing. The etch stop layerand/or the first semiconductor layersmay, for example, be or comprise silicon germanium (e.g., having an atomic percentage of germanium within a range of about 10% to 35%), silicon, doped silicon (e.g., silicon doped with boron), or the like. The second semiconductor layersand/or the lower semiconductor layermay, for example, be or comprise silicon, epitaxial silicon, or some other suitable semiconductor material.

As shown in cross-sectional viewof, a masking layeris formed over the plurality of second semiconductor layers (of). Further, a patterning process is performed on the plurality of first semiconductor layersand the plurality of second semiconductor layers (of) according to the masking layer, thereby forming a plurality of semiconductor channelsvertically stacked with the first semiconductor layers. In some embodiments, the patterning process includes performing a dry etch process, a wet etch process, another suitable etch process, or any combination of the foregoing. Further, the masking layermay be removed during or after the patterning process (not shown).

As shown in cross-sectional viewof, a plurality of semiconductor devicesare formed over the base substrate. In various embodiments, the semiconductor devicesare GAA FETs. The semiconductor devicesrespectively comprise the plurality of semiconductor channels, a gate dielectric structure, a gate electrode, a spacer layer, and source/drain regions. The semiconductor channelsfor each of the semiconductor devicesare vertically stacked with one another. The gate electrodeoverlies the semiconductor channelsand is spaced vertically between adjacent semiconductor channels. The gate dielectric structureis spaced between the gate electrodeand the semiconductor channels. The gate electrodeand the gate dielectric structureof each semiconductor devicedefines a gate structure of the corresponding semiconductor device.

In some embodiments, a process for forming the semiconductor devicesincludes forming (e.g., by CVD, PVD, etc.) a dummy gate structure (not shown) over the first semiconductor layers (of); forming (e.g., by CVD, PVD, ALD, etc.) the spacer layeralong the first semiconductor layers (of) and the dummy gate structure; forming (e.g., by an epitaxial process) the source/drain regionsadjacent to the semiconductor channels; selectively removing the dummy gate structure and the first semiconductor layers (of); forming (e.g., by CVD, PVD, etc.) the gate dielectric structureon the semiconductor channels; and forming (e.g., by CVD, PVD, electroplating, electroless plating, etc.) the gate electrodeon the gate dielectric structure.

As shown in cross-sectional viewof, a first interconnect structureis formed over a frontside FS of the semiconductor devices. The first interconnect structurecomprises a plurality of first conductive contacts, a plurality of first conductive wires, and a plurality of first conductive viasdisposed within a first dielectric structure. In some embodiments, conductive structures of the first interconnect structuremay each be formed by a damascene process (e.g., a single damascene process or a dual damascene process) or some other suitable process. In further embodiments, the first dielectric structurecomprises one or more inter-level dielectric (ILD) layers and one or more etch stop layers (e.g., as illustrated and/or described in) that may, for example, each be formed by CVD, PVD, ALD, or some other suitable growth or deposition process.

As shown in cross-sectional viewof, a carrier substrateis provided and subsequently bonded to the first interconnect structure. The carrier substratemay, for example, be or comprise silicon, germanium, or some other suitable semiconductor substrate material. In various embodiments, bonding the carrier substrateto the first interconnect structureincludes: forming (e.g., by CVD, PVD, ALD, etc.) an insulating layeron the carrier substrateand bonding (e.g., by fusion bonding, vacuum bonding, direct bonding, etc.) the insulating layerto the first interconnect structure. The insulating layermay, for example, be or comprise an oxide such as silicon dioxide or some other suitable material.