Gate Driver Fault Reporting

This application claims priority to Germany Patent Application No. 102024203281.6 filed on Apr. 10, 2024, the content of which is incorporated by reference herein in its entirety.

This implementation relates to gate drivers, and in particular to systems and methods for identifying the gate driver that has reported a fault.

Gate drivers are power amplifiers that accept a low-power input from a controller and produce a high-current drive input for a gate of a high-power transistor (e.g., an IGBT or power MOSFET). A motor drive system, for example, may comprise six gate drivers, each providing input to a respective gate of a high-power transistor. Often, gate drivers comprise a pin (e.g., a fault output node) for reporting a fault detected by the gate driver. This pin can report internal faults of the gate driver, and/or faults of the transistor that the gate driver controls.

Nevertheless, in order to reduce a number of I/O pins of a controller, the fault output node of each of the gate drivers are typically connected to a single I/O pin. Thus, once a fault is detected by any of the gate drivers, the single I/O pin will indicate the presence of the fault, but the identity of the gate driver reporting the fault is lost. In other words, with this connection method, it is difficult to distinguish which gate driver has reported the fault, especially when the fault is triggered by random noise.

The inventors have thus identified a need for identifying the gate driver that has reported the fault whilst minimizing the required number of I/O pins.

According to one aspect of the implementation, there is provided a gate drive system. The gate drive system includes a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicating a detected fault by the respective gate driver and an operating state. The system further includes a common node that is switchable between a first state and a second state; a timing arrangement for each of the gate drivers, each timing arrangement connected to the fault output node of the respective gate driver and the common node, each timing arrangement configured to set the common node to the first state responsive to the fault output node of the respective gate driver being set to the fault state; and release the common node from the first state responsive to a predetermined time period having elapsed from a trigger event, wherein the predetermined time period of each timing arrangement is different.

Concepts are provided for identifying the gate driver of a gate driver system that has reported a fault (e.g., to identify which gate driver among a plurality of gate drivers reported or is associated with the fault). The gate driver system includes a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicating a detected fault by the respective gate driver and an operating state. Timing arrangements are provided for each of the gate drivers, with each timing arrangement configured to switch a common node to a first state responsive to the fault output node of the respective gate driver being set to the fault state. Then, after a predetermined time period having elapsed from a trigger event, the common node is released from the first state. As the predetermined time period for each of the timing arrangements (and thus each of the gate drivers) is different, the amount of time between the trigger event and the common node being released from the first state may be measured to identify the gate driver that reported a fault (e.g., the gate driver that switched the common node to the first state). Thus, the proposed concept enables the identification of the gate driver that reported the fault whilst using only a single output pin (e.g., connected to the common node).

In typical gate drivers, all of the fault output nodes (each corresponding to one gate driver) are connected to each other at one common node. This is to minimize the number of I/O pins required to report a fault. As a result, when a fault is detected by one gate driver (or a selection of gate drivers), the common node indicates that there is a fault detected by one (or more) of the gate drivers, but does not indicate which gate driver has reported the fault. Identifying the gate driver which has reported the fault may be useful for locating, and subsequently correcting, the cause of the fault.

Of course, alternatively each of the fault output nodes may be connected to a different I/O pin. Once a fault is detected by one of the gate drivers, then the corresponding I/O pin will indicate that there is a fault, and the location determined in a straightforward manner. However, this method requires a large number of I/O pins.

The disclosed implementation provides a solution to this issue without increasing the number of I/O pins to report the fault. Specifically, the disclosed implementation enables the identification of the gate driver that has reported the fault. This is achieved via a timing arrangement associated with each of the gate drivers, which initially sets the common node to the first state, and only releasing the common node from the first state after a predetermined period of time. Accordingly, an entity observing only the common node will initially be aware of the presence of a fault as the common node is set to the first state, and will be able to identify the gate driver that has reported the fault by monitoring the length of time between a trigger event and the common node being released from the first state.

That is, as the trigger event and the predetermined length of time associated with each gate driver (and provided by the timing arrangement) is known, then the common node can be monitored to identify the gate driver associated with the reported fault. Accordingly, the common node may be connected to a single I/O pin for reporting both the detection and location of the fault.

In some implementations, the first state may be a low state, and the second state may be a high state. That is, each timing arrangement may individually set the common node to a low state responsive to the fault output node of the respective gate driver being set to the fault state. Then, after a predetermined time period associated with the respective timing arrangement, the common node may be released from the low state (e.g., pulled/switched to the high state).

Accordingly, a falling edge of the common node may indicate that a fault output node of at least one of the gate drivers has been set to the fault state. Then, after a predetermined time period from a trigger event, a rising edge of the common node may indicate the gate driver having the fault output node that had been set to the fault state. In other words, the length of time between the trigger event and the rising edge on the common node will indicate which of the fault output nodes had been set to the fault state (and thus providing clues as to the location of the fault).

Nevertheless, in some implementations the first state may be a high state, and the second state may be a low state. Accordingly, a rising edge of the common node may indicate that a fault output node of at least one of the gate drivers has been set to the fault state. Then, after a predetermined time period from a trigger event, a falling edge of the common node may indicate the gate driver having the fault output node that had been set to the fault state. In other words, the length of time between the trigger event and the falling edge on the common node will indicate which of the fault output nodes had been set to the fault state (and thus providing clues as to the location of the fault).

The system may further include a controller connected to the common node. The controller may be configured to measure a length of time between the trigger event and the common node switching to the second state, and identify the gate driver corresponding to the detected fault based on the measured length of time and the predetermined time period of each respective timing arrangement.

The controller may therefore identify the gate driver having the fault output node that had been switched to the fault state by monitoring/measuring/determining a time between the trigger event and the common node switching to the second state. That is, the controller may consult a list of predetermined time periods and associated gate drivers, and match the time period elapsed from the trigger event and the common node switching to the second state to the list in order to ascertain the gate driver associated with the reported fault.

Of course, other means of providing the identity of the gate driver may be implemented in other implementations. For example, a sensor output may be provided to indicate the moment of the trigger event, followed by the moment the common node switches to the second state. A user may then be able to tell (from the amount of time from the two sensor outputs) which of the gate drivers has reported the fault.

The trigger event may be either the common node being set to the first state, or the fault output node of the respective gate driver being set to the operating state.

In other words, in some cases each of the timing arrangements are configured to delay an associated predetermined time period from when it sets the common node to the first state before releasing the common node from the first state. That is, the timing arrangement keeps the common node in the first state until the predetermined time period passes, at which point the common node is released from the first state.

In other cases, each of the timing arrangements are configured to delay an associated predetermined time period from when the fault output node of the associated gate driver is set to the operating state (from the fault state) before releasing the common node from the first state. Put another way, the timing arrangement waits a predetermined amount of time from a reset signal which resets each of the fault output nodes to the operating state.

When the trigger event is the common node being set to the first state, each timing arrangement may include a ramp generator and control logic. The ramp generator may be configured to generate a ramped output voltage responsive to the fault output node of the respective gate driver being set to the fault state. The control logic may be configured to set the common node to the first state responsive to the fault output node of the respective gate driver being set to a fault state and the ramped output voltage failing to meet a first voltage condition, and release the common node from the first state responsive to the ramped output voltage meeting the first voltage condition.

That is, the ramp generator outputs an increasing or decreasing voltage after the fault output node is set to the fault state. The control logic monitors the output voltage of the ramp generator, and compares the output voltage to a first voltage condition. Depending on the result of the comparison (e.g., whether the output voltage meets (satisfies) the first voltage condition or not), the common node is either set to the first state or released from the first state. The common node is released from the first state once the output voltage meets (satisfies) the first condition.

Accordingly, each timing arrangement is configured to set the common node to the first state, and release the common node from the first state after a predetermined time period from the trigger event (e.g., the common node being set to the first state). Either the rate at which the rate generator varies its associated output voltage, or the first voltage condition, may be set to ensure this operation according to the predetermined time period.

In some implementations, the ramp generator of each timing arrangement may be configured to generate the respective ramped output voltage such that the respective ramped output voltage meets the first voltage condition once the respective predetermined time period of the timing arrangement has elapsed from the trigger event. In this case, the first voltage condition of each timing arrangement may be the same.

In this case, the ramp generator of each timing arrangement is different in order to ensure that each timing arrangement has a different associated predetermined time period. Indeed, it will take each ramp generator a different amount of time for its associated output voltage to meet the first voltage condition.

Alternatively, the first voltage condition of each timing arrangement may be selected such that the ramped output voltage generated by the respective ramp generator meets the respective first voltage condition once the respective predetermined time period of the timing arrangement has elapsed from the trigger event.

In this case, the first voltage condition of each timing arrangement is different in order to ensure that each timing arrangement has a different associated predetermined time period. Indeed, if the ramp generator of each respective timing arrangement is the same, each ramp generator will require a different amount of time to meet the respective voltage condition of each timing arrangement.

The control logic of each timing arrangement may be further configured to set the common node to the first state responsive to the ramped output voltage meeting (satisfying) a second common voltage condition and the first voltage condition.

Accordingly, once the common voltage condition is met, the common node is re-set to the first state. This may be useful for continuing to indicate that a fault has been detected. That is, the common node will be set to the first state indicating a fault after being released for the purpose of indicating the identity of the gate driver reporting the fault.

In some cases, the ramp generator may include a capacitor, a current source, and a switch arranged to enable the current source to charge the capacitor responsive to the fault output node of the respective gate driver being set to the fault state.

This may provide a simple and cheap ramp generator for the purpose of the implementation. Nevertheless, other ramp generator arrangements are possible and would be readily appreciated by the skilled person.

The capacitance of the capacitor and/or an amperage of the current source of each ramp generator may be selected such that the respective ramped output voltage meets the first voltage condition once the respective predetermined time period of the timing arrangement has elapsed from the trigger event. In this case, the first voltage condition of each timing arrangement may be the same condition.

Indeed, the capacitor and/or current source of the ramp generator are parameters that may be altered to ensure that the output voltage meets the voltage condition after the respective predetermined time period.

When the trigger event is the fault output node of the respective gate driver being set to the operating state, each timing arrangement may include a ramp generator and control logic. The ramp generator may be configured to generate a ramped output voltage responsive to the fault output node of the respective gate driver being set to the operating state. The control logic may be configured to set the common node to the first state responsive to the fault output node of the respective gate driver being set to a fault state and the ramped output voltage failing to meet a voltage condition. The control logic may also be configured to release the common node from the first state responsive to the ramped output voltage meeting a voltage condition.

That is, the ramp generator outputs an increasing or decreasing voltage after the fault output node is set to the operating state (e.g., the fault output node is reset). The control logic sets the common node to the first state responsive to the fault output node being set to the fault state. The control logic then (once the fault output node is reset) monitors the output voltage of the ramp generator, and compares the output voltage to a voltage condition. The common node is released from the first state once the output voltage meets the first condition.

In some implementations, the ramp generator of each timing arrangement may be configured to generate the respective ramped output voltage such that the respective ramped output voltage meets the voltage condition once the respective predetermined time period of the timing arrangement has elapsed from the trigger event. In this case, the voltage condition of each timing arrangement may be the same.

Alternatively, the voltage condition of each timing arrangement may be selected such that the ramped output voltage generated by the respective ramp generator meets the respective voltage condition once the respective predetermined time period of the timing arrangement has elapsed from the trigger event.

The control logic of each timing arrangement may include a comparator configured to compare the ramped output voltage and a reference voltage (the reference voltage based on the voltage condition) to generate a comparison result, and set the common node to the first state or release the common node from the first state based on the comparison result.

In some implementations, the system may further include a biasing arrangement configured to bias the common node to the second state. Each timing arrangement may further include a switching arrangement connected to the common node, the switching arrangement of each respective timing arrangement configured to set the common node to the first state responsive to the fault output node of the respective gate driver being set to the fault state.

As a result of the biasing arrangement, the common node is switched to the second state once the common node is released from the first state. Meanwhile, the switching arrangement of each of the timing arrangements enables the timing arrangement to pull or switch the common node to the first state. Accordingly, when none of the switching arrangements pull the common node to the first state, the common node will be in the second state. When one or more of the timing arrangements, by the respective switching arrangements, switches the common node, the common node will be set to the first state until all timing arrangements allow the common node to be released.

In addition, there is provided a method for determining a location of a fault in a gate drive system including a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicating a detected fault by the respective gate driver and an operating state. The method includes:

It should be noted that these figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings.

To understand the present disclosure, it is important to understand the operation of a typical gate driver system.is a circuit diagram of a gate driver system.

As shown, each gate driver-provides input to a gate of a respective switch-(e.g., an IGBT, a GaN transistor, or a power MOSFET). Each gate driver-also provides the capacity for reporting that a fault has been detected. The fault may, for example, be an internal fault of the gate driver-, may correspond to the switch-or a component connected to the switch-. Specifically, each gate driver-reports the presence of a fault by a fault output node-. The fault output node-may be in an operating state (e.g., a high or clear state) indicating that no fault has been detected by the gate driver, or in a fault state (e.g., a low state) indicating that a fault has been detected by the respective gate driver.

Each of the fault output nodes-are typically connected together via one common node. As a result, if any one of the fault output nodes-is in a fault state, the common nodewill report that there is a fault. Thus, the gate driver-that detected the fault will not be derivable from information on the common node.

Specifically, each of the gate drivers-are usually configured to individually pull the common nodeto a low state (e.g., to ground) when they detect a fault. As the common nodeis biased to a high state (e.g., VDD), by a biasing arrangement, if none of the gate drivers-detect a fault then the common nodewill be in the high state. This binary system does not allow for the reporting of which of the gate drivers-has detected and reported a fault.

presents a simplified block diagram of an implementation of the implementation. Specifically,presents a gate driver systemthat enables the identification, by one common output node, of the gate driver-that has reported a fault.

Similarly to, the gate drive systemcomprises a plurality of gate drivers-. As described above, each gate driver-has a fault output nodeswitchable between a fault state and an operating state. There are three gate drivers-shown, but there may only be two gate drivers, or there may be more than three gate drivers.

In addition, there is provided a timing arrangement-for each of the gate drivers-. Each timing arrangement-is connected to the fault output node-of the respective gate driver-and a common node. That is, each gate driver-has a timing arrangement-connected between the fault output node-of the gate driver-and a common node. To be clear, all of the timing arrangements-are connected to the same common node.

Each timing arrangement-may be implemented separately from the gate driver-(e.g., connected to a pin of the gate driver-outputting a fault signal as the fault output node-). Alternatively, one or more components of the timing arrangement-may be implemented as part of the gate driver-, with the timing arrangement-connected to an internal fault node of the gate driver-as the fault output node-