A method of making an integrated circuit includes forming a first gate electrode structure extending in a first direction. The method further includes forming a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The method further includes forming a conductive feature, wherein the conductive feature includes: a first section electrically connected to the second portion, a second section electrically connected to the second gate structure, and a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction. The method further includes forming a third gate electrode structure extending in the first direction, wherein the third gate electrode structure is spaced from the first gate electrode structure in the first direction.
Legal claims defining the scope of protection, as filed with the USPTO.
. A method of making an integrated circuit, the method comprising:
. The method of, further comprising forming the first section, the second section and the third section on a same layer of an interconnect structure.
. The method of, wherein forming the third gate electrode comprises:
. The method of, wherein forming the third gate electrode comprises forming the third gate electrode electrically separated from the conductive feature.
. The method of, wherein forming the second gate electrode comprises forming the second gate electrode extending beyond the first gate electrode in the first direction.
. The method of, wherein forming the first gate electrode comprises forming the first gate electrode over a single active region.
. The method of, wherein forming the second gate electrode comprises forming the second gate electrode over a plurality of active regions.
. The method of, further comprising forming a first transistor, wherein forming the first transistor comprises:
. The method of, further comprising electrically connecting the conductive feature to the second gate electrode.
. A method of making an integrated circuit, the method comprising:
. The method of, further comprising forming a first source/drain (S/D) region between the first gate electrode and the third gate electrode in a plan view.
. The method of, further comprising forming a second S/D region between the second gate electrode and the third gate electrode in the plan view.
. The method of, further comprising forming a fourth gate electrode aligned with the first gate electrode, wherein the fourth gate electrode over is over the second active region and is spaced from the first active region.
. The method of, wherein forming the second gate electrode comprises forming the second gate electrode over the second active region.
. The method of, further comprising forming a via electrically connected to the third gate electrode.
. The method of, wherein forming the via comprises forming the via landing on the third gate electrode at a position spaced from each of the first active region and the second active region.
. A method of making an integrated circuit, the method comprising:
. The method of, wherein forming the plurality of gate electrode structures comprises:
. The method of, wherein forming the conductive feature comprises forming the conductive feature extending parallel to the first portion and the second portion.
. The method of, wherein forming the conductive feature comprises forming the conductive feature having a width greater than a width of the first portion, wherein width is measured in the second direction.
Complete technical specification and implementation details from the patent document.
The present application is a continuation of U.S. application Ser. No. 18/184,063, filed Mar. 15, 2023, which is a continuation of U.S. application Ser. No. 17/317,216, filed May 11, 2021, now U.S. Pat. No. 11,631,661, issued Apr. 18, 2023, which is a continuation of U.S. application Ser. No. 16/722,324, filed Jan. 16, 2020, now U.S. Pat. No. 11,024,622, issued Jun. 1, 2021, which is a continuation of U.S. application Ser. No. 15/233,126, filed Aug. 10, 2016, now U.S. Pat. No. 10,522,527, issued Dec. 31, 2019, which is a divisional of U.S. application Ser. No. 14/500,528, filed Sep. 29, 2014, now U.S. Pat. No. 9,431,381, issued Aug. 30, 2016, which are incorporated herein by reference in their entireties.
An integrated circuit (IC) is fabricated according to a set of layouts usable to form corresponding masks for selectively forming or removing various layers of features, such as active regions, gate electrodes, various layers of isolation structures, and/or various layers of conductive structures. Many fabrication processes are available to increase the spatial resolution of various layers of features and thus allow layout patterns to have a finer spatial resolution requirement in a corresponding layout. Some approaches usable for increasing the spatial resolution include using one or more fabrication processes such as ultraviolet lithography, extreme ultraviolet lithography, electron-beam lithography, and/or multiple-patterning. However, in many applications, a fabrication process offering a finer spatial resolution often comes with a higher cost, lower yield, and/or longer processing time. Having every layer of features of an IC fabricated by processes offering the same spatial resolution is not always economically feasible.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In accordance with one or more embodiments of the present disclosure, a gate electrode layout has a finer spatial resolution than a corresponding gate electrode cutting layout. By merging two gate electrode cutting layout patterns that are not spaced apart in compliance with the spatial resolution requirement of the gate electrode cutting layout and adding a remedial connecting layout pattern to a corresponding conductive layer for reestablishing an electrical connection interrupted as a result of the inclusion of the merged gate electrode cutting layout pattern, the violation of the spatial resolution requirement of the gate electrode cutting layout is resolved. In some embodiments, the system and method disclosed in the present application are applicable to cutting layouts usable in conjunction with conductive features other than gate electrodes.
are usable to illustrate one or more non-compliance scenarios and corresponding remedial measures. A systematic approach to implementing various remedial measures explained in conjunction withwill be further illustrated in conjunction with the flow chart of.further depicts a system usable to perform the method of.
is a layout diagramA of a portion of a circuit in accordance with some embodiments. Layout diagramA includes a plurality of gate electrode layout patterns,,,, andand two gate electrode cutting (CUT) layout patternsand. In some embodiments, gate electrode layout patterns,,,, andare part of a gate electrode layout, and CUT layout patternsandare part of a CUT layout. Other layout patterns and other layouts that are usable to fabricate the circuit are omitted.
Gate electrode layout patterns,,,, andare usable to fabricate gate electrode structures. The gate electrode structures corresponding to gate electrode layout patterns,,,, andextend along a first direction Y and have a predetermined spatial resolution along a second direction X. In some embodiments, the gate electrode structures corresponding to gate electrode layout patterns,,,, andare fabricated using a multiple patterning technology or other suitable processes offering the predetermined spatial resolution. In some embodiments, the gate electrode structures corresponding to gate electrode layout patterns,,,, andare polysilicon structures. In some embodiments, the polysilicon structures corresponding to gate electrode layout patterns,,,, andare further replaced by metallic materials to become metallic gate electrodes.
CUT layout patternsandare aligned along the X direction. CUT layout patternsandcorrespond to carve-out portions (e.g., regionsand) of the gate electrode structures fabricated according to gate electrode layout patternsand. In some embodiments, the CUT layout is usable in conjunction with one or more processes that do not offer as fine spatial resolution as the one or more processes for fabricating the gate electrode structures. As a result, the CUT layout has a predetermined spatial resolution requirement, and the spatial resolution of the gate electrode structures is finer than the spatial resolution requirement of the CUT layout in.
In, a minimum distance Dbetween CUT layout patternsandis less than a predetermined threshold distance. Therefore, CUT layout patternsandare too close to be in compliance with the spatial resolution requirement of the CUT layout. In some embodiments, CUT layout patternsandare too close to be implemented using a single mask. Further modification of the CUT layout in order to resolve the non-compliance of CUT layout patternsandwill be illustrated in conjunction with one or more of the following Figures.
is a layout diagramB of a portion of another circuit in accordance with some embodiments. Components inthat are the same or similar to those inare given the same reference numbers, and detailed description thereof is thus omitted.
Layout diagramB includes a plurality of gate electrode layout patterns,,,, andand two CUT layout patternsandcorresponding to CUT layout patternsandin. In some embodiments, gate electrode layout patterns,,,, andare part of a gate electrode layout, and CUT layout patternsandare part of a CUT layout. Other layout patterns and other layouts are usable to fabricate the circuit are omitted.
Compared with layout diagramA, CUT layout patternsandare not aligned along the X direction, i.e., they correspond to different y-coordinates. CUT layout patternsandcorrespond to carve-out portions (e.g., regionsand) of the gate electrode structures fabricated according to gate electrode layout patternsand. In some embodiments, the spatial resolution of the gate electrode structures is finer than the spatial resolution requirement of the CUT layout in.
In, a minimum distance Dbetween CUT layout patternsandis less than a predetermined threshold distance. Therefore, CUT layout patternsandare too close to be in compliance with the spatial resolution requirement of the CUT layout. Further modification of the CUT layout in order to resolve the non-compliance of CUT layout patternsandwill be illustrated in conjunction with one or more of the following Figures.
is a layout diagramA of a portion of a circuit in accordance with some embodiments. Layout diagramA depicts an example approach to modify the CUT layout in order to resolve the non-compliance of CUT layout patternsandin. Components inthat are the same or similar to those inare given the same reference numbers, and a detailed description thereof is thus omitted.
In, a stitching layout patternis introduced to connect CUT layout patternsandinto a merged CUT layout pattern. Merged CUT layout patternis included in the CUT layout in place of CUT layout patternsand. Merged CUT layout patternalso makes it possible to avoid separating two layout patterns by a distance Dthat is smaller than the spatial resolution requirement of the CUT layout. Thus, the inclusion of merged CUT layout patternmakes it possible to resolve the non-compliance of CUT layout patternsand. Stitching layout patternhas an I shape extending along the direction X. In some embodiments, stitching layout patternhas a shape other than the I shape extending along the direction X.
Stitching layout patternfurther corresponds to a carve-out portion (e.g., region) of the gate electrode structure fabricated according to gate electrode layout pattern. Carve-out regionis thus aligned with carve-out regionsandalong direction X. The gate electrode structure fabricated according to gate electrode layout patternis thus divided into two portions (corresponding to regionsand) separated by the carve-out portion corresponding to region. However, compared with the original layout as depicted in, the two portions (corresponding to regionsand) of the gate electrode fabricated according to layout patternare meant to be electrically connected.
is a layout diagramB of a portion of the circuit ofin accordance with some embodiments. Layout diagramB depicts an example approach to further modify a conductive layer layout to reestablish the electrical connections of one or more gate electrodes that are interrupted by the inclusion of stitching layout pattern. Components inthat are the same or similar to those inare given the same reference numbers, and detailed description thereof is thus omitted.
Layout diagramB depicts that a remedial connecting layout patternis added to a conductive layer layout usable for fabricating the IC. Remedial connecting layout patternis usable to fabricate a conductive feature electrically connecting two portions (corresponding to regionsand) of the gate electrode structure fabricated according to layout pattern. Remedial connecting layout patternhas an I shape extending along the direction Y and partially overlaps the regionsandof gate electrode layout pattern. In some embodiments, remedial connecting layout patternhas a shape other than the I shape extending along the direction Y.
is a layout diagramC of a portion of a circuit in accordance with some embodiments. Layout diagramC depicts an example approach to modify the CUT layout in order to resolve the non-compliance of CUT layout patternsandin. Components inthat are the same or similar to those inare given the same reference numbers, and detailed description thereof is thus omitted.
In, a stitching layout patternis introduced to connect CUT layout patternsandinto a merged CUT layout pattern. Merged CUT layout patternis included in the CUT layout in place of CUT layout patternsand. Merged CUT layout patternalso makes it possible to avoid separating two layout patterns with a distance Dthat is smaller than the spatial resolution requirement of the CUT layout. Thus, the inclusion of merged CUT layout patternmakes it possible to resolve the non-compliance of CUT layout patternsand. Stitching layout patternhas an L shape including one leg extending along the direction X and another leg extending along the direction Y. In some embodiments, stitching layout patternhas a shape other than the L shape depicted in.
Stitching layout patternfurther corresponds to a carve-out portion (e.g., region′) of the gate electrode structure fabricated according to gate electrode layout pattern. Carve-out region′ is thus aligned with carve-out regionbut not carve-out regionalong direction X. The gate electrode structure fabricated according to gate electrode layout patternincludes two portions (corresponding to regions′ and′) separated by the carve-out portion corresponding to region′. However, compared with the original layout as depicted in, the two portions (corresponding to regions′ and′) of the gate electrode fabricated according to layout patternare meant to be electrically connected.
is a layout diagramD of a portion of the circuit ofin accordance with some embodiments. Layout diagramD depicts an example approach to modify a conductive layer layout to reestablish the electrical connection of one or more gate electrodes that are interrupted by the inclusion of stitching layout pattern. Components inthat are the same or similar to those inare given the same reference numbers, and a detailed description thereof is thus omitted.
Layout diagramD depicts that a remedial connecting layout patternis added to a conductive layer layout usable for fabricating the IC. Remedial connecting layout patternis usable to fabricate a conductive feature electrically connecting two portions (corresponding to regions′ and′) of the gate electrode structure fabricated according to layout pattern. Remedial connecting layout patternhas an I shape extending along the direction Y and partially overlaps the regions′ and′ of gate electrode layout pattern. In some embodiments, remedial connecting layout patternhas a shape other than the I shape extending along the direction Y.
are diagrams of example stitching layout patterns in accordance with some embodiments.depicts a stitching layout patternthat has an I shape extending along the X direction.depicts a stitching layout patternthat has an I shape extending along the Y direction.depicts a stitching layout patternthat has an L shape with a first legextending along the X direction and a second legextending along the Y direction.depicts a stitching layout patternthat has a Z shape with a central portionextending along the X direction and a first legand a second legat corresponding ends of central portionand extending along the Y direction.
depicts a stitching layout patternthat has a slanted I shape. Stitching layout patternincludes a central portionextending along a direction having a predetermined angle θ to the Y direction. Stitching layout patternfurther includes two contact portionsandcorresponding to conductive structures for connecting two different gate structures or conductive structures that extend along the Y direction.depicts a stitching layout patternthat has a J shape with a central portionextending along the Y direction and a first legand a second legat corresponding ends of central portionand extending along the X direction. Legsandinclude contact portionsandcorresponding to conductive structures for connecting two different gate structures or conductive structures that extend along the Y direction.
depicts a stitching layout patternthat has a slanted I shape. Stitching layout patternincludes a central portionextending along a direction having a predetermined angle θ′ to the Y direction. Stitching layout patternfurther includes two contact portionsandcorresponding to conductive structures for connecting two different gate structures or conductive structures that extend along the Y direction. Compared with stitching layout patternin, central portionand contact portionsandare merged as a single convex polygon.
In some embodiments, a stitching layout pattern has a shape of a graphic combination of one or more of stitching layout patterns,,,,,, and. In some embodiments, a stitching layout pattern is a mirrored image of stitching layout patterns,,,,,, and. In some embodiments, a stitching layout pattern corresponds to stitching layout patterns,,,,,, and, rotated by a predetermined angle.
is a layout diagramA of a portion of a circuit in accordance with some embodiments. Components inthat are the same or similar to those inare given the same reference numbers, and detailed description thereof is thus omitted.
Compared with layout diagramA, the conductive layer layout where the remedial connecting layout patternwould be included already has layout patternsand. Layout patterncorresponds to forming a conductive structure connecting a portion of the gate electrode corresponding to layout patternand a first portion (corresponding to regionin) of the gate electrode corresponding to layout pattern. Layout patterncorresponds to forming another conductive structure connecting a portion of the gate electrode corresponding to layout patternand a second portion (corresponding to regionin) of the gate electrode corresponding to layout pattern. An I shape layout patternis generated as a tentative remedial connecting layout pattern corresponding to remedial connecting layout pattern. However, a minimum distance Dbetween tentative remedial connecting layout patternand layout patternand a minimum distance Dbetween tentative remedial connecting layout patternand layout patternare not in compliance with a spatial resolution requirement of the conductive layer layout.
is a layout diagramB of a portion of the circuit ofin accordance with some embodiments. Layout diagramB depicts an example approach to further modify the conductive layer layout to resolve the non-compliance of layout patterns of the conductive layer layout as a result of introducing tentative remedial connecting layout pattern. Components inthat are the same or similar to those inare given the same reference numbers, and detailed description thereof is thus omitted. In, a revised remedial connecting layout patternis generated by merging tentative remedial connecting patternand layout patternsand. Revised remedial connecting layout patternmakes it possible to avoid gaps corresponding to distance Dand distance D, and thus makes it possible to resolve the non-compliance of the spatial resolution requirement of the conductive layer layout.
In the embodiment depicted in, remedial connecting layout patternhas a Z shape as illustrated in conjunction with. In some embodiments, remedial connecting layout patternis replaced with a connecting layout pattern having a slanted I shape as illustrated in conjunction withor, or a J shape as illustrated in conjunction with.
is a layout diagramC of a portion of another circuit in accordance with some embodiments. Components inthat are the same or similar to those inare given the same reference numbers, and detailed description thereof is thus omitted.
Compared with layout diagramA, the conductive layer layout where the remedial connecting layout patternwould be included already has layout patternsand, and layout patterndoes not electrically connect the gate electrode corresponding to layout patternand the gate electrode corresponding to layout pattern. Moreover, a distance Dbetween tentative remedial connecting layout patternand layout patternis not in compliance with a spatial resolution requirement of the conductive layer layout.
is a layout diagramD of a portion of the circuit ofin accordance with some embodiments. Layout diagramD depicts an example approach to further modify the conductive layer layout to resolve the non-compliance of layout patterns of the conductive layer layout as a result of introducing tentative remedial connecting layout pattern. Components inthat are the same or similar to those inare given the same reference numbers, and detailed description thereof is thus omitted.
In, a revised remedial connecting layout patternis generated by merging tentative remedial connecting layout patternand layout patternin a manner similar to that illustrated in conjunction with. Layout patternis shifted further away from the region corresponding to tentative remedial connecting layout patternto become layout pattern. Also, to further adjusting layout patternand revised remedial connecting layout patternto be further away from each other, a revised CUT layout patternis introduced in place of merged CUT layout patternin order to allow an upper edgeof revised remedial connecting layout patternto be shifted further away from the region corresponding to layout pattern.
The resulting conductive layout includes layout patternsandin place of layout patterns,, and, and a distance Dbetween layout patternand layout patternis in compliance with the spatial resolution requirement of the conductive layout. In some embodiments, if the distance Dbetween layout patternand layout patternis still not in compliance with the spatial resolution requirement of the conductive layout, a circuit engineer or a layout engineer of the circuit/layout ofis notified, and a manual inspection and revision of the circuit and/or the corresponding layout are performed.
is a flow chart of a methodof processing a gate electrode cutting (CUT) layout in accordance with some embodiments.will be illustrated in conjunction with the examples depicted in. It is understood that additional operations may be performed before, during, and/or after the methoddepicted in, and that some other processes may only be briefly described herein.
The process begins with operation, where a layout design usable for fabricating an integrated circuit (IC) is received. The layout design includes a gate electrode layout usable to fabricate gate electrode structures and an original gate electrode cutting (CUT) layout correspond to various carve-out portions of the gate electrode structures. In some embodiments, the layout design further includes an original conductive layer layout usable to fabricate a layer of conductive features above the gate electrode structures. In some embodiments, the gate electrode layout includes layout patterns such as layout patterns,,,, andin. In some embodiments, the original CUT layout includes CUT layout patternsandinor CUT layout patternsandin.
The process proceeds to operation, where two CUT layout patterns of the original CUT layout are selected for further processing. In one example as depicted in, CUT layout patternsandare selected to be further processed according to various operations consistent with the method. In another example as depicted in, CUT layout patternsandare selected to be further processed according to various operations consistent with the method.
The process proceeds to operationto determine if the two selected CUT layout patterns are in compliance with a predetermined spatial resolution requirement of the CUT layout. In some embodiments, the predetermined spatial resolution requirement includes a predetermined threshold distance. Thus, the two selected CUT layout patterns are determined to be in compliance with the predetermined spatial resolution requirement if a distance between the two selected CUT layout patterns is equal to or greater than the predetermined threshold distance. In some embodiments, if the distance between the two selected CUT layout patterns is less than the predetermined threshold distance, the two selected CUT layout patterns are determined to be not in compliance with the predetermined spatial resolution requirement. For example, in some embodiments, operationincludes checking if a distance Dbetween CUT layout patternsandis less than the predetermined threshold distance. In some embodiments, operationincludes checking if a distance Dbetween CUT layout patternsandis less than the predetermined threshold distance.
In operation, the process is further branched into two different paths. If it is determined in operationthat the selected CUT layout patterns are in compliance with the spatial resolution requirement of the CUT layout, the process proceeds to operationto determine if all CUT layout patterns have been checked for their compliance with the spatial resolution requirement of the CUT layout. If it is determined in operationthat the CUT layout patterns are not in compliance with the spatial resolution requirement of the CUT layout, the process proceeds to operationfor further processes.
In operation, a merged CUT layout pattern is generated based on the selected CUT layout patterns and a stitching layout pattern connecting the selected CUT layout patterns. Based on the merged CUT layout pattern, a modified CUT layout is generated by replacing the selected CUT layout patterns with the merged CUT layout pattern. In one example as depicted in, a merged CUT layout patternis generated by connecting CUT layout patternsandwith stitching layout pattern. In another example as depicted in, a merged CUT layout patternis generated by connecting CUT layout patternsandwith stitching layout pattern.
In some embodiments, as illustrated in conjunction with, the stitching layout pattern usable in operationhas a shape including an I shape, such as stitching layout patternsand; an L shape, such as stitching layout pattern; a Z shape, such as stitching layout pattern; an slanted I shape, such as stitching layout patternsand/or; or a J shape, such as stitching layout pattern.
After operation, the process proceeds to operation, where a remedial connecting layout pattern is added to the conductive layer layout. The remedial connecting layout pattern corresponds to fabricating a conductive feature electrically connecting two portions of the gate electrode structure that are separated by the carve-out portion defined based on the stitching layout pattern. In one example as depicted in, remedial connecting layout patternis added for electrically connecting portions of the gate electrode structure corresponding to regionsand. In another example as depicted in, remedial connecting layout patternis added for electrically connecting portions of the gate electrode structure corresponding to regions′ and
In some embodiments, after generating the remedial connecting layout pattern, operationfurther includes checking if the remedial connecting layout pattern and other layout pattern of the conductive layer layout are in compliance with a predetermined spatial resolution requirement of the conductive layer layout. In some embodiments, if the inclusion of the remedial connecting layout pattern would render the conductive layer layout non-compliance with the spatial resolution requirement of the conductive layer layout, the process proceeds to operationto notify a circuit designer and/or a layout designer the non-compliance of the remedial connecting layout pattern.
In some embodiments, operationfurther includes adjusting layout patterns of the conductive layer layout to resolve the non-compliance of the predetermined spatial resolution requirement of the conductive layer layout. In some embodiments, an original conductive layout pattern and the remedial connecting layout pattern are merged to become a modified remedial connecting layout pattern in place of the conductive layout pattern, if electrically connecting the conductive features corresponding to the remedial connecting layout pattern and the original conductive layout pattern is consistent with a circuit schematic of the IC. For example, as depicted in, a modified remedial connecting layout patternis generated by merging the remedial connecting layout patternand ordinal conductive layout patternsand. For another example, as depicted in, a modified remedial connecting layout patternis generated by merging the remedial connecting layout patternand ordinal conductive layout pattern.
In some embodiments, an original conductive layout pattern and the remedial connecting layout pattern are adjusted to be further away from each other, if electrically connecting the conductive features corresponding to the remedial connecting layout pattern and the original conductive layout pattern is inconsistent with the circuit schematic of the IC.
In one example as depicted in, conductive layout patternis shifted further away from the region corresponding to remedial connecting layout pattern. Also, as depicted in, modified remedial connecting layout patternis shaped to be further away from the region corresponding to conductive layout pattern. In some embodiments, in order to facilitate the adjustment of the shape of modified remedial connecting layout pattern, a shape of the merged CUT layout patternis further adjusted to become adjusted merged CUT layout pattern, which is further away from a region corresponding to the conductive layout pattern.
In some embodiments, if the additional adjustment measures as illustrated in conjunction withstill fail to make the modified conductive layer layout to be in compliance with the spatial resolution requirement thereof, the process proceeds to operationto notify a circuit designer and/or a layout designer the non-compliance of the remedial connecting layout pattern.
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October 16, 2025
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