Method and System for Conditioning a Polishing Pad

The present disclosure relates generally to semiconductor workpieces and fabrication processes for semiconductor workpieces, such as semiconductor wafers used in semiconductor device fabrication.

Power semiconductor devices are used to carry large currents and support high voltages. A wide variety of power semiconductor devices are known in the art including, for example, transistors, diodes, thyristors, power modules, discrete power semiconductor packages, and other devices. For instance, example semiconductor devices may be transistor devices such as Metal Oxide Semiconductor Field Effect Transistors (“MOSFET”), bipolar junction transistors (“BJTs”), Insulated Gate Bipolar Transistors (“IGBT”), Gate Turn-Off Transistors (“GTO”), junction field effect transistors (“JFET”), high electron mobility transistors (“HEMT”) and other devices. Example semiconductor devices may be diodes, such as Schottky diodes or other devices.

Power semiconductor devices may be packaged into various semiconductor device packages, such as discrete semiconductor device packages and power modules. Power modules may include one or more power devices and other circuit components and can be used, for instance, to dynamically switch large amounts of power through various components, such as motors, inverters, generators, and the like.

Semiconductor devices may be fabricated from wide bandgap semiconductor materials, such as silicon carbide and/or Group III nitride-based semiconductor materials. The fabrication process for power semiconductor devices may require processing of wide bandgap semiconductor wafers, such as silicon carbide semiconductor wafers.

Aspects and advantages of embodiments of the present disclosure will be set forth in part in the following description, or can be learned from the description, or can be learned through practice of the embodiments.

One example aspect of the present disclosure is directed to a method for conditioning a polishing pad of a polishing system. The method includes performing an in-situ pad conditioning process and an ex-situ pad conditioning process. The in-situ pad conditioning process includes causing a pad conditioner to contact the polishing pad during a polishing operation. The ex-situ pad conditioning process is performed outside of the polishing operation and includes causing the pad conditioner to contact the polishing pad while a cleaning agent is applied to the polishing pad.

Another example aspect of the present disclosure is directed to a method for conditioning a polishing pad of a polishing system. The method includes performing an in-situ pad conditioning process, measuring a process condition, and changing the in-situ pad conditioning process based at least in part on the process condition. The in-situ pad conditioning process includes causing a pad conditioner to contact the polishing pad during a polishing operation.

Another example aspect of the present disclosure is directed to a system for polishing a semiconductor wafer. The system includes a platen operable to rotate about an axis, a polishing pad coupled to the platen, a workpiece carrier operable to bring a semiconductor workpiece into contact with the polishing pad, a pad conditioner, a sensor configured to measure a process condition, and a controller comprising one or more control devices operable to bring the pad conditioner into or out of contact with the polishing pad based at least in part on the process condition.

These and other features, aspects and advantages of various embodiments will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the related principles.

Reference now will be made in detail to embodiments, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation of the embodiments, not limitation of the present disclosure. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the scope or spirit of the present disclosure. For instance, features illustrated or described as part of one embodiment can be used with another embodiment to yield a still further embodiment. Thus, it is intended that aspects of the present disclosure cover such modifications and variations.

Power semiconductor devices are often fabricated from wide bandgap semiconductor materials, such as silicon carbide or Group III-nitride based semiconductor materials (e.g., gallium nitride). Herein, a wide bandgap semiconductor material refers to a semiconductor material having a bandgap greater than 1.40 eV. Aspects of the present disclosure are discussed with reference to silicon carbide-based semiconductor structures as wide bandgap semiconductor structures. Those of ordinary skill in the art, using the disclosures provided herein, will understand that example embodiments of the present disclosure may be used with any semiconductor material, such as other wide bandgap semiconductor materials, without deviating from the scope of the present disclosure. Example wide bandgap semiconductor materials include silicon carbide and the Group III-nitrides.

Power semiconductor devices may be fabricated using epitaxial layers formed on a semiconductor workpiece, such as a silicon carbide semiconductor wafer. Power semiconductor device fabrication processes may include surface processing operations that are performed on the silicon carbide semiconductor wafer to prepare one or more surfaces of the silicon carbide semiconductor wafer for later processing steps, such as surface implantation, formation of epitaxial layers, metallization, etc. Example surface processing operations may include grinding operations, lapping operations, and polishing operations.

Aspects of the present disclosure are discussed with reference to a semiconductor workpiece that is a semiconductor wafer that includes silicon carbide (“silicon carbide semiconductor wafer”) for purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand that aspects of the present disclosure can be used with other semiconductor workpieces. Other semiconductor workpieces may include carrier substrates, ingots, boules, polycrystalline substrates, monocrystalline substrates, bulk materials having a thickness of greater than 1 mm, such as greater than about 5 mm, such as greater than about 10 mm, such as greater than about 20 mm, such as greater than about 50 mm, such as greater than about 100 mm to 200 mm, etc.

Grinding is a material removal process that is used to remove material from the semiconductor wafer. Grinding may be used to reduce a thickness of a semiconductor wafer. Grinding typically involves exposing the semiconductor wafer to an abrasive containing surface, such as grind teeth on a grind wheel. Grinding may remove material of the semiconductor wafer through engagement with the abrasive surface.

Lapping is a precision finishing process that uses a loose abrasive in slurry form. The slurry typically includes coarser particles (e.g., largest dimension of the particles being greater than about 100 microns) to remove material from the semiconductor wafer. Lapping typically does not include engaging the semiconductor wafer with an abrasive-containing surface on the lapping tool (e.g., a wheel or disc having an abrasive-containing surface). Instead, the semiconductor wafer typically comes into contact with a lapping plate or a tile usually made of metal. Lapping typically provides better planarization of the semiconductor wafer relative to grinding.

Polishing is a process to remove imperfections and create a very smooth surface with a low surface roughness. Polishing may be performed using a slurry and a polishing pad. The slurry typically includes finer particles relative to lapping, but coarser particles relative to chemical mechanical planarization (CMP). Polishing typically provides better planarization of the semiconductor wafer relative to grinding.

CMP is a type of fine or ultrafine polishing, typically used to produce a smoother surface ready, for instance, for epitaxial growth of layers on the semiconductor wafer. CMP may be performed chemically and/or mechanically to remove imperfections and to create a very smooth and flat surface with low surface roughness. CMP typically involves changing the material of the semiconductor through a chemical process (e.g., oxidation) and removing the new material from the semiconductor wafer through abrasive contact with a slurry and/or other abrasive surface or polishing pad (e.g., oxide removal). In CMP, the abrasive elements in the slurry typically remove the product of the chemical process and do not remove the bulk material of the semiconductor wafer, often leaving very low subsurface damage.

Polishing tools (e.g., such as chemical mechanical polishing (CMP) tools) may be used after grinding operations to polish and/or smooth a semiconductor wafer surface. Polishing tools, such as CMP tools, may use a combination of chemical and mechanical forces to remove excess materials from a wafer surface, ensuring desired flatness and smoothness. Polishing tools, such as CMP tools, may include a rotating platen, polishing pad, and a slurry containing abrasive particles and chemical agents. As the wafer is pressed against the polishing pad and rotated, the slurry chemically reacts with and/or mechanically removes material, resulting in a highly planar and smooth surface.

Grinding and polishing silicon carbide semiconductor wafers may pose several challenges due to the inherent properties of the material. Silicon carbide is an extremely hard and brittle compound with a high level of abrasiveness, making the polishing process more demanding. One challenge is the potential for excessive tool wear and heat generation during grinding or polishing, which can affect the quality of the finished product. The hardness of silicon carbide may also lead to the formation of cracks or fractures if not properly managed, impacting the structural integrity of the material. Additionally, achieving precise dimensions and surface finishes can be challenging due to the resistance of silicon carbide to abrasion. Controlling parameters such as polishing pad selection, rotational speed, slurry composition, and/or cooling mechanisms may be important to overcoming these challenges and ensuring the successful fabrication of silicon carbide components with the desired properties and performance.

Pad conditioning is an important part of the polishing (e.g., CMP) process. Pad conditioning is the process of dressing the pad using a conditioning disk or dresser (e.g., a diamond pad conditioner) to remove the polish biproducts and particles adsorbed/absorbed on the pad material to avoid pad glazing and to regenerate a fresh pad surface asperity to maintain a uniform surface profile. The right choice of pad conditioning for silicon carbide polishing helps maintain high and consistent material removal rates and acceptable pad temperatures by reducing pad glazing.

Due to the very high chemical resistance and mechanical hardness, CMP of silicon carbide wafers is a challenging process. For silicon carbide workpiece processing in particular, CMP may be the most expensive fabrication step due to lengthy processing times. Additionally, there are benefits to using single wafer CMP processes, which offer wafer level process optimization and can achieve the desired material removal rate and surface finish in a more controlled and efficient manner. However, throughput is reduced when employing single wafer CMP processes if the cycle times and process parameters are not optimized. As such, it would be desirable to use more time efficient processes for polishing silicon carbide workpieces to increase throughput.

In some instances, for silicon carbide wafer polishing, the polishing pad is conditioned only ex-situ, or only between polishing of different wafers. However, according to examples of the present disclosure, the process can be improved by the use of in-situ pad conditioning, or pad conditioning during the polishing of a wafer. For example, in-situ conditioning can change the process temperature profile and material removal rate during polishing compared to using ex-situ conditioning alone. Additionally, ex-situ pad conditioning may be used in combination with in-situ pad conditioning due to the nature of the slurries (e.g., permanganate-based slurries) typically used for silicon carbide polishing. For instance, in some examples, a cleaning agent (e.g., reducing agent) may be used to clean the pad after polishing and regenerate the polishing pad for the next polishing cycle. However, cleaning agents containing reducing agents and/or organic compounds can cause redox type degradation reactions between the slurry and the cleaning agent, which can form particle agglomerates (e.g., manganese dioxide), leading to excessive scratches. Therefore, the use of such cleaning agents may be avoided during in-situ pad conditioning and employed only during ex-situ pad conditioning.

The in-situ pad conditioning can be performed at the beginning of polishing, at the end of polishing, intermittently during polishing (e.g., at regular or irregular intervals), or continuously throughout the entire polishing process. However, in some instances, continuous conditioning can cause rapid degradation of the pad and thus shortened pad conditioner life. Continuous pad conditioning can also affect the pad surface temperature and the roughness profile. Therefore, according to examples of the present disclosure, intermittent or segmented in-situ pad conditioning may be performed, and in-situ pad conditioning can be started and stopped based on a preset schedule or based on various process conditions.

In this regard, example aspects of the present disclosure are directed to methods for conditioning a polishing pad of a polishing system. In some embodiments, the method includes performing an in-situ pad conditioning process and an ex-situ pad conditioning process outside of the polishing operation. The in-situ pad conditioning process includes causing a pad conditioner to contact the polishing pad during a polishing operation. The ex-situ pad conditioning process includes causing the pad conditioner to contact the polishing pad while a cleaning agent is applied to the polishing pad.

In some embodiments, the method includes performing the in-situ pad conditioning process, measuring a process condition, and changing the in-situ pad conditioning process based at least in part on the process condition.

A system for polishing a semiconductor workpiece is also provided. The system includes a platen operable to rotate about an axis, a polishing pad coupled to the platen, a workpiece carrier operable to bring a semiconductor workpiece into contact with the polishing pad, a pad conditioner, a sensor configured to measure a process condition, and a controller comprising one or more control devices operable to bring the pad conditioner into or out of contact with the polishing pad based at least in part on the process condition.

Aspects of the present disclosure provide technical effects and benefits, For instance, the use of such processes and systems according to examples of the present disclosure can improve throughput by reducing the frequency and/or duration of ex-situ conditioning required. Additionally, aspects of the present disclosure may increase material removal rates during polishing, which can further improve throughput while also reducing slurry consumption rates.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be understood that when an element such as a layer, structure, region, or substrate is referred to as being “on” or extending “onto” another element, it may be directly on or extend directly onto the other element or intervening elements may also be present and may be only partially on the other element. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present, and may be partially directly on the other element. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

As used herein, a first structure “at least partially overlaps” or is “overlapping” a second structure if an axis that is perpendicular to a major surface of the first structure passes through both the first structure and the second structure. A “peripheral portion” of a structure includes regions of a structure that are closer to a perimeter of a surface of the structure relative to a geometric center of the surface of the structure. A “center portion” of the structure includes regions of the structure that are closer to a geometric center of the surface of the structure relative to a perimeter of the surface. “Generally perpendicular” means within 15 degrees of perpendicular. “Generally parallel” means within 15 degrees of parallel.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “lateral” or “vertical” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Embodiments of the disclosure are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Similarly, it will be understood that variations in the dimensions are to be expected based on standard deviations in manufacturing procedures. As used herein, “approximately” or “about” includes values within 10% of the nominal value.

Like numbers refer to like elements throughout. Thus, the same or similar numbers may be described with reference to other drawings even if they are neither mentioned nor described in the corresponding drawing. Also, elements that are not denoted by reference numbers may be described with reference to other drawings.

Some embodiments of the invention are described with reference to semiconductor layers and/or regions which are characterized as having a conductivity type such as n type or p type, which refers to the majority carrier concentration in the layer and/or region. Thus, N type material has a majority equilibrium concentration of negatively charged electrons, while P type material has a majority equilibrium concentration of positively charged holes. Some material may be designated with a “+” or “−” (as in N+, N−, P+, P−, N++, N−−, P++, P−−, or the like), to indicate a relatively larger (“+”) or smaller (“−”) concentration of majority carriers compared to another layer or region. However, such notation does not imply the existence of a particular concentration of majority or minority carriers in a layer or region.

In the drawings and specification, there have been disclosed typical embodiments and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation of the scope set forth in the following claims.

depicts an example polishing systemfor a semiconductor workpiece (e.g., silicon carbide wafer)according to example embodiments of the present disclosure. The polishing systemis a CMP system operable to perform one or more polishing operations for a silicon carbide wafer. The silicon carbide wafermay include 4H silicon carbide, 6H silicon carbide, or another crystal structure. The silicon carbide wafermay be an on-axis workpiece (e.g., end face parallel to the (0001) plane) or an off-axis workpiece (e.g., end face non-parallel to the (0001) plane). The polishing operation may be performed on a carbon face or a silicon face of the silicon carbide wafer. The silicon carbide wafermay be doped or undoped. In some embodiments, the silicon carbide wafer has a diameter from about 100 mm to about 300 mm, such as about 100 mm, such as about 150 mm, such as about 200 mm. In some examples, the polishing systemincludes a platenwith a polishing pad, a workpiece carrier, a delivery system, a pad conditioner, and a controller.

More specifically, the polishing systemincludes the platen. The platenmay be operable to rotate about an axis. The platenmay be operable to rotate about the axisin either a clockwise or counterclockwise direction. In some examples, the platenmay rotate, for instance, at a rotational speed in a range of about 10 rpm to about 10000 rpm, such as about 10 rpm to about 7500 rpm, such as about 10 rpm to about 2000 rpm, such as about 10 rpm to about 1000 rpm, such as about 10 rpm to about 500 rpm, such as about 10 rpm to about 120 rpm.

The platenmay include a receptacle. The receptaclemay be configured to hold a polishing padfor a CMP process. The receptaclemay be a surface configured to support or receive the polishing pad. In some examples, the receptaclemay be a planar surface that supports the polishing pad.

The polishing padmay provide a surface for polishing the silicon carbide semiconductor wafer. The polishing padmay include durable and chemically resistant materials such as polyurethane and/or polyether ether ketone (PEEK) material. The polishing padmay have a surface with a specified roughness and porosity to facilitate polishing a silicon carbide semiconductor wafer. The polishing padmay include grooves or dimples to increase slurry distribution and reduce edge effects during the CMP process. The polishing padmay include a cushioning layer (e.g., foam or rubber), in some examples, to facilitate adaptation of the polishing padto the topography of the semiconductor wafer, providing improved planarity of the semiconductor wafer.

The polishing padmay have a diameter. The diameter may be greater than a size of the silicon carbide semiconductor wafer. The polishing padmay have a diameter in a range of, for instance, about 150 mm to about 820 mm, such as in a range of about 150 mm to about 400 mm, such as in a range of about 150 mm to about 300 mm. In some examples, the diameter of the polishing padmay be smaller or nearly the same size as the diameter of the platen(). However, the diameter of the polishing padmay be larger than the diameter of the platenwithout deviating from the scope of the present disclosure. In some examples, the polishing padmay have a thickness in a range of about 2 mm to about 40 mm, such as in a range 5 mm to about 40 mm, such as in a range of about 10 mm to about 40 mm.

In some examples, the polishing systemincludes a delivery system. The delivery systemmay be used to deliver a slurry to the polishing padon the platenduring a CMP process, for instance, from a slurry delivery outlet. In some embodiments, the slurry delivery outletmay include a nozzle for delivering the slurry. In some examples, the slurry may include an oxidizing agent. For example, the oxidizing agent may include, potassium hypochlorite, sodium hypochlorite, ammonium persulfate, potassium peroxymonosulfate, sodium permanganate, potassium permanganate, potassium periodate, or potassium persulfate. In some example embodiments, the oxidizing agent may include sodium permanganate and/or potassium permanganate and optionally one or more other oxidizing agents, such as those listed above. Other suitable slurries with one or more abrasive elements (e.g., abrasive particles) may be used without deviating from the scope of the present disclosure.

The delivery systemmay further include fluid delivery outlet. The fluid delivery outletmay be configured to provide a cleaning agent. In some embodiments, the fluid delivery outletmay include a nozzle for delivering the cleaning agent. The cleaning agent may include a reducing agent. In some embodiments, for example, the reducing agent may include hydrogen peroxide, urea peroxide, carboxylic acids (e.g., citric acid, oxalic acid, and the like), hydrazine, hydrophosphorous acid, phosphorous acid, sulfurous acid, sodium metabisulfite, ammonium metabisulfite, potassium metabisulfite, ascorbic acid, L(+)-ascorbic acid, isoascorbic acid, hydroxylamine, hydroxylamine salts, dimethylhydroxylamine, diethylhydroxylamine, reducing sugars chosen from galactose, xylose, glucose, fructose, lactose and maltose, hydroquinone, catechol, tetrahydrofulvalene, N,N-dimethylanilinebenzylamine, or a mixture thereof. The delivery systemmay further include one or more additional fluid delivery outlets (not shown), which can dispense one or more additional fluids (e.g., coolant, additive, lubricant, etc.) to the polishing padduring a polishing process. In some examples, the delivery systemmay include an additive delivery systemconfigured to deliver one or more additives (e.g., oxidizing material, oxide removal material) either with the slurry through the slurry delivery outletor separate from the slurry through an additional fluid delivery outlet.

Aspects of the present disclosure are discussed with reference to providing a slurry and/or a cleaning agent to the polishing padthrough fluid delivery outletsandfor purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand that the delivery systemmay deliver materials (e.g., slurry, oxidizing materials, oxide removal materials, cleaning agent) to the polishing padin various ways without deviating from the scope of the present disclosure, such as from a plurality of fluid delivery outlets, from apertures in the platen and/or the polishing pad, or from other fluid delivery techniques.

In some examples, the polishing systemincludes a workpiece carrier. The workpiece carrieris operable to bring one or more silicon carbide semiconductor wafersinto contact with the polishing padto implement a polishing process. In some examples, the workpiece carriermay be operable to hold a single silicon carbide semiconductor waferfor single wafer processing. In some examples, the workpiece carriermay be operable to hold a plurality of silicon carbide semiconductor wafersfor batch processing. As explained above, the methods described herein, in some instances, are particularly useful for single wafer processing due to the need for improved efficiency to increase throughput. However, the methods are similarly useful for batch processing.

The workpiece carriermay be operable to rotate the silicon carbide semiconductor waferabout an axis. The axisis not aligned with the axisassociated with the platen. The workpiece carriermay be operable to rotate the silicon carbide semiconductor waferabout the axisin either a clockwise or counterclockwise direction. In some examples, the workpiece carriermay rotate, for instance, at a rotational speed in range of about 10 rpm to about 10000 rpm, such as about 10 rpm to about 7500 rpm, such as about 10 rpm to about 2000 rpm, such as about 10 rpm to about 1000 rpm, such as about 10 rpm to about 500 rpm, such as about 10 rpm to about 120 rpm. The workpiece carriermay rotate in the same direction as the platenor in a different direction relative to the platen.

The workpiece carriermay be able to provide a downforceof the silicon carbide semiconductor waferagainst the polishing pad. The downforceof the workpiece carriermay be controlled to adjust the polishing rate of the polishing process of the silicon carbide semiconductor wafer.

The workpiece carriermay also oscillate in a lateral direction along the surface of the polishing pad. This will allow exposure of the semiconductor waferto different portions of the polishing pad(e.g., at different radii of the polishing pad) during a polishing operation.

The polishing systemmay include a pad conditioner. The pad conditionermay rotate about an axis, such that the pad conditionerrotates along the surface of the polishing pad(e.g., in either a clockwise or counterclockwise direction). In some examples, the pad conditionermay be on a swing armthat may swing about an axisto move the pad conditionerto different locations on the polishing pad. The pad conditionermay include an abrasive-containing material having one or more abrasive elements (e.g., diamond) that are used to condition or dress the polishing padas the polishing padis subject to glazing during a polishing process. In some embodiments, the abrasive elements may include one or more of: (i) diamond; (ii) ceramic; (iii) metal carbide; (iv) metalloid nitride (e.g., silicon nitride); (v) metalloid oxide; (vi) metalloid carbide (e.g., silicon carbide); (vii) carbon group nitride; (viii) carbon group oxide; (ix) carbon group carbide, (x) boron nitride (e.g., c-BN or w-BN), or any other suitable abrasive materials having a similar hardness.