Operational Amplifier Circuit and Operational Amplifier Compensation Circuit for Amplifying Input Signal at High Slew Rate

This application claims priority under 35 U.S.C. § 120 to U.S. patent application Ser. No. 17/691,428, filed on Mar. 10, 2022, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0062745 filed on May 14, 2021, and Korean Patent Application No. 10-2021-0095157 filed on Jul. 20, 2021, the collective subject matter of which are hereby incorporated by reference in their entireties.

The inventive concept relates generally to operational amplifier circuits and operational amplifier compensation circuits. More particularly, the inventive concept relate to operational amplifier circuits providing high slew rates, as well as operational amplifier compensation circuits associated with same.

Display devices are widely used in smartphones, notebook computers, and monitors and often include a display panel configured to display an image. Here, the display panel includes a vast plurality of pixels driven by a data signal generated by a display driver integrated circuit (IC). The nature and quality of the data signal is an important factor in the display of the image by the display panel.

In this regard, the display driver IC should shorten a settling time of a source amplifier so as to drive the pixels at a high slew rate. Here, “settling time” may be understood as a time required for an output signal (e.g., a signal corresponding to an input signal) to fall within a defined range associated with a stable state value. A reduced settling time improves resolution, as well as a frame rate, of an image provided by the display panel.

Embodiments of the inventive concept provide operational amplifier circuits and operational amplifier compensation circuits that efficiently reduce settling time.

According to an aspect of the inventive concept, an operational amplifier compensation circuit may include; a first transistor activated/deactivated in response to a signal level difference between an input signal applied to an operational amplifier and an output signal provided by the operational amplifier, a first signal amplifying circuit including a second transistor and a first load, wherein the first signal amplifying circuit is configured to generate a first gate voltage amplified in response to the voltage level difference between the input signal and the output signal in relation to an internal resistance of the second transistor and a resistance of the first load when the first transistor is activated, and a third transistor configured to generate a first compensation current in response to the amplified first gate voltage and provide the first compensation current to the operational amplifier.

According to another aspect of the inventive concept, an operational amplifier circuit may be used to compensate for a slew rate of an output signal provided by the operational amplifier circuit, wherein operational amplifier circuit may include; an amplifying circuit configured to provide an amplification signal by amplifying a difference between an input signal applied to the operational amplifier circuit and the output signal, an output circuit configured to generate the output signal in response to the amplification signal, and a compensation circuit configured to receive the amplification signal and provide a compensation current generated in response to the amplification signal to the output circuit, wherein the output circuit is further configured to generate the output signal in relation to the compensation current to reduce a signal level shift time.

According to another aspect of the inventive concept, an operational amplifier compensation circuit may include; a first input transistor configured to generate a first current in response to a difference between an input signal applied to an operational amplifier and an output signal provided by operational amplifier, a first current mirror circuit connected to a source/drain of the first input transistor and generating a second current having a same level as a level of the first current, a second current mirror circuit configured to receive the second current and generate a third current, and an additional compensation circuit including a first additional compensation transistor and a first load, wherein the additional compensation circuit is configured to provide the second current mirror circuit with an additional compensation current generated in response to an internal resistance of the first additional compensation transistor and a resistance of the first load when the first input transistor is activated, wherein a compensation current obtained by summating the additional compensation current and the third current is provided to the operational amplifier.

Throughout the written description and drawings, like reference numbers and labels are used to denote like or similar elements, components and/or features.

Figure (FIG.)is a block diagram illustrating an operational amplifier.

Referring to, the operational amplifiermay include an input circuit, an amplifying circuit, and an output circuit.

The input circuitmay receive as inputs; an input signal IN applied to the operational amplifierand an output signal OUT provided by the operational amplifier. The input circuitmay output a differential current in response to a voltage difference between the input signal IN and the output signal OUT. For example, the input circuitmay receive the input signal IN through a first (or positive +) input terminal may receive the output signal OUT through a second (or negative −) input terminal.

The amplifying circuitmay include a plurality of resistors that receive the differential current generated by the input circuitand generate an amplified voltage signal in response to the differential current. For example, the amplifying circuitmay include passive and/or active resistors having a high resistance value and may output an amplification signal having a voltage level obtained by multiplying a level of the differential current by a resistance value. In some embodiments, the amplifying circuitmay output the amplification signal through a plurality of output terminals, and the output circuitmay receive the amplification signal through a plurality of input terminals.

The output circuitmay receive the amplification signal and generate the output signal OUT as an amplified response to the input signal IN. For example, the output circuitmay include a capacitor that stores electrical charge received as the amplification signal and may generate the output signal OUT in response to (or in proportion to) the electrical charge stored in the capacitor.

However, as the operational amplifiergenerates the output signal OUT using the combination of the input circuit, the amplifying circuit, and the output circuit, a delay may arise due to the charging/discharging of electrical charge by the capacitor. As a result of this signal processing delay, a compensating “delay time” is required, such that the output signal OUT corresponding to the input signal IN settles within a defined range associated with a stable state value. This delay time may be referred to as a “settling time.”

is a block diagram illustrating the operational amplifieroftogether with an operational amplifier compensation circuitaccording to embodiments of the inventive concept.

Referring to, the operational amplifier compensation circuitmay be used in conjunction with the operational amplifier circuitto decrease delay. In this regard, the operational amplifier compensation circuitmay provide a compensation current Icomp to at least one of the amplifying circuitand the output circuit, thereby decreasing delay associated with operation of the operational amplifier. For example, the operational amplifier compensation circuitmay provide the compensation current Icomp to a capacitor included in one of the amplifying circuitand the output circuit, in order to adjust (e.g., increase) a charge rate and/or a discharge rate of the capacitor.

In various embodiments, the operational amplifier compensation circuitmay receive the input signal IN applied to the operational amplifierand an output signal OUT provided by the operational amplifierin order to generate the compensation current Icomp in response to a signal level difference between the input signal IN and the output signal OUT. Accordingly, a level of the compensation current Icomp may be proportional to a voltage level obtained by multiplying a drain current level (e.g., a level generated in response to the signal level difference between the input signal IN and the output signal OUT) by a resistance value of an element included in the operational amplifier compensation circuit. That is, the operational amplifier compensation circuitmay provide the operational amplifierwith the compensation current Icomp having a level that is amplified in response to a drain current. Hereinafter, an amplified level of the compensation current Icomp in response to the drain current may be referred to as a “gain level.”

In some embodiments, the operational amplifier compensation circuitmay further receive an amplification signal AMP—different from the input signal IN and the output signal OUT—the operational amplifier, and may adjust a gain level corresponding to the drain current in response to the amplification signal AMP. In some embodiments, the operational amplifier compensation circuitmay further include a source degeneration transistor having an activation level that is determined in response to a level of the amplification signal AMP, such that when the source degeneration transistor is activated, the gain level may be reduced and a stable compensation current Icomp and output signal OUT may be generated.

is a graph comparing output signal OUT slew rates between a comparative example and an embodiment of the inventive concept.

That is, referring to, performance of the operational amplifier, standing alone, verses performance of the operational amplifiertogether with the operational amplifier compensation circuitare compared-particularly as relates to slew rate. Namely, the slew rate of the output signal OUT is much higher when the operational amplifier compensation circuitis used in combination with the operational amplifier. And given this higher slew rate, the settle time required for the output signal OUT to reach range associated with a stable state value may be reduced. That is, operational amplifier circuits including the operational amplifier compensation circuitaccording to embodiments of the inventive concept may exhibit a reduced settling time t.

This is a material outcome because when display apparatuses are driven at high speed, comparative operational amplifier circuits may provide insufficient margin of the settling time t, thereby generating the output signal OUT with a less accurately defined voltage level. In this regard, the margin of the settling time tmay denote a time other than (or in addition to) the settling time tduring a period in which the display apparatus is driven at high speed. For example, in one comparative example assuming that a display apparatus is driven at 144 Hz or higher, the margin of the settling time tmay be insufficient, and display luminance may decrease by a voltage difference which does not reach a stable state value. This may be regarded as a latent defect factor.

In contrast, operational amplifier circuits according to embodiments of the inventive concept generate a compensation current using the operational amplifier compensation circuitthat ensures the margin of the settling time t. Accordingly, a display apparatus incorporating an operational amplifier circuit according to embodiments of the inventive concept may operate at high speed, yet stably output an image having a desired luminance.

is a circuit diagram further illustrating in one example the operational amplifierof.

Referring to, the operational amplifierincludes the input circuit, the amplifying circuit, and the output circuit. Each of the input circuit, the amplifying circuit, and the output circuitmay include transistor, wherein for each transistor, a gate terminal (or gate), a source terminal (or source), and/or a drain terminal (or drain) may be organically connected to different transistor(s) and may output an output signal OUT and at least one amplification signal (e.g., first and second amplification signals AMPand AMP). Hereafter, one of a source or a drain of a transistor will be denoted by the term “source/drain.”

In some embodiments, the input circuitmay include a folded-cascode operational transconductance amplifier (OTA). The folded-cascode OTA may be used to convert a voltage difference into a current, and then variously communicate the current. For example, the input circuitmay include P-type Metal Oxide Semiconductor (MOS) (PMOS) transistors MP, MPand MP, include N-type MOS (NMOS) transistors MN, MNand MN, receive the input signal IN, and provide the output signal OUT as a differential current.

That is, the input circuitmay include a first differential input circuit including the transistor MPand the transistor MP, and a second differential input circuit including the transistor MNand the transistor MN. The transistor MPand the transistor MNmay supply a bias current to the first differential input circuit and the second differential input circuit.

The transistor MPmay apply a constant bias current to the first differential input circuit in response to a first bias voltage VB, and the transistor MNmay apply a constant bias current to the second differential input circuit in response to a second bias voltage VB.

Each of the first differential input circuit and the second differential input circuit may separate a bias current in response to a differential input signal and may output a separated current as a differential current to the amplifying circuit. That is, the input circuitmay convert a voltage difference between the input signal IN and the output signal OUT into a current and may output the current to the amplifying circuit.

The amplifying circuitmay include a current mirror circuit including PMOS transistors MP, MP, MP, MP, MPand MP, and NMOS transistors MN, MN, MN, MN, MNand MN. The amplification circuitmay amplify the differential current input from the input circuit. The NMOS transistors MN, MN, MNand MNof the amplifying circuitmay be connected to the first differential input circuit, and the PMOS transistors MP, MP, MP, and MPmay be connected to the second differential input circuit.

The transistor MPand the transistor MPmay be serially connected between a source voltage VDD and each of the transistor MPand the transistor MN, and the transistor MPand the transistor MPmay be serially connected between the source voltage VDD and each of the transistor MPand the transistor MN. The transistor MNand the transistor MNmay be serially connected between ground, and each of the transistor MPand the transistor MN, and the transistor MNand the transistor MNmay be serially connected between ground and each of the transistor MPand the transistor MN. A third bias voltage VBmay be applied to the gates of the transistors MPand MP, and a fourth bias voltage VBmay be applied to the gates of the transistors MNand MN.

The PMOS transistor MPand the NMOS transistor MNmay be connected in parallel and may respectively receive a fifth bias voltage VBand a sixth bias voltage VBto generate a constant static bias current. The PMOS transistor MPand the NMOS transistor MNmay be connected in parallel and may respectively receive a seventh bias voltage VBand an eighth bias voltage VBto generate a constant static bias current.

The output circuitmay include first and second capacitors Cand C, a PMOS transistor MP, and an NMOS transistor MN. The output circuitmay receive amplified voltages from the transistor MPand the transistor MNto generate the amplification signals AMPand AMP. The first and second capacitors Cand Cmay be used to stabilize frequency characteristic(s) of the output signal OUT. Thus, under certain conditions, the first and second capacitors Cand Cmay prevent the output signal OUT from being generated.

A source of the transistor MPof the output circuitmay be connected to the source voltage VDD, a gate thereof may be connected to a drain of the transistor MP, and a drain thereof may be connected to a drain of the transistor MNand an output terminal at which the output signal OUT is apparent. A source of the transistor MNmay be connected to ground, a gate thereof may be connected to a drain of the transistor MN, and a drain thereof may be connected to a drain of the transistor MPand an output terminal at which the output signal OUT is apparent.

The input circuitdescribed above may be biased by direct current (DC) bias voltages VBand VB, and thus, a slew rate based thereon may be expressed by Equation 1 below.

wherein, Idenotes a DC bias current value generated from the DC bias voltage VBor VB, and Cdenotes a capacitance value associated with at least one of the first and second capacitors Cand Cof the output circuit.

In this case, in some embodiments, a slew rate of the operational amplifierreceiving the compensation current Icomp may be expressed by Equation 2 below.

wherein Icomp denotes the compensation current Icomp generated by the operational amplifier compensation circuit.

That is, a slew rate of the output signal OUT generated by receiving the compensation current Icomp may have a value which is greater than a slew rate of the output signal OUT generated in the absence of the compensation current Icomp.

is a circuit diagram illustrating a variation () of the operational amplifier compensation circuitofaccording to embodiments of the inventive concept.

Referring to, the operational amplifier compensation circuitmay include a first partial compensation circuit including first, second, third, fifth and sixth transistors TR, TR, TR, TRand TRand a second partial compensation circuit including seventh, eighth, ninth, eleventh and twelfth transistors TR, TR, TR, TRand TR. When a voltage level difference between an output signal OUT and an input signal IN is greater than a threshold voltage of the first transistor TR, the first partial compensation circuit may be controlled so that an operational amplifierprovides a compensation current Icomp to an operational amplifier compensation circuit, and when the voltage level difference between the input signal IN and the output signal OUT is greater than a threshold voltage of the seventh transistor TR, the second partial compensation circuit may be controlled to provide the compensation current Icomp to the operational amplifier. That is, the first partial compensation circuit may operate when the input signal IN shifts from low to high, and the second partial compensation circuit may operate when the input signal IN shifts from high to low.

The first partial compensation circuit may include the first transistor TR, a first signal amplifying circuit, and the third transistor TR. The first transistor TRmay be activated when the voltage level difference between the input signal IN and the output signal OUT is greater than a threshold voltage thereof. When the first transistor TRis activated, the first transistor TRmay generate a drain current proportional to the voltage level difference between the input signal IN and the output signal OUT.

The first signal amplifying circuitmay include the second transistor TR, the fifth transistor TR, and the sixth transistor TR. A gate and a drain of the sixth transistor TRmay be connected to a drain of the first transistor TR. Thus, the sixth transistor TRmay be self-biased. A gate of the second transistor TRmay be connected to the gate of the sixth transistor TR, and the second transistor TRand the sixth transistor TRmay configure a current mirror. Therefore, a drain current of the first transistor TRmay be copied to a drain current of the second transistor TR.

The fifth transistor TRincluded in the first signal amplifying circuitmay be connected to a drain of the second transistor TRand may receive a first bias signal Biasthrough a gate thereof, and thus, may operate as a load having a variable resistance value in response to a voltage level of the first bias signal Bias. In relation to the operational amplifier compensation circuitof, a load disposed between ground and a drain of the second transistor TRmay be an active load configured with a transistor as illustrated in, however the scope of the inventive concept is not limited thereto, and other embodiments may be configured with a passive load.

In some embodiments, the second transistor TRof the first signal amplifying circuitmay operate as a common source amplifier, where the fifth transistor TRis a load. A voltage gain of the common source amplifier may be expressed by Equation 3 below.

wherein ‘Rd’ denotes a resistance value of a load connected to an output terminal of the common source amplifier, and ‘ro’ denotes an internal resistance of a transistor.

Referring still to, the load connected to the output terminal of the common source amplifier may be the fifth transistor TR, and thus, Rd may denote a resistance value of the fifth transistor TRand ro may denote an internal resistance (e.g., a second internal resistance) of the second transistor TR. That is, an output voltage value of the first signal amplifying circuitmay have a voltage value amplified in response to the internal resistance of the second transistor TRand an internal resistance (e.g., a fifth internal resistance) of the fifth transistor TRwith respect to a difference between the input signal IN and the output signal OUT.