Silicon Carbide Planar Mosfet Device and Manufacturing Method Therefor

The present invention relates to the field of semiconductor devices and manufacturing technologies therefor, and in particular, to a planar silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method therefor.

A SiC MOSFET device has advantages such as a high switching speed and low on-resistance, and can achieve a high breakdown voltage level with a smaller drift layer thickness, thereby reducing a volume of a power switch module and reducing energy consumption. The MOSFET device has significant advantages in application fields such as power switches and converters.

Planar SiC MOSFET devices are widely used due to advantages such as simple processes, good cell consistency, and high avalanche energy. However, how to further improve performance of the planar SiC MOSFET device has also become one of the hotspot problems that have been studied by persons skilled in the art.

An objective of the present invention is to provide a planar SiC MOSFET device and a manufacturing method therefor, to improve performance of a planar SiC MOSFET device.

To achieve the foregoing objective, the present invention provides a planar SiC MOSFET device. The planar SiC MOSFET device includes:

Optionally, the crystal plane having the channel mobility higher than that of the () crystal plane includes a () crystal plane, a () crystal plane, or a () crystal plane.

Optionally, a plurality of trenches are sequentially arranged side by side and spaced apart in a length direction of the gate, and any two of the trenches are not in communication or at least two of the trenches are in communication in a corresponding region.

Optionally, a bottom depth of the trench is smaller than bottom depths of the source regions.

Optionally, the planar SiC MOSFET device further includes a dielectric structure, where the dielectric structure is formed in a partial region of the trench, the gate oxide layer covers the inner surface of the trench at a periphery of the dielectric structure, and the gate further buries the dielectric structure therein.

Optionally, a top of the dielectric structure is higher than a top of the gate oxide layer at a periphery of the trench, and the gate conformally covers the dielectric structure to form a protruding portion, or the gate has a flat top.

Optionally, the planar SiC MOSFET device further includes:

Based on the same inventive concept, the present invention further provides a manufacturing method for the planar SiC MOSFET device according to the present invention. The manufacturing method includes:

Optionally, before the top surface of the SiC drift layer in the region of the to-be-formed gate is etched, to form the at least one trench, the well regions of the second conductivity type and the source regions of the first conductivity type are first formed in the top surface of the SiC drift layer, the well regions are formed in a surface layer of the top surface of the SiC drift layer on two sides of the gate, and the source regions are formed in surface layers of the well regions on the two sides of the gate; or

Optionally, the substrate further includes a buffer layer of the first conductivity type and a base of the first conductivity type sequentially stacked on a bottom surface of the SiC drift layer, and the manufacturing method further includes:

Compared with the related art, the technical solutions of the present invention have at least one of the following beneficial effects:

In the following description, numerous specific details are given to facilitate a more thorough understanding of the present invention. However, it is obvious to persons skilled in the art that the present invention can be implemented without one or more of these details. In other examples, to avoid confusion with the present invention, some technical features known in the art are not described It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. Conversely, these embodiments are provided for the purpose of making the disclosure thorough and complete, and conveying the scope of the present invention fully to persons skilled in the art. In the drawings, for the sake of clarity, the sizes and relative sizes of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout the present invention. It should be understood that when an element or layer is referred to as being “on” or “connected to” other elements or layers, it can be directly located on or connected to the other elements or layers, or there may be an intervening element or layer. Conversely, when an element is referred to as being “directly on” or “directly connected to” other elements or layers, no intervening element or layer is present. Although the terms, such as first and second, can be used to describe various elements, components, regions, layers, and/or portions, these elements, components, regions, layers, and/or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, or portion discussed below may be expressed as a second element, component, region, layer, or portion. Terms indicating the spatial relationships, such as “under . . . ”, “below”, “lower”, “above . . . ”, “upper”, “on a top surface”, “on a bottom surface”, “on a front surface”, and “on a back surface”, are used herein for the convenience of description, to describe the relationship between one element or feature and another element or feature shown in the figure. It can be understood that in addition to the orientations shown in the figures, the terms indicating the spatial relationships are also intended to include different orientations of a device in use and operation. For example, if the device in the figure is upside down, then an element or feature described as being “under . . . ”, “below”, “lower”, “on a bottom surface”, or “on a back surface” will be oriented to be “above”, “on the top of”, or “on the front of” another element or feature. The device can be otherwise oriented (rotated by 90 degrees or in other orientations), and the spatial descriptive terms used herein are interpreted accordingly. The terms are used herein merely for purpose of describing specific embodiments and not as a limitation of the present invention. When used herein, the singular forms “a”, “an”, and “the” are also meant to include the plural form, unless otherwise clearly indicated. It should also be understood that the term “include” is used to confirm the existence of the features, steps, operations, elements, and/or components, but do not exclude the existence or addition of one or more other features, steps, operations, elements, components, and/or groups. As used herein, the term “and/or” includes any and all combinations of related listed items.

The technical solutions provided in the present invention are further described below in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention are more clearly according to the following descriptions. It should be noted that the accompanying drawings are all in a very simplified form and are not drawn to accurate scale, but are merely used for convenience and clarity of description of the embodiments of the present invention.

Referring toand, a structure of an existing planar SiC MOSFET device includes a drain, an N++ base, an N+ buffer layer, an N− drift layer, a gate oxide layer, and a gatesequentially stacked from bottom to top, and further includes P wellsformed in the N− drift layer, N+ source regionsand P+ contact regionsthat are formed in the P wells(also referred to as Pbase regions), and metal layers of the sourcesformed on the N− drift layer. The sourcesare in electrical contact with the N+ source regionsand the P+ contact regionsto short-circuit the N+ source regionsand the P+ contact regions.

In the foregoing planar SiC MOSFET device, a channel (not marked) is located in a region in which a bottom of the gateoverlaps the P wells. During forward operation, when a gate voltage is positively biased and greater than a threshold thereof, an inversion layer is formed, the channel is opened, and electrons flow from the sources, through the N+ source regionsand the channel in sequence, to reach a depletion region (also referred to as a JFET region, that is, the N− drift layerlocated below the bottom of the gateand between the two P wells), and flow downward through the N− drift layer, the N+ buffer layer, and the N++ base, to finally reach a metal layer of the drain. When the gateand the sourcesare short-circuited, and the drainis positively biased, the P wellsand the N− drift layerform a reverse-biased depletion region, and since P-type ion doping concentrations of the P wellsare greater than an N-type ion doping concentration of the N− drift layer, the reverse-biased depletion region mainly expands toward the N− drift layerto reach a high breakdown voltage.

However, the foregoing planar SiC MOSFET device has some defects. Specifically, an existing planar SiC MOSFET device is usually manufactured by using a 4H—SiC crystal. A distribution diagram of crystal planes and crystal directions of the 4H—SiC crystal is shown in. Due to influence of a 4H—SiC epitaxial (EPI) crystal direction, the gateof the planar SiC MOSFET device is always located on the () crystal plane of the SiC crystal. However, the () crystal plane has a large number of interface states, and has a channel mobility of only ⅓ of that of the () crystal plane and that of the () crystal plane, as shown in. Therefore, the planar SiC MOSFET device has high channel resistance. In addition, parasitic capacitance of such a structure is also large. The () crystal plane and the () crystal plane are facets perpendicular to the () crystal plane.

In addition, in the related art, there are few wafers that are expitaxially grown on a crystal plane having a high channel mobility, such as the () crystal plane, the () crystal plane, or the () crystal plane, of the SiC crystal. Moreover, even if a wafer can be expitaxially grown on a crystal plane having a high channel mobility, such as the () crystal plane, the () crystal plane, or the () crystal plane, of the SiC crystal, an epitaxial defect directly extends to the entire surface of the wafer, resulting in large power leakage and poor electrical performance of a manufactured device.

Therefore, the present invention provides a novel structural design and manufacturing method for a planar SiC MOSFET device, so that based on that a gate is located on a () crystal plane of a SiC crystal, another crystal plane having a high channel mobility of the SiC crystal, for example, a crystal planes having a high channel mobility, such as a () crystal plane, a () crystal plane, and a () crystal plane, can be further effectively used to reduce channel resistance and improve performance of a device. In addition, parasitic capacitance of the device is further reduced.

Referring toto, an embodiment of the present invention provides a planar SiC MOSFET device. The planar SiC MOSFET device includes a drain, a base, a buffer layer, a SiC drift layer, a gate oxide layer, and a gatesequentially stacked from bottom to top (that is, from a bottom surface to a top surface).

The base, the buffer layer, and the SiC drift layerare all of a first conductivity type (for example, an N-type), and their impurity doping concentrations of the first conductivity type decrease in sequence.

A SiC crystal in the SiC drift layeris a hexagonal crystal such as a 4H—SiC crystal or a 6H—SiC crystal. A top surface (which may also be referred to as a front surface) of the SiC drift layeris a () crystal plane of the SiC crystal. In addition, well regionsof a second conductivity type (for example, a P-type) are formed in a surface layer of the top surface of the SiC drift layeron two sides of the gate, a source regionof the first conductivity type is formed in a surface layer of a top surface of the well regionon each side, and body contact regionsof the second conductivity type are formed in the well regionsat peripheries of the source regions. Impurity doping concentrations of the first conductivity type in the source regionsand impurity doping concentrations of the second conductivity type in the body contact regionsare respectively greater than impurity doping concentrations of the second conductivity type in the well regions.

Sourceare formed on surfaces of the source regionsand the body contact regions, and are electrically connected the body contact regionsand the source regions, to make them have an equal potential. The drainis stacked on a bottom surface of the base(that is, a back surface of the base). The sourcesand the drainmay both be mainly made of metal, and materials thereof may be selected from one of Al, AlCu, or AlSiCu.

In this embodiment, the gate, the source regions, and the well regionsare all arranged as strip-shaped structures parallel to each other. A material of the gatemay include doped polysilicon, and a conductivity type of the gatemay be opposite to that of the SiC drift layer

At least one trenchis arranged in the SiC drift layerbelow a bottom of the gate. The at least one trenchis arranged in a channel current crossing direction (as indicated by a dashed arrow in), and when there are a plurality of trenches, the trenchesare formed spaced apart in the channel current crossing direction (as indicated by the dashed arrow in). Bottoms of all the trenchesare shallower than bottoms of the well regions. Optionally, bottoms of all the trenchesare shallower than bottoms of the source regions. For example, bottom depths (that is, heights from the top surface of the SiC drift layer to bottom surfaces of the trenches) of all the trenchesare less than 1000 Å.

The trenchesmay be in any suitable shape, for example, a cuboid or a trapezoid. Each trenchextends along two sides of the gateto between boundaries of the source regionsand boundaries of the well regions. To be specific, a length w by which the trenchextends in a width direction (namely, a direction AA′ or a direction BB′ in) of the gate is between a distance a between the well regionson the two sides of the gateand a distance b between the source regions, that is, a<w<b.

Crystal planes of two sidewall surfaces Sand Sof each trenchextending in the width direction of the gateare each a crystal plane having a channel mobility higher than that of the () crystal plane in the SiC crystal, for example, a () crystal plane, a () crystal plane, or a () crystal plane of the SiC crystal. That is, the sidewall surfaces Sand Sare parallel to the () crystal plane, the () crystal plane, or the () crystal plane of the SiC crystal in the SiC drift layer. Referring to, both the () crystal plane and the () crystal plane of the SiC crystal are facets perpendicular to the () crystal plane of the SiC crystal, and a channel mobility of the () crystal plane or the () crystal plane is about 3 times that of the () crystal plane. The () crystal plane of the SiC crystal is a crystal plane at an angle of about 55° or 54.74° to a () crystal plane of the SiC crystal. The () crystal plane of the SiC crystal is parallel to the () crystal plane of the SiC crystal.

It should be understood that the two sidewall surfaces Sand Sof each trenchmay be parallel to the width direction AA′ of the gate, or intersect, due to a process error, the width direction AA′ of the gate, however, at an angle limited within an allowable range. In other words, angles between the two sidewall surfaces Sand Sof the trenchand the direction AA′ may not be 90° provided that it is ensured that crystal planes of the sidewall surfaces Sand Sare each a crystal plane having a high channel mobility such as the () crystal plane, the () crystal plane, or the () crystal plane.

Optionally, in other embodiments of the present invention, to reduce parasitic capacitance of the gate, referring to, the planar SiC MOSFET device further includes a dielectric structure. The dielectric structureis formed in a partial region of the trenchand is configured to raise the bottom of the gate. The gate oxide layercovers an inner surface of the trenchat a periphery of the dielectric structureand exposed surfaces of the source regions. The gatefurther buries the dielectric structuretherein. The dielectric structureis made of an insulating dielectric material, and a material thereof is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, a high-K material, a spin-on dielectric material (for example, spin-on phosphosilicate glass, borophosphosilicate glass, or fluorosilicate glass), or a dielectric material having a low dielectric constant. By arranging the foregoing dielectric structure, a distance between the gateand the drainis increased, which is equivalent to directly increasing a distance between two electrodes of gate-drain capacitance (Cgd), so that Cgd, that is, reverse transmission capacitance or Miller capacitance, can be effectively reduced, and application losses can be reduced. For example, a top of the dielectric structureis higher than a top of the gate oxide layerat the periphery of the trench, and the gateconformally covers the dielectric structureand the gate oxide layer, to form a protruding portion (not marked), as shown in. In another example, a top of the dielectric structureis higher than a top of the gate oxide layerat the periphery of the trench. The gatefurther buries the dielectric structuretherein, and the gatehas a flat top, as shown in.

Referring toto, in the foregoing embodiments, the plurality of trenchesformed may be sequentially arranged side by side and spaced apart at an equal distance or different distances in a length direction of the gate. Any two trenchesare not in communication with each other. In this case, the plurality of trenchesare formed spaced apart in the channel current crossing direction. However, the technical solutions of the present invention are not limited thereto. In other embodiments of the present invention, referring to, the plurality of trenchesmay be sequentially arranged side by side and spaced a part in a length direction of the gate, and at least two of the trenchesare in communication with each other in a corresponding region (for example, an end portion or an intermediate segment). The trenchesin communication may be adjacent, or may be further separated by at least one trench

With further reference toto, in the foregoing embodiments, the trenchesformed are each a single-step trench, but the technical solutions of the present invention are not limited thereto. In other embodiments of the present invention, at least one trenchmay be a two-step trench, a three-step trench, or trench with more steps as long as allowed by the overall depth design of the trench. A cross-sectional structure of the trenchpresented as a two-step trench is shown in. Sidewall surfaces including Sand Sof the trenchmay each have two steps. A cross-sectional structure of the trenchpresented as a three-step trench is shown in. Sidewall surfaces including Sand Sof the trenchmay each have three steps.

Based on the same inventive concept, referring to, an embodiment of the present invention further provides a manufacturing method for a planar SiC MOSFET device, so that the planar SiC MOSFET device of the present invention can be manufactured. The manufacturing method specifically includes the following steps:

In step s, referring to (A) in, a baseis provided, and a buffer layerof a first conductivity type and a SiC drift layerare sequentially formed on the basethrough any suitable process such as an epitaxial growth process. A top surface of the SiC drift layeris a () crystal plane. Thicknesses and doping concentrations of the base, the buffer layer, and the SiC drift layerare all designed according to requirements of the device, and are not specifically limited in this embodiment.

In step s, referring to (A) in, first, dry etching is performed on a surface layer of a region in which a channel and a depletion layer are to be formed in the SiC drift layer, to form the at least one trench. The surfaces of the two sidewalls of the trenchextending in the width direction of the to-be-formed gate are each a crystal plane having a channel mobility higher than that of the () crystal plane.

Optionally, a crystal plane of the trenchmay be trimmed through an appropriate process such as wet etching or oxidation followed by wet etching, to form a crystal plane having a high channel mobility such as a () crystal plane, a () crystal plane, or a () crystal plane, or the trenchmay be trimmed from a single-step trench to a two-step trench shown in, a three-step trench shown in, or a trench with more steps.

In an example of this embodiment, referring to (A) in, before step sis performed, that is, before the top surface of the SiC drift layerin the region of the to-be-formed gate is etched, to form the at least one trench, well regionsof a second conductivity type are first formed in the top surface of the SiC drift layerthrough a series of processes such as mask deposition, patterning, and ion implantation, and then, source regionsof the first conductivity type and body contact regionsof the second conductivity type are formed, where the formed trenchextends from the well regionon one side serving as a boundary region of a channel to the well regionon the other side serving as a boundary region of the channel. The source regionsare formed in surface layers of the well regionson the two sides respectively, and there are gaps between the trenchand boundaries of the source regions. To be specific, as shown inand, a length w by which the trenchextends in a width direction (namely, a direction AA′ or a direction BB′ in) of the gate is between a distance a between the well regionson the two sides of the gateand a distance b between the source regions, that is, a<w<b. Further, after the well regions, the source regions, and the body contact regionsare formed, the corresponding mask is removed, and implanted impurities are activated through a high-temperature annealing process. A bottom depth of the trenchis shallower than bottom depths of the source regionsor bottom depths of the well regions.

In another example of this embodiment, referring to (A) in, after step sis performed, well regionsare first formed in the top surface of the SiC drift layeron two sides of the trenchthrough a series of processes such as mask deposition, patterning, and ion implantation, and then, source regionsof the first conductivity type and body contact regionsof the second conductivity type are formed. After the well regions, the source regions, and the body contact regionsare formed, the corresponding mask is removed, and implanted impurities are activated through a high-temperature annealing process. A bottom depth of the trenchis shallower than bottom depths of the source regionsor bottom depths of the well regions. Each trenchextends along two sides of the gateto between boundaries of the source regionsand boundaries of the well regions. To be specific, as shown inand, a length w by which the trenchextends in a width direction (namely, a direction AA′ or a direction BB′ in) of the gate is between a distance a between the well regionson the two sides of the gateand a distance b between the source regions, that is, a<w<b.

In step s, referring to (D) and (E) in, a gate oxide layermay be formed through a thermal oxidation process, a deposition process, or the like. Polysilicon is deposited on the gate oxide layer, and impurities of the second conductivity type are implanted and activated to form a highly-doped polysilicon gate material layer. Then, the polysilicon gate material layer and the gate oxide layerare patterned to form the gateand the gate oxide layercovered by the gate.

In an example of this embodiment, referring to (B) and (C) in, after step sis performed and before step s, a dielectric layer′ is first covered on the trench, the source regions, and the body contact regionsthrough an appropriate process such as deposition or spin coating. The dielectric layer′ may have a flat top surface or an uneven top surface. A top height of the dielectric layer′ protrudes above the top surface of the SiC drift layer. Then, a patterned maskis formed through processes such as photoresist coating, exposure, and development. Further, under a masking effect of the patterned mask, the dielectric layer′ is etched to form the dielectric structurein the trench. The gateformed in step smay conformally cover the dielectric structureand the gate oxide layer. The gatemay have a flat top surface or a convex top surface.

It should be noted that for formation of the source regions, the well regions, and the channels, compared to the related art, protection from an additional ion implanted layer (IMP layer) is not needed for formation of the trench. Therefore, the manufacturing method of this embodiment has simple processes, and is easy to implement.

Further, referring to (E) and (F) in, after step sis performed, a passivation layer (not shown) may be deposited on the gateand a surface of the device exposed by the gate, and the passivation layer is etched to form a surface that exposes the source regionsand the body contact regions. Further, a source metal is grown on the source regionsand the body contact regions, and is annealed to form sources. The sourcesare electrically connected to the source regionsand the body contact regions. Next, a drain metal is deposited on a bottom surface of the base, and is annealed to form a drain.

In conclusion, in the planar SiC MOSFET device and the manufacturing method therefor in the present invention, some shallow trenches are arranged based on that a channel current is still parallel to a () crystal plane of a SiC crystal, to further effectively use a crystal plane having a high channel mobility, for example, a () crystal plane, a () crystal plane, or a () crystal plane, of the SiC crystal, thereby effectively reducing channel resistance of the planar SiC MOSFET device. In addition, source regions, well regions, and a channel are formed without protection from an additional ion implanted layer (IMP layer), leading to simple processes. Besides, a degree by which channel resistance Ron or Rsp is reduced is related to density of trenches, and a planar MOSFET device used below 1700 V has beneficial effects that are more significant. For example, when the solutions of the present invention are applied to a 750 V planar SiC MOSFET device, channel resistance Ron or Rsp may be reduced by 30%.

The foregoing descriptions are merely descriptions of the preferred embodiments of the present invention and do not limit the scope of the present invention in any way. All changes or modifications made by persons of ordinary skill in the art of the present invention according to the foregoing disclosure fall within the protection scope of the technical solutions of the present invention.