Semiconductor Device

This patent application relates to the commonly assigned U.S. patent application Ser. No. 17/526,490, filed Nov. 15, 2021, entitled “SEMICONDUCTOR DEVICE,” which application is hereby incorporated herein by reference in its entirety.

The present disclosure relates to semiconductor devices, for example, semiconductor devices with a high breakthrough voltage, and manufacturing methods therefore.

Semiconductor devices include an edge termination structure to reduce electric field gradients at an edge of the semiconductor device.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

According to some embodiments, a semiconductor device is provided. The semiconductor device comprises a device region, an edge termination region surrounding the device region, a first metal feature in the edge termination region, a first conformal ion diffusion barrier layer over the first metal feature, and a first conformal chemical protection layer over the first conformal ion diffusion barrier layer.

According to some embodiments, a semiconductor device is provided. The semiconductor device comprises a device region, an edge termination region adjacent the device region, a first metal feature in the edge termination region, a first atomic layer deposition layer having a first material composition over the first metal feature, and a second atomic layer deposition layer having a second material composition different than the first material composition over the first atomic layer deposition layer.

According to some embodiments, a method for forming a semiconductor device is provided. The method comprises forming a first conformal layer having a first material composition and a first thickness less than 200 nm over a first metal feature formed in an edge termination region of the semiconductor device. A second conformal layer having a second material composition different than the first material composition and a second thickness less than 200 nm is formed over the first conformal layer. A conformal dielectric layer is formed over the second conformal layer. A polymer layer is formed over the conformal dielectric layer.

According to some embodiments, an apparatus is provided. The apparatus includes means for forming a semiconductor device. The apparatus comprises means for forming a first conformal layer having a first material composition and a first thickness less than 200 nm over a first metal feature formed in an edge termination region of the semiconductor device. The apparatus comprises means for forming a second conformal layer having a second material composition different than the first material composition and a second thickness less than 200 nm over the first conformal layer. The apparatus comprises means for forming a conformal dielectric layer over the second conformal layer. The apparatus comprises means for forming a polymer layer over the conformal dielectric layer.

To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth certain illustrative aspects and implementations. These are indicative of but a few of the various ways in which one or more aspects may be employed. Other aspects, advantages, and novel features of the disclosure will become apparent from the following detailed description when considered in conjunction with the annexed drawings.

The claimed subject matter is now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. It may be evident, however, that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the claimed subject matter.

It is to be understood that the following description of embodiments is not to be taken in a limiting sense. The scope of the present disclosure is not intended to be limited by the embodiments described hereinafter or by the drawings, which are taken to be illustrative only. The drawings are to be regarded as being schematic representations and elements illustrated in the drawings are not necessarily shown to scale. Rather, the various elements are represented such that their function and general purpose become apparent to a person skilled in the art.

All numerical values within the detailed description and the claims herein are modified by “about” or “approximately” the indicated value, and take into account experimental error and variations that would be expected by a person having ordinary skill in the art.

The term “over” and/or “overlying” is not to be construed as meaning only “directly over” and/or “having direct contact with”. Rather, if one element is “over” and/or “overlying” another element (e.g., a region is overlying another region), a further element (e.g., a further region) may be positioned between the two elements (e.g., a further region may be positioned between a first region and a second region if the first region is “over” and/or “overlying” the second region). Further, if a first element is “over” and/or “overlying” a second element, at least some of the first element may be vertically coincident with the second element, such that a vertical line may intersect the first element and the second element.

The semiconductor substrate or body may extend along a main extension plane. The term “horizontal” as used in this specification intends to describe an orientation substantially parallel to said main extension plane. A first or main horizontal side of the semiconductor substrate or body may run substantially parallel to horizontal directions or may have surface sections that enclose an off-axis angle of at most 8° (or at most 6° or at most 4°) with the main extension plane. The first or main horizontal side can be for instance the surface of a wafer or a die. Sometimes, the horizontal direction is also referred to as the lateral direction.

The material of the semiconductor substrate may have hexagonal crystal structure, such as seen in a silicon carbide material, for example. In some embodiments, the material of the semiconductor substrate has a cubic crystal structure not having an off-axis angle, such as seen in a silicon material, for example.

The term “vertical” as used in this specification intends to describe an orientation which is substantially arranged perpendicular to the horizontal direction, (e.g., parallel to the normal direction of the first side of the semiconductor substrate or body or parallel to the normal direction of a surface section of the first side of the semiconductor substrate or body).

The Figures illustrate relative doping dosages by indicating “−” or “+” next to the doping type “n” or “p”. For example, “n−” means a doping dosage which is lower than the doping dosage of an “n”-doping region while an “n+”-doping region has a higher doping dosage than an “n”-doping region. Doping regions of the same relative doping dosage do not necessarily have the same absolute doping dosage. For example, two different “n”-doping regions may have the same or different absolute doping dosages.

In accordance with the present disclosure, a semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device may comprise doped semiconductor material formed in trenches and over a mesa defined between adjacent trenches. The doping profile of the semiconductor material may be varied to affect the forward current and leakage current of the device.

According to some embodiments, a semiconductor device is provided. The semiconductor device comprises a device region, an edge termination region surrounding the device region, a first metal feature in the edge termination region, a first conformal ion diffusion barrier layer over the first metal feature, and a first conformal chemical protection layer over the first conformal ion diffusion barrier layer.

The embodiments described herein may be combined in any way.

illustrate a cross-sectional view and a top view of a semiconductor device, respectively, according to various examples of the present disclosure. In some embodiments, the semiconductor devicecomprises a device regionand an edge termination region. In some embodiments, one or more functional devices (not shown), such as a diode, transistor, or some other device, is formed in the device region. The one or more devices in the device regionmay comprise high voltage devices, having operating voltages greater than 200V, greater than 400V, greater than 600V, greater than 1.2 kV, or even greater than 2 kV. The edge termination regioncomprises an edge termination structurethat serves to reduce electric field gradients at an edgeof the semiconductor device. In some embodiments, the semiconductor devicecomprises a semiconductor bodyin which the one or more functional devices are formed, and contacts,that serve as terminals of the one or more functional devices. Other structures and configurations of the contacts,, are within the scope of the present disclosure.

In some embodiments, the semiconductor bodycomprises crystalline semiconductor material. The semiconductor bodymay comprise silicon, silicon carbide (SiC), and/or other semiconductor compounds. The semiconductor bodymay comprise dopants (e.g., nitrogen (N), phosphorus (P), beryllium (Be), boron (B), aluminum (Al), gallium (Ga) and/or other dopants). Alternatively and/or additionally, the semiconductor bodymay comprise impurities (e.g., hydrogen, fluorine, oxygen and/or other impurities). The semiconductor bodymay comprise a hexagonal phase of silicon carbide, e.g., 4H—SiC, or a cubic phase of silicon. For a hexagonal phase, the <0001> crystal axis may be tilted by an off-axis angle α to a surface normal the first surface. The <11-20> crystal axis may be tilted by the off-axis angle α with respect to the horizontal plane. The <1-100> crystal axis may be orthogonal to the cross-sectional plane. The off-axis angle α may be in a range from 2° to 8°. For example, the off-axis angle α may be 4°.

In some embodiments, the semiconductor bodycomprises a substrate portion and a drift layer (not separately illustrated) formed using an epitaxial growth process using the substrate portion as a growth template. The semiconductor bodymay be a semiconductor material, such as SiC (e.g. having a hexagonal crystal structure), GaN, GaO, diamond, InP, AlP, a ternary group III-V semiconductor, such as AlGaN, InGaN, InGaP, InAlP, or some other suitable material alone or in combination. In some embodiments, the semiconductor bodyhas a band gap of about 2.4 eV to 3.4 eV. In some embodiments, the semiconductor bodyhas a band gap greater than 2 eV (a so-called wide band gap semiconductor). In some embodiments, the semiconductor bodycomprises an n-type impurity, such as at least one of phosphorous, arsenic, or another suitable n-type dopant provided at an n-dosage.

In some embodiments, the edge termination structurecomprises one or more metal featuresand a doped featuredefined in the semiconductor body. In some embodiments, a dielectric layeris positioned between the semiconductor bodyand the metal features. In some embodiments, the metal featurescomprise metal, such as aluminum, copper, or other suitable material. In some embodiments, each metal featuredefines a ring-shaped or framing structure that surrounds the device region. For example, the innermost metal structureA contacts and/or overlaps the contact, thereby framing the contact. In some embodiments, one or more of the metal featurescomprises a ring-shaped plate. The metal featuresmay be continuous, as illustrated in, or the structure of the metal featuresmay be discontinuous, comprised of discrete conductive elements. The number of metal featuresin the edge termination structuremay vary. Other structures and configurations of the metal featureare within the scope of the present disclosure. In some embodiments, the metal featurehas a u-shaped cross-section, a rectangular cross-section, or a cross-section that conforms to the topology of the dielectric layer. For example, the dielectric layer may define one or more openings(shown in phantom) that expose portions of the semiconductor body, and the metal featuremay extend into the opening(s) to contact the semiconductor bodyand the doped feature. In some embodiments, the outermost metal featureis part of a channel stopper structure.

In some embodiments, a high voltage may be applied to the outermost metal featureand decreasing voltages may be applied to metal featurescloser to the device region. For example, a voltage at or near the level of the breakthrough voltage for a device in the device region may be applied to the outermost metal feature, a voltage of OV may applied to the innermost metal featureand intermediate voltages may be applied to the intermediate metal features in a decreasing manner.

In some embodiments, the doped featurecomprises a variation of lateral doping (VLD) structure where the dopant concentration is greatest at the edgeof the edge termination regiondecreases as it approaches the device region. The VLD structure may comprise one or more doped regions in the semiconductor bodywith different spacing, different concentrations, or different sizes to achieve the VLD profile. In some embodiments, the doped featureis counter-doped with respect to the base doping of the semiconductor body. For example, in an embodiment where the semiconductor bodyis n-doped, a portion of the doped featureis p-doped. The size, depth, and arrangement of the doped featuremay vary. The doped featuremay comprise multiple doped regions with different dopant dosages and/or different conductivity types.

In some embodiments, the dielectric layercomprises silicon dioxide, silicon nitride, and/or other suitable materials. In some embodiments, the material(s) for the dielectric layercomprises at least one of Si, O, C, N, or H, such as SiCOH, SiOC, oxygen-doped SiC (ODC), nitrogen-doped SiC (NDC), plasma-enhanced oxide (PEOX), and/or other suitable materials. Organic material, such as polymers, may be used for the dielectric layer. In some embodiments, the dielectric layercomprises one or more layers of a carbon-containing material, organo-silicate glass, a porogen-containing material, and/or other suitable materials. The dielectric layermay be formed by using, for example, at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), plasma enhanced CVD (PECVD), or other suitable techniques. The dielectric layermay comprise one or more layers, at least some of which may have a same material composition. Other structures and/or configurations of the dielectric layerare within the scope of the present disclosure.

are cross-section views of edge termination structures, according to various examples.illustrates a VLD structure comprising metal featuresA,B and doped regionsA,B,C. In some embodiments, the metal featureA frames the contactand contacts the contact. In some embodiments, the metal featureB and the doped regionsA,B,C comprise ring shaped structures. The doped regionsA,B may have opposite conductivity types compared to the semiconductor body. The dopant concentration of the doped regionB decreases as the distance from the contactincreases. The doped regionC and the metal featureB define a channel stopper structure. The doped regionC may have the same conductivity type or an opposite conductivity type as the semiconductor body. In some embodiments, a portionP of the dielectric layerbetween the metal featuresA,B and delineated by phantom lines is removed and the upper surface of the semiconductor bodyis exposed.

illustrates a VLD structure comprising metal featuresA,B,C,D,E,F and doped regionsA,C,D,E,F,G. In some embodiments, the metal featureA frames the contactand contacts the contact. In some embodiments, the doped regionsC,D,E,F are below openings in the dielectric layerand the metal featuresC,D,E,F are in the openings and contact the doped regionsC,D,E,F. In some embodiments, the metal featuresC,D,E,F and the doped regionsA,C,D,E,F,G comprise ring shaped structures. The doped regionsA,C,D,E,F,G may have opposite conductivity types compared to the semiconductor body. The spacing between the doped regionsD,E,F,G may increase as the distance from the contactincreases. In some embodiments, the doped regionC and the metal featureB define a channel stopper structure. The doped regionC may have the same conductivity type or an opposite conductivity type as the semiconductor body.

illustrate aspects with respect to manufacturing the semiconductor deviceaccording to various examples of the present disclosure. The views illustrated inrepresent a portion(see) of the semiconductor deviceincluding a metal feature.

At(illustrated in), a conformal ion diffusion barrier layeris formed over the metal feature. In some embodiments, the conformal ion diffusion barrier layerserves to inhibit migration of the material of the metal feature, oxidized or reduced material of the metal feature, external contaminants, solvents, and/or other materials. In some embodiments, the conformal ion diffusion barrier layeris formed by performing at least one of an atomic layer deposition (ALD) process, a pulsed CVD process, molecular vapor deposition, or some other suitable process. In some embodiments, a thickness of the conformal ion diffusion barrier layeris at least about 1 nm and less than about 200 nm. In some embodiments, the conformal ion diffusion barrier layercomprises aluminum oxide, aluminum nitride, tantalum nitride, or some other suitable material that inhibits migration of the material of the metal feature.

At(illustrated in), a conformal chemical protection layeris formed over the conformal ion diffusion barrier layer. In some embodiments, the conformal chemical protection layerserves to protect the metal featurefrom degradation from external agents, such as water (e.g., from elevated humidity), OH—, HO+, Na+, or some other degrading chemical agent. In some embodiments, the conformal chemical protection layeris formed by performing an atomic layer deposition (ALD) process. In some embodiments, a thickness of the conformal chemical protection layeris at least about 1 nm and less than about 200 nm. In some embodiments, the conformal chemical protection layercomprises silicon dioxide, zirconium dioxide, titanium dioxide, hafnium dioxide, tantalum oxide, boron nitride, or some other suitable material that inhibits chemical degradation of the material of the metal featureand/or the layer(s) underneath.

At(illustrated in), a conformal ion diffusion barrier layeris formed over the conformal chemical protection layer. In some embodiments, the conformal ion diffusion barrier layerserves to inhibit migration of the material of the metal feature. In some embodiments, the conformal ion diffusion barrier layeris a conformal layer formed by performing an atomic layer deposition (ALD) process. In some embodiments, a thickness of the conformal ion diffusion barrier layeris at least about 1 nm and less than about 200 nm. In some embodiments, the conformal ion diffusion barrier layercomprises aluminum oxide, aluminum nitride, tantalum nitride, or some other suitable material that inhibits migration of the material of the metal feature. In some embodiments, the material composition of the conformal ion diffusion barrier layeris the same as the material composition of the conformal ion diffusion barrier layer.

At(illustrated in), a conformal chemical protection layeris formed over the conformal ion diffusion barrier layer. In some embodiments, the conformal chemical protection layerserves to protect the metal featurefrom degradation from external agents, such as water (e.g., from elevated humidity), OH—, HO+, Na+, or some other degrading chemical agent. In some embodiments, the chemical protection layeris a conformal layer formed by performing an atomic layer deposition (ALD) process. In some embodiments, a thickness of the conformal chemical protection layeris at least about 1 nm and less than about 200 nm. In some embodiments, the conformal chemical protection layercomprises silicon dioxide, zirconium dioxide, titanium dioxide, hafnium dioxide, tantalum oxide, boron nitride, or some other suitable material that inhibits chemical degradation of the material of the metal feature. In some embodiments, the material composition of the conformal chemical protection layeris the same as the material composition of the conformal chemical protection layer.

The conformal ion diffusion barrier layers,and the conformal chemical protection layers,define a stackof conformal protective layers,,,. In some embodiments, the number of layers in the stackof conformal protective layers,,,may vary. The thicknesses of the individual conformal protective layers,,,in the stackmay vary. In an embodiment where the stackof conformal protective layers,,,is formed using an ALD process, the conformal protection layers,,,may be referred to as ALD layers,,,. An ALD layer differs structurally from layers formed using a different deposition process. For example, an ALD layer is highly conformal and exhibits an amorphous or crystalline state. Pinholes are suppressed in an ALD layer. The term ALD layer is intended to denote a physical structure as well as a technique for forming the conformal protection layer,,,. For example an ALD layer exhibits few to no seams at corners of the underlying topographical features.

At(illustrated in), a conformal dielectric layeris formed over the stackof conformal protective layers,,,. For ease of illustration, the thicknesses of the conformal protective layers,,,in the stackrelative to the size of the metal featureas illustrated inwas exaggerated. In the illustration of, the stackis illustrated as a single layer. In some embodiments, the conformal dielectric layercomprises silicon nitride and/or other suitable materials. In some embodiments, the conformal dielectric layercomprises multiple layers having the same or different material compositions. For example, the conformal dielectric layermay comprise a layer of silicon dioxide and a layer of silicon nitride. The conformal dielectric layeris a mechanical stabilization layer for the metal featurein the edge termination region.

The conformal dielectric layermay be formed by using, for example, at least one of chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), plasma enhanced CVD (PECVD), or other suitable techniques. The conformal dielectric layermay comprise one or more layers, at least some of which may have a same material composition. Other structures and/or configurations of the conformal dielectric layerare within the scope of the present disclosure.

In some cases, the conformal dielectric layerhas seamsS over portions of the metal feature. For example, the seamsS may be present where an inside cornerA is defined in the metal featureor where an inside cornerB where the metal featureinterfaces with the dielectric layer. A seamS, if present, is a weak point in the protection provided to the metal featureby the conformal dielectric layer. The stackof conformal protective layers,,,provides protection to the metal featureand mitigates protection weaknesses arising from the seamsS.

At(illustrated in), a passivation layeris formed over the conformal dielectric layer. In some embodiments, the passivation layeris a polymer layer such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), an inorganic-organic hybrid material, such as ORMOCER®, or some other suitable passivation layer. The passivation layerserves as a mechanical protection and stress buffer layer in the edge termination region. In some embodiments, a precursor of the passivation layeris first deposited by spin coating and/or other suitable techniques.

At(illustrated in), the passivation layer, the conformal dielectric layer, and the stackof conformal protective layers,,,are patterned to expose the contact. For ease of illustration, the stackof conformal protective layers,,,and the conformal dielectric layerare illustrated as a single layer by the dashed line. In some embodiments, the passivation layeris a photosensitive layer that can be patterned using photolithography techniques, such as coating, exposure, development, and/or other suitable processes. In some embodiments, the patterning of the passivation layerdefines an openingover the contact. In some embodiments, a thermal curing process is performed on the passivation layer. In some embodiments, the patterned passivation layeris used as an etch mask for removing portions of the stackof conformal protective layers,,,and the conformal dielectric layerover the contact. Other structures and/or configurations of the passivation layerare within the scope of the present disclosure. In some embodiments, multiple openings or different configurations of openings may be performed in the passivation layer, the stackof conformal protective layers,,,, and/or the conformal dielectric layer. In some embodiments, such as the edge termination structureillustrated inwhere the portionP of the dielectric layeris removed, the stackof conformal protective layers,,,and the conformal dielectric layerrepresented by the dashed linecontacts the semiconductor body.

illustrates aspects with respect to manufacturing a semiconductor deviceaccording to various examples of the present disclosure. At(illustrated in), a conformal charge shielding layeris formed over the metal feature. In some embodiments, the conformal charge shielding layerserves to counter-balance external charges, which could have an influence on the electrical behavior of the edge termination. In some embodiments, the conformal charge shielding layeris a conformal layer formed by performing an atomic layer deposition (ALD) process. In some embodiments, a thickness of the conformal charge shielding layeris at least about 1 nm and less than about 200 nm. In some embodiments, the conformal charge shielding layercomprises an electrically conductive material, such as titanium dioxide, or some other suitable charge shielding material.

At(illustrated), the acts,,,illustrated an described in reference toare performed to form the conformal protective layers,,,over the conformal charge shielding layer, such that the stackincludes the conformal protective layers,,,,. In some embodiments, the acts,illustrated inare performed to form the conformal dielectric layerand the passivation layer, and to pattern the opening.

is an illustration of an example methodfor manufacturing a semiconductor device. At, a first conformal layer having a first material composition and a first thickness less than 200 nm is formed over a first metal feature formed in an edge termination region of the semiconductor device. At, a second conformal layer having a second material composition different than the first material composition and a second thickness less than 200 nm is formed over the first conformal layer. In some embodiments,andare repeated to form a stack comprising multiple instances of the first conformal layer and the second conformal layer. At, a conformal dielectric layer is formed over the second conformal layer. At, a polymer layer is formed over the conformal dielectric layer.

It may be appreciated that by applying one or more of the techniques described herein, such as by forming a stack of conformal protective layers over a metal feature in an edge termination region, increases the reliability of the device by reducing the likelihood of damage from migration of the metal featureor degradation from external agents. Increasing the reliability tends to increase performance, increase yield, and increase profitability.

According to some embodiments, a semiconductor device is provided. The semiconductor device comprises a device region, an edge termination region surrounding the device region, a first metal feature in the edge termination region, a first conformal ion diffusion barrier layer over the first metal feature, and a first conformal chemical protection layer over the first conformal ion diffusion barrier layer.

According to some embodiments, the semiconductor device comprises a dielectric layer over the first conformal chemical protection layer.

According to some embodiments, the semiconductor device comprises a polymer layer over the dielectric layer.

According to some embodiments, the polymer layer comprises at least one of polyimide, benzocyclobutene, polybenzoxazole, or an inorganic-organic hybrid material.

According to some embodiments, the dielectric layer comprises silicon nitride.

According to some embodiments, the first metal feature comprises a metal ring surrounding the device region.