Apparatus with Post-Processing Data Adjustment Mechanism and Methods for Operating the Same

The present application claims priority to U.S. Provisional Patent Application No. 63/640,477, filed Apr. 30, 2024, the disclosure of which is incorporated herein by reference in its entirety.

The disclosed embodiments relate to devices, and, in particular, to semiconductor memory devices with post-processing data adjustment mechanisms and methods for operating the same.

Memory systems can employ memory devices to store and access information. The memory devices can include volatile memory devices, non-volatile memory devices (e.g., flash memory employing “NAND” technology or logic gates, “NOR” technology or logic gates, or a combination thereof), or a combination device. The memory devices utilize electrical energy, along with corresponding threshold levels or processing/reading voltage levels, to store and access data. However, the stored energy is vulnerable to a variety of factors, such as environmental temperatures, storage duration, unpowered or unoperated duration, or the like. The vulnerabilities can lead to data loss, which can cause performance issues, such as degraded access time, data loss, and/or catastrophic device failure.

As described in greater detail below, the technology disclosed herein relates to an apparatus, such as memory systems, systems with memory devices, related methods, etc., for adjusting data access/management operations to account for voltage shifts and for adapting such adjustments for device initialization, reset, and the like. For example, the apparatus (e.g., a non-volatile memory device within a personal computing device, such as a mobile phone) can estimate charge loss corresponding to the stored data according to a tracked duration since the previous/last power application. Based on the tracked duration, the apparatus can implement a data management mechanism (e.g., a background scan for estimating charge loss) or a portion thereof to manage the stored data.

The data management mechanism can be configured or targeted for deployed operation of the device. In some embodiments, the data management mechanism can include implementing background scans and/or tracking durations since previous/last power-on. Based on the resulting scan and/or tracked duration, the apparatus can assign (e.g., via pointers) groupings of memories (e.g., memory blocks or other related groupings) to bins or other similar loss-estimate groupings. The apparatus can use the bin assignments to adjust one or more data access or data maintenance processes, such as by adjusting read level voltages and/or by triggering data refresh or error recovery. For embodiments of the present technology, the apparatus can further utilize the data management mechanism for managing previously loaded data under targeted conditions, such as first-power-up events, device/system reset events, a power-up event following a long time (as defined by a predetermined thresholding conditions/parameters) without having power, and/or the like.

As an illustrative example, the apparatus can include non-volatile memory devices (e.g., NAND memory devices) within electronic devices, such as smart phones or other consumer products, used to store preloaded software or operating instructions. However, the electronic devices may remain at the retail store or warehouse over an unpredictable duration before users buy and powers up the devices. Accordingly, the memory devices can remain unpowered for potentially long periods, which can negatively affect the preloaded data.

Such potential negative impact on the preloaded data may be worsened by manufacturing steps that precede the unpredictable duration. For example, electronic device manufactures may attach or mount the memory devices to substrates and/or apply protective structures (e.g., underfills) after preloading data. However, such manufacturing processes often require external conditions, such as elevated ambient/device temperatures, that negatively affect (e.g., by causing charge loss or increasing the rate thereof) the integrity of the preloaded data.

Often, the preloaded data can include mission critical data, such as an image of the operating system (OS). In order to prevent or minimize corruption of such preloaded data, the memory device can include a data management or adjustment mechanism configured to account for the affected integrity of the data. In some embodiments, the memory device can have a post-underfill bootup (e.g., initial device power up after completion of manufacturing) that includes the data management mechanism. Such data management mechanism can include leveraging (e.g., enabling or forcing) a Write Booster feature of the Universal Flash Storage (UFS) standard, forcing single-level cell (SLC) writes, or the like before the underfill step. However, such remedial measures often require additional steps, increase resource usages, delays, or other types of costs. For example, leveraging the Write Booster features before the underfill step can violate UFS protocol, thereby requiring the electronic device manufacturer/assembler to take additional steps that account for such violation. Also, forced SLC writes can impact the performance of the initial or immediately subsequent power-on event since the SLC mode significantly reduces the number of write-available blocks.

As described in further detail below, embodiments of the technology described herein can use or adapt the data management mechanism to account for the negative effects of prolonged removal of power, manufacturing conditions, etc. on the preloaded data. For example, the memory device can include an adapted management mechanism that can selectively implement a background scan and a bin assignment of the data management mechanism. The adapted management mechanism can be configured to iteratively (1) scan/sample charge levels or read error rates of memory groupings using the background scan and (2) adjust the bin assignments of the memory groupings according to the scan results. The bin assignments can correspond to (1) an estimated charge loss for the corresponding memory grouping and (2) a processing adjustment, such as a read level offset, that accounts for the estimated charge loss.

In iteratively scanning and adjusting, the adapted management mechanism can be configured to track an adjustment progress that effectively represents a degree or a severity of the charge loss. Some examples of the adjustment progress can include a program-erase count, a number of adjusted groupings, a magnitude of the bin adjustment, or a combination thereof. The adapted management mechanism can be configured to stop the scan and adjustment, thereby deviating from the data management mechanism as intended for the standard operation, and implement a data refresh operation without completing the scan of the intended set of groupings.

As such, the adapted management mechanism can account for potential corruption of preloaded data using standard operating features instead of specifically targeted (e.g., rarely used) features. Moreover, the adapted management mechanism can implement such data management while complying with UFS protocol. Further, the adapted management mechanism can reduce the duration of the data management, such as by recognizing extreme charge loss conditions using the adjustment progress and then implementing the data refresh mechanism without completing the background scan. Additionally, the adapted management mechanism can improve the performance by removing the forced SLC write requirement and allowing other denser writes before the underfill process.

is a block diagram of a computing systemin accordance with an embodiment of the present technology. The computing systemcan include a personal computing device/system, a mobile device (e.g., a mobile/smart phone), a wearable device, or the like. The computing systemcan include a memory system or subsystemcoupled to a host device. The host devicecan include one or more processors that can write data to and/or read data from the memory system. For example, the host devicecan include a central processing unit (CPU) controlling the operation of the computing system.

The memory systemcan include circuitry configured to store data (via, e.g., write operations) and provide access to stored data (via, e.g., read operations). For example, the memory systemcan include a persistent or non-volatile data storage system, such as a NAND-based Flash drive system or the like. In some embodiments, the memory systemcan include a host interface(e.g., buffers, transmitters, receivers, and/or the like) configured to facilitate communications with the host device. For example, the host interfacecan be configured to support one or more host interconnect schemes, such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), Serial AT Attachment (SATA), USF, or the like. The host interfacecan receive commands, addresses, data (e.g., write data), and/or other information from the host device. The host interfacecan also send data (e.g., read data) and/or other information to the host device.

The memory systemcan further include a memory controllerand a memory array. The memory arraycan include memory cells that are configured to store a unit of information. The memory controllercan be configured to control the overall operation of the memory system, including the operations of the memory array.

In some embodiments, the memory arraycan include a set of storage devices or packages. Each of the storage devices can include a set of memory cells that each store data in a charge storage structure. The memory cells can include, for example, floating gate, charge trap, phase change, ferroelectric, magnetoresistive, and/or other suitable storage elements configured to store data persistently or semi-persistently. The memory cells can be one-transistor memory cells that can be programmed to a target state to represent information. For instance, electric charge can be placed on, or removed from, the charge storage structure (e.g., the charge trap or the floating gate) of the memory cell to program the cell to a particular data state. The stored charge on the charge storage structure of the memory cell can indicate a Vt of the cell. For example, a SLC can be programmed to a targeted one of two different data states, which can be represented by the binary units 1 or 0. Also, some flash memory cells can be programmed to a targeted one of more than two data states. Multi-level cells (MLCs) may be programmed to any one of four data states (e.g., represented by the binary 00, 01, 10, 11) to store two bits of data. Similarly, triple-level cells (TLCs) may be programmed to one of eight (i.e., 13) data states to store three bits of data, and quadruple-level cells (QLCs) may be programmed to one of 16 (i.e., 14) data states to store four bits of data.

Such memory cells may be arranged in rows (e.g., each corresponding to a word line) and columns (e.g., each corresponding to a bit line). The arrangements can further correspond to different groupings for the memory cells. For example, each word linecan correspond to one or more memory pages. Also, the memory arraycan include memory blocksthat each include a set of memory pages. In operation, the data can be written or otherwise programmed (e.g., erased) with regards to the various memory regions of the memory array, such as by writing to groups of pages and/or memory blocks. In NAND-based memory, a write operation often includes programming the memory cells in selected memory pages with specific data values (e.g., a string of data bits having a value of either logic 0 or logic 1). An erase operation is similar to a write operation, except that the erase operation re-programs an entire memory block or multiple memory blocks to the same data state (e.g., logic 0).

In some embodiments, the memory systemcan further group the memory cells (e.g., the memory blocks) into data management groupingsfor the purposes of managing the data stored therein. The data management groupingscan correspond to one of many different granularities, containing only whole codewords, whole pages, whole super pages, or whole superblocks, or a combination thereof. For example, the data management groupingscan be based on superblocks that each include a set of data blocks spanning multiple dies/packages that are written in an interleaved fashion. Further the data management groupingscan include block families that each include memory cells that have been programmed within a specific time window. As such, the memory systemcan use the data management groupingsthat include blocks and/or superblocks that are expected to exhibit similar or correlated charge retention states or other data metrics. Details regarding the data management and the use of data management groupingsare further described below.

The memory systemcan include preloaded datain the memory array. The preloaded datacan include data stored on the computing systemprior to deployment/usage thereof. In some embodiments, the preloaded datacan be loaded onto the memory arraybefore one or more manufacturing steps, such as attaching the memory array(e.g., the corresponding packages/dies) to a substrate, applying/flowing underfill, and/or the like. In some applications, the preloaded datacan include instructions or software for operating the computing system. For example, the preloaded datacan correspond to the operating system or an image thereof for the computing system.

While the memory arrayis described with respect to the memory cells, it is understood that the memory arraycan include other components (not shown). For example, the memory arraycan also include other circuit components, such as multiplexers, decoders, buffers, read/write drivers, address registers, data out/data in registers, etc., for accessing and/or programming (e.g., writing) the data and for other functionalities.

As described above, the memory controllercan be configured to control the operations of the memory array. The memory controllercan include a processor, such as a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The processorcan execute instructions encoded in hardware, firmware, and/or software (e.g., instructions stored in controller-embedded memory) to execute various processes, logic flows, and routines for controlling operation of the memory systemand/or the memory array.

Further, the memory controllercan further include an array controllerthat controls or oversees detailed or targeted aspects of operating the memory array. For example, the array controllercan provide a communication interface between the processorand the memory array(e.g., the components therein). The array controllercan function as a multiplexer/demultiplexer, such as for handling transport of data along serial connection to flash devices in the memory array.

In addition to storing and accessing data in the memory array, the memory controller, logic circuits within the memory array, corresponding firmware, or a combination thereof can manage the data stored in the memory array. For example, the memory systemcan include a data management mechanism(e.g., software, firmware, dedicated logic/circuit, or a combination thereof) configured to update one or more operating parameters to account for charge loss. The data management mechanismcan be configured to track charge loss, shift, or other disturbances within the memory array(e.g., according to the data management groupings) and adjust and calibrate the operating parameters. In effect, the data management mechanismcan use the tracked measures and the adjustments to allow the stored data to be accessed with acceptable (e.g., according to a predetermined threshold) Bit Error Rate (BER). Thus, the data management mechanismcan increase the duration between data refresh operations and the refresh rate by allowing acceptable access to otherwise disturbed data/charge levels.

In some embodiments, the data management mechanismcan be configured to implement a background scanthat evaluates the stored charge levels. The memory systemcan implement the background scanaccording to the memory blocksand/or the data management groupings(e.g., block families or superblocks). For example, the memory systemcan read a portion of each superblock using a previously established read level and compute the corresponding error rate. When the error rate exceeds a predetermined threshold, the memory systemcan estimate that a qualifying amount of charge has been lost and adjust the read level as a remedial response.

The management mechanismcan represent the charge loss and the read level adjustment using bin assignments. In other words, the memory systemcan assign each block or data management grouping to a bin that uniquely corresponds to a read offset level. As the stored data gets older and more charge is lost, the memory systemcan sequentially assign the block/grouping to the next bin. The memory systemcan refresh the blocks/groupings in the last bin.

As an illustrative example, newly written blocks can be assigned to Bin 0, which can correspond to a highest read level voltage setting (e.g., highest positive offset for a low base level voltage or zero offset for a high base level voltage). When the result of the background scan(e.g., BER) exceeds a predetermined acceptability threshold, the memory systemcan assign the corresponding block/grouping to the next bin, such as Bin 1, that corresponds to a reduced read level voltage (e.g., second highest positive offset for the low base level scheme or a first negative offset for a high base level scheme). Accordingly, the memory systemcan change the bin assignmentfor the corresponding block(s)/group. In some embodiments, the bin assignmentscan be implemented using pointers that each correspond to a unique grouping and point to the assigned read levels or corresponding offset values.

In addition to the data management mechanism, the memory systemcan include an adapted management mechanismthat leverages the data management mechanismto manage the stored data in targeted scenarios, such as an initial power on event (e.g., after deployment or by a consumer), a first power on event following completion of manufacturing/assembly, a first power on event following a factory reset, a power on event after a prolonged duration without power, and the like. Accordingly, the adapted management mechanismcan be configured to selectively implement iterate through the data management mechanismuntil a predetermined condition is satisfied. Once the predetermined condition is met, the adapted management mechanismcan implement a data refresh mechanismthat rewrites the affected data and restores the stored charges to the targeted levels.

In some embodiments, the memory systemcan trigger or implement the adapted management mechanismaccording to an adapted management trigger. The adapted management triggercan include a tracked data, such as a status parameter, a measure, or the like indicative of targeted conditions, such as the initial power on event, the first power on event following completion of manufacturing/assembly, the first power on event following a factory reset, the power on event after a prolonged duration without power, etc.

For example, the adapted management triggercan include a status bit that is preset to a value at the end of manufacturing, after a factory reset, or the like. Accordingly, the memory systemcan be configured to check the status bit during a power on process and implement the adapted management triggerfor the targeted conditions. After implementing the adapted management trigger, the memory systemcan change the value of the status bit.

Additionally or alternatively, the memory systemcan track the adapted management triggermeasuring or estimating a power removal duration (e.g., following power off, removal of battery, or when battery charge levels fall below a triggering threshold). As examples, the memory systemcan measure or estimate the power removal duration by using internally stored power to operate a counter or by charging a capacitor during runtime and assessing the remaining charges when power becomes available. When the adapted management triggerexceeds a predetermined threshold indicative of a substantial charge loss or a potential data disturbance, the memory systemcan adapted management mechanism. In other embodiments, the memory systemcan implement the adapted management mechanismduring each power up event.

The memory systemcan be configured to use the adapted management mechanismto assess and manage the stored data, such as the preloaded data, that experienced the targeted conditions. For example, the adapted management mechanismcan be configured to manage or maintain the operating system or the image thereof in the memory arrayacross manufacturing conditions (e.g., elevated temperatures during solder reflow or underfill application) and/or prolonged storage duration, such as between completion of manufacturing and first power up event by a consumer following the purchase of the computing system(e.g., fresh out of box or FoB condition).

In managing such data, the adapted management mechanismcan be configured to selectively leverage and implement the data management mechanism. For example, the adapted management mechanismcan implement the background scanand iteratively assess and process data stored in the data management groupings(e.g., super blocks or block families). During the iterative process, the memory system(e.g., the memory controller) can compute and track an adjustment progress. The adjustment progresscan include a quantifiable measure that can be used to estimate targeted conditions (e.g., the FoB condition) that require implementation of the data refresh mechanism. For example, the adjustment progresscan include a program erase count (PEC).

For the selective aspect, the adapted management mechanismcan be configured to stop the background scan(e.g., break the iteration without completing/assessing the remaining groupings) and implement the data refresh mechanismwhen the adjustment progresssatisfies a refresh trigger condition. Continuing with the PEC example, the refresh trigger conditioncan include a predetermined threshold PEC (e.g., 5, 10, 12, 15, or another positive integer). Accordingly, the memory systemcan identify the targeted conditions and take necessary measures to refresh the data without examining the remaining groupings. Moreover, the adapted management mechanismcan allow the preloaded datato be stored without violating UFS requirements and without being limited to SLC writes as described above. Details regarding the adapted management mechanismare further described below.

andillustrate manufacturing steps in accordance with an embodiment of the present technology.can illustrate the storage of the preloaded datainto a storage device(e.g., the memory arrayofor one or more packages/dies therein). For example, the preloaded datacan be stored in the storage deviceafter the storage deviceis attached to or mounted on a substrate(e.g., a system substrate, such as a printed circuit board (PCB)) using interconnects.

can illustrate a manufacturing process following the storage of the preloaded data. For example, the manufacturing process can include applying an underfill(e.g., epoxy or resin-type material) between the storage device, the interconnects, and/or the substrate. Alternatively, the manufacturing process can include reflowing the interconnectsto mount the storage device(having the preloaded datastored thereon) on the substrate.

The manufacturing process can expose the storage deviceand the preloaded datato one or more charge loss conditions, such as elevated temperatures or prolonged durations without power to the storage device(e.g., a non-volatile memory). Accordingly, the charge loss conditionscan alter or deplete the stored charges, thereby potentially or likely changing the preloaded datato loss-affected data(e.g., reduced or shifted charges that may correspond to altered bit values).

To further describe the shift from the preloaded datato the loss-affected datadue to the charge loss conditions,illustrates voltage shifts that may occur in storage devices. For the illustrated example,shows temporal voltage shift (TVS) of a TLC capable of storing three bits of data by programming the memory cell into eight charge states Qthat differ by the amount of charge on the cell's floating gate. The distributions of threshold voltages P(V, Q) are separated with 7 valley margins VM. The cell programmed into k-th charge state (Q) can store a particular combination of 3 bits. For example, the charge state Qcan store the binary combination ‘101’, as depicted. This charge state Qcan be determined during a readout operation by detecting that a control gate voltage Vwithin the valley margin VMis sufficient to open the cell to the source-drain current whereas a control gate voltage within the preceding valley margin VMis not. A memory cell can be configured to store N=1 bits (SLC), N=2 bits (MLC), N=3 bits (TLC), N=4 bits (QLC), and so on, depending on how many distributions can be fit (and interspersed with adequate-size valley margins) within the working range of the control gate voltages. Even thoughdepicts a TLC, the operations described in the present disclosure can be applied to any N-bit memory cells.

Memory cells are typically joined by wordlines (e.g., conducting lines electrically connected to the cells' control gates) and programmed together as memory pages (e.g., 16 KB or 32 KB pages) in one setting, such as by selecting consecutive bitlines connected to the cells' source and drain electrodes. After three programming passes, memory cells corresponding to a wordline of a TLC can store up to three pages: lower page (LP), upper page (UP), and extra page (XP). For example, upon the first programming pass, the cell can be driven to one of the charge states Q, Q, Q, Q(corresponding to LP bit value 1, as shown in) or one of the charge states Q, Q, Q, Q(corresponding to LP bit value 0). Upon the second path, when the UP is programmed into the same wordline, the charge state of the memory cell can be adjusted so that the range of possible locations of the cell's threshold voltage is further narrowed. For example, a cell that is in one of the charge states Q, Q, Q, Q(LP bit value 1) can be driven to just one of the two states Qor Q(corresponding to UP bit value 1) or to one of the two states Qor Q(corresponding to UP bit value 0). Similarly, upon the third programming path, the charge state of the memory cell can be fine-tuned even more. For example, a cell that is in the logic state ‘10’ (i.e., UP bit stores value 1 and LP bit stores value 0) and in one of the charge states Qor Qcan be driven to state Q(corresponding to XP bit value 0) or to state Q(corresponding to XP bit value 1). Conversely, during a read operation, the memory controller can determine that the applied control gate voltage Vwithin the sixth valley margin VMis not insufficient to open the cell to the source-drain electric current whereas the control gate voltage within the seventh valley margin VMis sufficient to open the open the cell. Hence, the memory controllercan determine that the cell is in the charge state Qcorresponding to the logic state ‘010’ (i.e., XP: 0, UP: 1, LP: 0).

The distributions of threshold voltages depicted with solid lines inare distributions that the memory cells have immediately after programming. With the passage of time, as a result of a slow charge loss, the distributions shift (typically, towards lower values of V), as shown by the shifted valleys indicated with dashed lines. As a result, the threshold voltages of various memory cells are shifted by certain values ΔVthat can depend on the time elapsed since programming, environmental conditions (e.g., ambient temperature), and so on. For example, the solid line can correspond to the preloaded dataof, and the dashed lines can correspond to the loss-affected dataof. Moreover, the shift can be caused by the charge loss conditionsof, such as manufacturing processes (e.g., underfill flow) and/or the time between manufacturing and first power on event.

For optimal read operations, the controller can, therefore, adjust the base read levels with the corresponding offsets V→V+ΔV, which are the same (or approximately the same) as the temporal voltage shifts. In one embodiment, the offsets can be determined (or estimated) using the background scanofas the difference between the center of the valley margin (such as the centerof VM) immediately after programming and the center of the same—but shifted-valley margin (such as the new center) at some later instance of time. As depicted in, TVS of different distributions (valleys) and valley margins can differ from each other. In a typical scenario depicted in, TVS is greater for larger charges Q and smaller for lesser charges.

As shown in, the TVS in a memory device is a continuous process. In some embodiments, however, an adequate accuracy of voltage offsets can be achieved using a discrete set of bins and, accordingly, a discrete set of voltage offsets ΔV. In such embodiments, TVS phenomenon can be addressed with setting up a number of discrete bins, e.g., five, eight, twenty, etc., associated with various memory partitions. The bin-related data can be stored in metadata tables(e.g., data construct in the data management mechanismof). The associations of various memory partitions (grouped into families, as described in more detail below) with bins can be stored in family-bin associations(e.g., the bin assignmentsof); the family-bin associations can dynamically change with the passage of time. For example, as the memory cells continue to lose charge with time, the respective memory partitions (grouped into families) can be moved, in a consecutive fashion, from junior bins to more senior bins having larger voltage offsets.

Bin-offset associationscan also be stored in the metadata tables. In some embodiments, the bin-offset associationscan be static whereas the family-bin associationscan be adjusted (based on calibration of the memory partitions) to account for the actual charge loss by the memory cells of the respective partitions. In some embodiments, the family-bin associationscan store logical addresses of the memory partitions, such as LBA of the respective blocks, while associations of LBAs with respective physical block addresses (PBA) can be stored outside the metadata tables, e.g., in memory translations tables stored separately in the local memory or one of the memory devices. In some embodiments, however, family-bin associationscan additionally include LBA-to-PBA translations or store direct PBA-to-bin associations. As schematically depicted with a curved arrow in, the number of bins, the bin-offset associations, the partition bin associations can be based upon calibration of the memory device (or similar types of memory devices, e.g., during design and manufacturing) for maximizing performance and minimizing read errors during read operations.

The threshold voltage offset depends on the time after program (TAP). TAP is the time since a cell has been written and is the primary driver of TVS. TAP may be estimated (e.g., inference from a data state metric), or directly measured (e.g., from a controller clock). A cell, block, page, block family, etc. is young (or, comparatively, younger) if it has a (relatively) small TAP and is old (or, comparatively, older) if it has a (relatively) large TAP. A time slice is a duration between two TAP points during which a measurement may be made (e.g., perform reference calibration from 8 to 12 minutes after program). A time slice may be referenced by its center point (e.g., 10 minutes).

Blocks of the memory device are grouped into block families, such that each block family includes one or more blocks that have been programmed within a specified time window and possibly a specified temperature window. As noted herein above, since the time elapsed after programming and temperature are the main factors affecting the temporal voltage shift, all blocks and/or partitions within a single block family are presumed to exhibit similar distributions of threshold voltages in memory cells, and thus would require the same voltage offsets for read operations.

Block families can be created asynchronously with respect to block programming events. In an illustrative example, the memory controller can create a new block family whenever a specified period of time (e.g., a predetermined number of minutes) has elapsed since creation of the last block family or whenever the reference temperature of memory cells, which is updated at specified time intervals, has changed by more than a specified threshold value since creation of the current block family.

A newly created block family can be associated with bin 0. Then, the memory subsystem controller can periodically perform a calibration process in order to associate each die of every block family with one of the predefines threshold voltage offset bins (bins 0-9 in the illustrative example of), which is in turn associated with the voltage offset to be applied for read operations. The associations of blocks with block families and block families and dies with threshold voltage offset bins can be stored in respective metadata tables maintained by the memory sub-system controller.

The voltage distributions change in time due to the slow charge loss (SCL), which results in drifting values of the threshold voltage levels. In various embodiments of the present disclosure, the temporal voltage shift is selectively tracked for programmed blocks grouped by block families, and appropriate voltage offsets, which are based on block affiliation with a certain block family, are applied to the base read levels in order to perform read operations.

illustrates example adjustments to account for the voltage shifts in accordance with an embodiment of the present technology.shows a set of predefined threshold voltage offset bins (bin 0 to bin 9). As illustrated by, the threshold voltage offset graphcan be subdivided into multiple threshold voltage offset bins, such that each bin corresponds to a predetermined range of threshold voltage offsets. While the illustrative example ofdefines ten bins (0-9), in other implementations, various other numbers of bins can be employed (e.g., 64 bins). Based on a periodically performed management process, the memory controller can associate each die of every block family with a threshold voltage offset bin (via, e.g., the bin assignmentsof), which defines a set of threshold voltage offsets to be applied to the base voltage read level in order to perform read operations.

is a flow diagram illustrating an example methodof operating an apparatus to adjust for the voltage shifts in accordance with an embodiment of the present technology. The methodcan be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the methodcan correspond to the processorofimplementing the data management mechanismof, such as during targeted operation after deployment of the memory systemof. Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated operations can be performed in a different order, while some operations can be performed in parallel. Additionally, one or more operations can be omitted in some embodiments. Thus, not all illustrated operations are required in every embodiment, and other process flows are possible.

At block, the memory systemcan detect a power-up state thereof following a power loss event. Memory blocks may be associated with respective voltage offset bins based on statistical analysis of test data obtained from test devices mimicking the memory device. The test data can include read error data when read operations are performed in similar environmental and operational conditions as the real memory device is likely to experience. As described above, during a power loss event, all previously stored associations of memory blocks with specific voltage offset bins may be lost, and the memory device may need to be recalibrated (e.g., by initiating a re-synchronization operation) to correct and/or avoid read errors. The read errors may be associated with host-initiated read operations or system-initiated scanning operations.

At block, the memory systemcan detect a read error with respect to data residing in a block of the memory device. As described above, the block is initially associated with a current voltage offset bin based on statistical analysis of test data. In certain embodiments, if two or more read errors are detected with respect to multiple blocks, the memory systemcan select a block associated with a voltage offset bin corresponding to a lowest voltage offset value. In other words, priority is given to relatively older bins over relatively younger bins, as the likelihood of TVS being the dominant voltage distortion mechanism in the older bins is much higher than that in the relatively younger bins. Note that detecting the read error can be performed in response to performing a host-initiated read operation or during the background scanof.