Recycled Fine Granularity Counter-Based Ras Chain

This application claims priority to U.S. Provisional Application No. 63/640,704, filed Apr. 30, 2024, which is incorporated by reference herein in its entirety.

The present invention relates generally to the field of memory devices. More specifically, embodiments of the present disclosure relate to timing control circuits in memory devices.

This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are frequently provided as internal memory, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others, may require a source of applied power to maintain its data. Non-volatile memory, by contrast, may retain its stored data even when not externally powered. Non-volatile memory is available in a wide variety of technologies, including flash memory (e.g., NAND and NOR) phase change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), among others.

A memory device may include a number of storage elements, such as memory cells. Memory cells of a binary memory device may, for example, include a charged or discharged capacitor. A charged capacitor of a memory cell may, however, become discharged over time through leakage currents, resulting in the loss of the stored information. Certain features of volatile memory may offer performance advantages, such as faster read or write speeds, while features of non-volatile memory, such as the ability to store data without periodic refreshing, may be advantageous. Some of the memory devices include memory cells that may be accessed by turning on a transistor that couples the memory cell (e.g., the capacitor) with a wordline or a bitline/digit line. Different memory devices may use different architectures for arranging the memory cells. For example, different memory devices may arrange the memory cells in 2-dimensional or 3-dimensional rows and columns. A memory cell may be accessed (e.g., by using access commands such as read/write) based on activating a row and a column of the memory device corresponding to the memory cell. Sense amplifiers (SAs) may be used by a memory device during read operations. Specifically, the read circuitry of the memory device utilizes the sense amplifiers to receive low voltage (e.g., low differential) signals and amplify the small voltage differences to enable the memory device to interpret the data properly. A sense amplifier may include multiple devices (e.g., an isolation gate, a PMOS sense amplifier (PSA), an NMOS sense amplifier (NSA)) formed on an integrated circuit (IC) chip.

Timing control circuits may be used to provide timing signals for controlling the access to the memory cells. For example, a memory device may employ a row address strobe (RAS) chain circuit to generate timing control signals, such as word line (WL) activation timing, sense amplifier (SA) activation timing, precharge timings, etc. Traditionally, delay-based RAS chains are used to provide timing control signals. However, it may be hard to adjust the trim range in a delay-based RAS chain. For example, adjusting the trim range in a delay-based RAS chain may involve adding or removing delay elements, which may affect the area efficiency (AE). In addition, it is difficult to reorder signals in the delay-based RAS chain. Alternatively, a counter-based RAS chain may be used to provide timing control signals. The counter-based RAS chain may have the ability to program event timings and reorder events. However, timing granularity of the current counter-based RAS chain is limited due to various factors, such as the timing granularity of the oscillator used to provide oscillating signal for the counter-based RAS chain, time delay caused by the Gray code counter in the counter-based RAS chain, etc. Accordingly, it is desirable to have a counter-based RAS chain having fine timing granularity and improved area efficiency (AE).

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

A memory device may perform memory operations such as storing data (e.g., write operations) and retrieving stored data (e.g., read operations). For example, a computing system may include various system components including one or multiple memory devices. The system components may communicate data (e.g., data bits) to perform system operations. For example, the system may include one or more processing components, one or more memory devices, among other system components. In different embodiments, the computing system may be disposed on a single electronic chip or multiple electronic chips. Moreover, the computing system may be disposed on a single electronic device or multiple electronic devices positioned in proximity of or remote from each other.

The memory device may include a number of memory banks, controller circuitry, command decoder circuitry, and a clock circuit to provide the clock signal, among other memory components. In some cases, the controller circuitry (hereinafter, controller) may include the command decoder circuitry (hereinafter, command decoder). In alternative or additional cases, the command decoder may include separate circuitry disposed between the controller and the memory banks or any other viable location. The memory device may include control blocks associated with the memory banks. In some cases, the command decoder may provide the access instructions to the control blocks of the memory banks. The memory banks and/or the control blocks of the memory banks may include sense amplifiers (SAs) used for read operations of the memory device.

The current disclosure herein provides a technology and methods related to generating timing control signals for controlling the access to the memory cells of a memory device. The memory device may employ a counter-based RAS chain circuit including multiple Match and Delay blocks to generate timing control signals with fine timing granularities. The Match and Delay blocks may include circuits to enable area savings and improve area efficiency (AE) in the memory device, as well as improve the flexibility for development chips and production parts.

Turning now to the figures,depicts a simplified block diagram illustrating certain features of a memory device(e.g., a memory subsystem of an apparatus). Specifically, the block diagram ofdepicts a functional block diagram illustrating certain functionality of the memory device. In accordance with one embodiment, the memory devicemay include a random access memory (RAM) device, a ferroelectric RAM (FeRAM) device, a dynamic RAM (DRAM) device, a static RAM (SRAM) device (including a double data rate SRAM device), flash memory, and/or a 3D memory array including phase change (PC) memory and/or other chalcogenide-based memory, such as self-selecting memories (SSM). Moreover, each memory cell of such 3D memory array may include a corresponding logic storing device (e.g., a capacitor, a resistor, or the resistance of the chalcogenide material(s)).

The memory devicemay include a number of memory bankseach including one or more memory arrays. Various configurations, organizations, and sizes of the memory bankson the memory devicemay be used based on an application and/or design of the memory devicewithin an electrical system. For example, in different embodiments, the memory banksmay include a different number of rows and/or columns of memory cells. Moreover, the memory banksmay each include a number of pins for communicating with other blocks of the memory device. For example, each memory bankmay receive one data bit per pin at each clock cycle. Furthermore, the memory banksmay be grouped into multiple memory groups (e.g., two memory groups, three memory groups).

The memory devicemay also include a command interfaceand an input/output (I/O) interface. The command interfaceis configured to provide a number of signals received from a processor (e.g., a processor subsystem of an apparatus) or a controller, such as a memory controller. In different embodiments, the memory controller, hereinafter controller, may include one or more processors (e.g., memory processors), one or more programmable logic fabrics, or any other suitable processing components.

In some embodiments, a busmay provide a signal path or a group of signal paths to allow bidirectional communication between the controller, the command interfaceand the I/O interface. For example, the controllermay receive memory access requests from the I/O interface via the command interfaceand the bus. Moreover, the controllermay provide the access commands and/or access instructions for performing memory operations to the command interfacevia the bus.

Similarly, an external busmay provide another signal path or group of signal paths to allow for bidirectional transmission of signals, such as data signals and access commands (e.g., read/write requests), between the I/O interface, the controller, a command decoder, and/or other components. Thus, the controllermay provide various signals (e.g., the access commands, the access instructions, or other signals) to different components of the memory deviceto facilitate the transmission and receipt of data to be written to or read from the memory banks.

That said, the command interfacemay receive different signals from the controller. For example, a reset command may be used to reset the command interface, status registers, state machines and the like, during power-up. Various testing signals may also be provided to the memory device. For example, the controllermay use such testing signals to test connectivity of different components of the memory device. In some embodiments, the command interfacemay also provide an alert signal to the controllerupon detection of an error in the memory device. Moreover, the I/O interfacemay additionally or alternatively be used for providing such alert signals, for example, to other system components electrically connected to the memory device.

The command interfacemay also receive one or more clock signals from an external device (e.g., an external clock signal). Moreover, the command interfacemay include a clock input circuit(CIC) and a command address input circuit(CAIC). The command interfacemay use the clock input circuitand the command address input circuitto receive the input signals, including the access commands, to facilitate communication with the memory banksand other components of the memory device.

Moreover, the clock input circuitmay receive the one or more clock signals (e.g., the external clock signal) and may generate an internal clock signal (CLK) therefrom. In some embodiments, the command interfacemay provide the CLK to the command decoderand an internal clock generator, such as a delay locked loop (DLL)circuit. The DLLmay generate a phase controlled internal clock signal (LCLK) based on the received CLK. For example, the DLLmay provide the LCLK to the I/O interface. Subsequently, the I/O interfacemay use the received LCLK as a clock signal for transmitting the read data using the external bus.

The command interfacemay also provide the internal clock signal CLK to various other memory components. As mentioned above, the command decodermay receive the internal clock signal CLK. In some cases, the command decodermay also receive the access commands via a busand/or through the I/O interfacereceived via the external bus. For example, the command decodermay receive the access commands through the I/O interfacetransmitted by one or more external devices. In some cases, a processor may transmit the access commands.

The command decodermay decode the access commands and/or the memory access requests to provide corresponding access instructions for accessing target memory cells. For instance, the command decodermay provide the access instructions to one or more control blocksassociated with the memory banksvia a bus path. In some cases, the command decodermay provide the access instructions to the control blocksin coordination with the DLLover a bus. For example, the command decodermay coordinate generation of the access instructions in-line (e.g., synchronized) with the CLK and/or LCLK. In some cases, the command decodermay receive the access commands using a rising edge and/or a falling edge of the external clock signal. For example, a processor may transmit the access commands using a memory command protocol, such as a single clock cycle memory command protocol, or a multi-clock cycle memory command protocol. The processor may use a specific memory command protocol based at least in part on the number of pins of the memory deviceor the I/O interface, the number of rows and/or columns of the memory banks, and the number of memory banks. Subsequently, the command decodermay provide the access instructions to the memory banksbased on receiving and decoding the access commands.

Accordingly, the command decodermay provide the access instructions to the memory banksusing one or multiple clock cycles of the CLK via the bus path. The command decodermay also transmit various signals to one or more registersvia, for example, one or more global wiring lines. Moreover, the memory devicemay include other decoders, such as row decoders and column decoders, to facilitate access to the memory banks, as discussed below.

In some embodiments, each memory bankmay include a respective control block. In some cases, each of the control blocksmay also provide row decoding and column decoding capability based on receiving the access instructions. Accordingly, the control blockmay facilitate accessing the memory cells of the respective memory banks. For example, the control blocksmay include circuitry (e.g., logic circuitry) to facilitate accessing the memory cells of the respective memory banksbased on receiving the access instructions. For example, each memory bankand/or corresponding control blockmay include sense amplifiers for read operations of the memory cells of respective memory bank.

In some cases, the control blocksmay receive the access instructions and determine target memory banksassociated with the target memory cells. In specific cases, the command decodermay include the control blocks. Moreover, the control blocksmay also provide timing control and data control functions to facilitate execution of different commands with respect to the respective memory banks.

Furthermore, the command decodermay provide register commands to the one or more registersto facilitate operations of one or more of the memory banks, the control blocks, and the like. For example, one of the one or more registersmay provide instructions to configure various modes of programmable operations and/or configurations of the memory device. The one or more registersmay be included in various memory devices to provide and/or define operations of various components of the memory device. The one or more registersmay communicate with the control blocksvia a bus path

In some embodiments, the one or more registersmay provide configuration information to define operations of the memory device. For example, the one or more registersmay include operation instructions for DRAMs, synchronous DRAMs, FeRAMs, chalcogenide memories (e.g., SSM memory, PC memory), or other types of memories. As discussed above, the one or more registersmay receive various signals from the command decoder, or other components, via the one or more global wiring lines.

In some embodiments, the one or more global wiring linesmay include a common data path, a common address path, a common write command path, and a common read command path. The one or more global wiring linesmay traverse across the memory device, such that each of the one or more registersmay couple to the global wiring lines. The additional registers may involve additional wiring across the memory device (e.g., die), such that the registers are communicatively coupled to the corresponding memory components.

The I/O interfacemay include a number of pins (e.g., 7 pins) to facilitate data communication with external components (e.g., the processing component, such as a processor). Particularly, the I/O interfacemay receive the access commands via the pins. Moreover, data stored on the memory cells of the memory banksmay be transmitted to and/or retrieved from the memory banksover a data path. The data pathmay include a plurality of bi-directional data buses to one or more external devices via the I/O interface. For certain memory devices, such as a DDR5 SDRAM memory device, the I/O signals may be divided into upper and lower bytes; however, such segmentation is not utilized in conjunction with other memory device types.

That said, in different embodiments, the memory devicemay include additional or alternative components. That is, the memory devicemay include additional or alternative components such as power supply circuits (for receiving external VDD and VSS signals), read/write amplifiers (to amplify signals during read/write operations), temperature sensors (for sensing temperatures of the memory device), etc. Accordingly, it should be understood that the block diagram ofis only provided to highlight certain functional features of the memory deviceto aid in the subsequent detailed description.

Referring now to, a memory bankof the memory deviceis illustrated in accordance with various examples of the present disclosure. The memory bankmay include a number of memory cellsthat are programmable to store different memory states. In the depicted embodiment, the memory cellsmay be arranged in multiple rows (e.g., 22 rows, 19 rows, etc.) and multiple columns.

Memory operations, such as reading and writing memory states, may be performed on the memory cellsby activating or selecting the appropriate word linesand digit lines. Activating or selecting a word lineor a digit linemay include applying a voltage to the respective lines. The word linesand the digit linesmay include conductive materials.

For example, word linesand digit linesmay be made of metals (such as copper, aluminum, gold, tungsten, etc.), metal alloys, other conductive materials, or the like. In the depicted embodiment, each row of the memory cellsis connected to a single word line, and each column of the memory cellsis connected to a single digit line. Moreover, each of the memory cellsmay be associated with a row and a column of the memory bank. Accordingly, each of the memory cellsis connected to a respective word lineand a respective digit line.

By applying a voltage to a single word lineand a single digit line, a single memory cellmay be activated (or accessed) at their intersection. Accessing the memory cellmay include performing reading or writing operation on the memory cell. For example, a read operation may include sensing a charge level from the memory cell. The intersection of a word lineand digit linemay be referred to as an address of a respective memory cell. Accordingly, the command decodermay provide the access instructions, including the address bits, to indicate the word linesand digit linescorresponding to the target memory cells.

In some architectures, the memory state storage of the memory cell(e.g., a capacitor) may be electrically isolated from the digit line by a selection component. The word linemay be connected to and may control the selection component. For example, the selection component may be a transistor and the word linemay be connected to the gate of the transistor. Activating the word linemay result in an electrical connection or closed circuit between the capacitor of the memory celland its corresponding digit line. The digit linemay then be activated to either read or write the memory cell.

Accordingly, accessing the memory cellmay be controlled through a respective row decoderand a respective column decoder. As mentioned above, in different embodiments, the controller, the command decoder, and/or the control blocksmay include the row decoderand/or the column decoder. In some examples, the row decodermay receive a row address from the command decoderand may activate the appropriate word linebased on the received row address.

Similarly, a column decodermay receive a column address from the command decoderand may activate the appropriate digit line. The command decodermay provide the row address and the column address based on receiving and decoding the access commands and providing the access instructions. For example, the memory bankmay include multiple word lines, labeled WL_1 through WL_M, and multiple digit lines, labeled DL_1 through DL_N. where M and N depend on the array size. Thus, by activating a word lineand a digit line, e.g., WL_2 and DL_3, the memory cellat their intersection may be accessed.

In any case, upon accessing, the memory cellmay be read, or sensed, by a sense component(e.g., includes one or more sense amplifiers) to determine the stored state of the memory cell. For example, after accessing the memory cell, a ferroelectric capacitor of the memory cellmay discharge a first charge (e.g., a dielectric charge) onto its corresponding digit line. In other examples, after accessing the memory cell, the ferroelectric capacitor of the memory cellmay discharge a second or third charge (e.g., a polarization charge) onto its corresponding digit line. Discharging the ferroelectric capacitor may be based on biasing, or applying a voltage, to the ferroelectric capacitor.

The discharging may induce a change in the voltage of the digit line, which sense componentmay compare to a reference voltage (not shown) in order to determine the stored state of the memory cell. For example, if the digit linehas a higher voltage than the reference voltage, then sense componentmay determine that the stored state in the memory cellis related to a first predefined memory state. In some cases, the first memory state may include a state 1, or may be another value—including other logic values associated with multi-level sensing that enables storing more than two values (e.g., 3 states per cell or 1.5 bits per cell). The sense componentmay include various transistors or amplifiers in order to detect and amplify a difference in the signals, which may be referred to as latching. The detected logic state of the memory cellmay then be output through column decoderas output.

In some examples, detecting and amplifying a difference in the signals may include latching a charge that is sensed in sense component. One example of this charge may include latching a dielectric charge associated with the memory cell. As an example, the sense componentmay sense a dielectric charge associated with the memory cell. The sensed dielectric charge may be latched in a latch within the sense componentor a separate latch that is in electronic communication with the sense component.

is a circuit diagram of an embodiment of a counter-based RAS chainthat may be used to generate timing control signals for the memory device. The counter-based RAS chainmay include an oscillator, which may be enabled by receiving an access command (e.g., Activate/Precharge). The oscillator may be trimmable by using one or more bias voltages (BiasVoltage(s)), which may be generated by using a digital to analog converterbased on a trim signal. The oscillatormay generate a clock oscillating signal (ClkOsc), which may be used to increment a Gray code counter(e.g., every half period

of the signal ClkOscincrement 1 count). In some embodiments, the Gray code countermay be incremented on both the rising edge and the falling edge of the signal ClkOsc. An outputincluding a count value of the Gray code countermay be transmitted into one or more Match and Delay blocks, such as Match and Delay block 0, Match and Delay block 1 . . . Match and Delay block B (B=0,1,2 . . . ). In some embodiments, the Match and Delay blocks may include similar circuits. In some embodiments, the Match and Delay blocks may include different circuits.

illustrates an embodiment of the Match and Delay blockincluding a circuit. The circuitmay include a digital comparatorto receive the outputfrom the Gray code counter. The digital comparatormay compare the count value included in the outputwith a coarse event value, and output a match signalwhen the count value of the outputmatches (e.g., equal to) the coarse event value. The coarse event valuemay be generated by a selection device(e.g., a multiplexer). The selection devicemay select an event setting from a groupof (n+1) event settings (n=1,2 . . . ) based on an event select signal(e.g., EventSel<┌log(n+1)┐−1:0>). For example, the event settings in the groupmay be programmed by (n+1) sets of testmode fuses (e.g., tmfzEventN<m:0>, N=0,1,2 . . . n), and each event setting may have (m+1) (m=0,1,2 . . . ) testmode fuse terms. The upper testmode fuse terms (e.g., EventTrim<m:1+1>, 1=0,1,2 . . . m−1) of the event setting may be used to generate the coarse event valueto indicate the count value of the Gray code counter(e.g., Cnt<m−1−1:0>) for generating the match signal, as illustrated in. That is, the digital comparatormay utilize the upper testmode fuse terms of an event setting to provide a coarse adjustment for the delay of the event and generate the match signal.

The match signalmay be input into a configurable delay chain, which may include one or more delay elements for providing a fine adjustment for the delay of the event, and the adjusted match signalmay be used to generate an event time pulse. The fine adjustment provided by the configurable delay chainmay be trimmable by using the one or more bias voltages, which may allow the oscillatorand the configurable delay chainto track one another. For example, the one or more bias voltagesmay be used to starve current from delay elements in the oscillatorand the configurable delay chain. The lower testmode fuse terms (e.g., EventTrim<1:0>, 1=0,1,2 . . . m−1) may be used to generate a fine event valueto indicate the value of the fine adjustment that may be used to adjust (e.g., delay) the match signalto obtain the event time pulse, as illustrated in. The event time pulsemay be input into a decode circuit(e.g., a demultiplexer). The decode circuitmay associate (e.g., via mapping) the event time pulsewith corresponding event (e.g., eventN, N=0,1,2 . . . n) based on the event select signalgenerated by an event counter. The event time pulsemay be used to set timing control signals for controlling the access to the memory cells of the memory device, as illustrated in. The event time pulse(e.g., the falling edge of the event time pulse) may be used to increment the event counter, which may generate the event select signal(e.g., EventSel<┌log2(n+1)┐−1:0>).

is a timing diagram showing a coarse adjustment of delay provided by the Gray code counterand a fine adjustment of delay provided by a set of nodesof the configurable delay chain. As illustrated in, the count value included in the outputof the Gray code counter(e.g., Cnt<m:0>) may indicate the coarse adjustment time period of the delay for the event. For instance, every increment of the Gray code countercorresponds to a fixed time period (e.g., every half period

of the ClkOsc), accordingly, the count value of the Gray code counter(e.g., Cnt<m:0>), which matches the coarse event value, corresponds to a coarse adjustment time period. Accordingly, the match signalmay be generated during a periodwhen the count value of the Gray code counter(e.g., Cnt<m:0>) matches (e.g., equal to) the coarse event value. As mentioned above, the fine event value(e.g., EventTrim<1:0>, 1=0,1,2 . . . m−1) may indicate the value of the fine adjustment of the configurable delay chainthat may be used to adjust the match signalto obtain the event time pulse. For example, a first nodeof the configurable delay chainmay provide no delay (e.g., the node ConfigDelay2K0.dly[0] illustrated in), which means that all fine adjustment delay elements in the configurable delay chainmay be bypassed. In the embodiment illustrated in, a slight delay is shown between the outputand the match signal, which may be due to delay through the digital comparator. In the embodiment illustrated in, a slight delay is shown between the rising edge T′ of the match signaland the rising edge t of the event time pulsein the node, which may be due to the logic required for performing the selection of the nodes. A second nodeof the configurable delay chainmay provide a fine delay from time t to time t(t=t+fine delay), and a second nodemay provide a fine delay for delaying from time tto time t(t=t+fine delay*2), and so on. Accordingly, the event time pulsemay have a relationship with the coarse event valueand the fine event value, as described in Equation [1]:

where the propagation delay represents the delay caused by the signal propagating in the counter-based RAS chain.

is a timing diagramdepicting example timing of signals (e.g., when m=7, 1=2, n=3) that may be used in the embodiment illustrated inand. In the illustrated embodiment in, an enable signal(e.g., the access command) may be used to enable the oscillator, which may generate the signal ClkOsc. In the illustrated embodiment in, a dynamic match circuit (e.g., for precharge and evaluate) may be used for the digital comparatorto provide further area savings, and a signalmay be used to increment the Gray code counter. The dynamic match signal may provide area savings. The signalmay have a period equal to a half period