Optimization of the Thermal Performance of the 3d Ics Utilizing the Integrated Chip-Size Double-Layer or Multi-Layer Microchannels

This patent application is a continuation of U.S. patent application Ser. No. 18/793,277 entitled “Optimization of the Thermal Performance of the 3D ICs Utilizing the Integrated Chip-size Double-layer or Multi-layer Microchannels,” which was filed on Aug. 2, 2024 and is incorporated herein by reference in its entirety. U.S. patent application Ser. No. 18/793,277 is a continuation of U.S. patent application Ser. No. 18/214,141 entitled “Optimization of the Thermal Performance of the 3D ICs Utilizing the Integrated Chip-size Double-layer or Multi-layer Microchannels,” which was filed on Jun. 26, 2023 and is also incorporated herein by reference in its entirety.

U.S. patent application Ser. No. 18/214,141 claims priority under 35 U.S.C. § 119 to U.S. Provisional Patent Application Ser. No. 63/356,873 entitled “Optimization of the Thermal Performance of the 3D ICs Utilizing the Integrated Chip-size Double-layer or Multi-layer Microchannels,” which was filed on Jun. 29, 2022, and is incorporated herein by reference in its entirety.

Embodiments are related to integrated circuits. Embodiments are also related to three-dimensional (3D) integrated circuits. Embodiments further relate to chip-size integrated double-layer microchannels (DLMC) and multi-layer microchannels (MLMC) used in three-dimensional integrated circuits.

A three-dimensional integrated circuit (3D IC) is a metal-oxide semiconductor-integrated circuit manufactured by stacking silicon wafers or dies and interconnecting them vertically using through-silicon vias (TSVs), such that they behave as a single integrated device to achieve higher performance, lower power consumption, higher functional density, lower transistor packaging density, and a smaller form factor than conventional two-dimensional integrated circuits.

Due to drastically increased integration density of 3D ICs, the task of removing a large amount of dispersed heat from a constrained space is beyond the capability of conventional cooling techniques. The accumulated heat within the device and the hotspot temperature are undesirable for the electrical performance since many electrical parameters are adversely affected by a substantial temperature rise [1-3]. As such effective heat removal from the 3D structure is extremely crucial.

Tavakkoli et al. [4,5] performed a comprehensive thermal analysis of 3D high performance chips using numerical simulations. The effect of parametric changes in the geometrical configuration on the temperature distribution and hotspot temperatures were extensively highlighted, such as size, number and spacing, TSV arrangements (nominal TSVs, uniform TSVs and core-concentrated TSVs). The investigation also sufficiently outlined the impact of the thermophysical properties of the chip and cooling fluid on the flow and heat transfer. Their results presented the key features to be used for establishing optimized design and setup of 3D ICs.

Wang et al. [6] performed an analysis to study the effects of geometric and thermal properties of multi-layer nominal 3D IC chips on the temperature hotspots with different distributions of processors (overlapped cores and staggered cores). They found that the larger the number of the chip layers, the higher the hotspot temperature is; but having a large Reynolds number can help decrease the hotspot temperature. Tavakoli, Salimpour and Vafai [7] investigated the optimization of the heat spreader by inserting the boron arsenide structures, including radial, one level of paring and two-level paring structures. Their results have shown that the two-level paring boron arsenide structures in the heat spreader achieved the superior performance by reducing the hotspot temperature up to 14%.

Tavakoli and Vafai [8] also established a numerical investigation of the optimal distribution of a limited amount of high thermal conductivity material to enhance the heat removal from 3D ICs. Single-layer and double-layer ring shape inserts were studied and optimized for the thermal performance. Their results show that the maximum temperature of the 3D IC is reduced up to 10% for the optimal condition and the size of the heat sink and heat spreader can be 200% smaller compared to the conventional ones.

Lu and Vafai [9] had established that rectangular-shaped heat pipes (RSHP) and disk-shaped heat pipes (DSHP) heat sinks substantially improved the overall thermal performance and reduced the hotspot temperatures by 7 K and 11 K on average, respectively. Furthermore, utilizing these innovative RSHP or DSHP as the heat spreader underneath the RSHP or DSHP heat sink further optimizes the thermal performance by reducing the junction temperatures by 14 K and 16 K on average, respectively. While RSHP and DSHP possess an excellent ability to removing the generated heat, microchannels have also been implemented in the electronic cooling systems to improve the thermal performance [10].

Microchannel heat sinks which were first proposed by Tuckerman and Pease [11], have been investigated and tested as high performance and compact cooling schemes. Both the industry and research communities have investigated the use of high performance microchannels on 3D IC structures. The works from IBM (Armonk, NY) [12-13] illustrate the structure and fabrication process of the integrated single-layer microchannel (SLMC) for 3D ICs. The SLMCs are distributed among device layers. Cooling fluid is delivered to the 3D ICs by employing fluidic through silicon vias (TSVs) and fluidic pipes [13].

With this configuration, Mizunuma et al. [14] developed a fast and accurate thermal-wake model for integrated SLMC 3D IC structure which shows that the integrated SLMC 3D IC reduces the junction temperature significantly. Lu et al. [15] investigated a Multiphysics-based co-simulation technique for the performance of 3D IC structure with integrated SLMC cooling. The integrated SLMC effectively reduced the hotspot temperature and achieved a more uniform temperature distribution. Feng et al. [16] focused on the fast and accurate GPU-based solver development and they showed that integrated SLMC cooling is effective in improving the thermal performance of 3D ICs.

One drawback of SLMC heat sink is the relatively higher streamwise temperature rise. This undesirable temperature gradient produces thermal stresses in IC packages and undermines both the thermal performance and the electrical performance [1-3]. Double-layer or multi-layer microchannels (DLMC or MLMC) can contribute to resolve these problems. DLMC and MLMC were first introduce by Vafai and Zhu [17-19]. DLMC and MLMC are not only excellent in reducing the undesired temperature variation in the streamwise direction thus enhancing the overall cooling capacity compared to the SLMC, but also have lower pressure drop and require less pumping power [17-20].

It should be noted that the counter-flow layout was implemented in Vafai and Zhu's works [17-19]. Following Vafai and Zhu [17-19], Xie et al. [21-24] explored straight and wavy rectangular DLMC with parallel-flow and counter-flow layouts. Their results show that the counter-flow DLMC has superior thermal performance, more uniform temperature rise and lower overall thermal resistance for various scenarios. The other limitation of the integrated SLMC on 3D ICs studied in [12-16] is the significant increased risk of water permanently damaging the 3D IC structure due to the fact that the integrated SLMCs among the device layers requires the fluidic TSVs and pipes to deliver the water into the structure.

To resolve the above problems, this work introduces the integrated chip-size DLMC and MLMC on top and bottom of the 3D IC structures to avoid the fluidic TSVs and pipes within the dies and improve the overall cooling performance. The hotspot temperature reductions and the substantial weight and size reduction of the heat sink equipment in diverse configurations of integrated DLMC and MLMC are thoroughly illustrated. In addition, optimization of the integrated DLMC and MLMC is discussed, including adding a heat sink on top of the structure, the change of the dimensions of the DLMC and investigation of nanofluids within the DLMC.

The following summary is provided to facilitate an understanding of some of the innovative features unique to the disclosed embodiments and is not intended to be a full description. A full appreciation of the various aspects of the embodiments disclosed herein can be gained by taking the entire specification, claims, drawings, and abstract as a whole.

It is, therefore, one aspect of the disclosed embodiments to provide for an improved integrated circuit.

It is another aspect of the disclosed embodiments to provide for an improved 3D integrated circuit.

The aforementioned aspects and other objectives and advantages can now be achieved as described herein.

In an embodiment, a three-dimensional integrated circuit apparatus, can include a three-dimensional integrated circuit comprising a substrate and a plurality of integrated double-layer microchannels (DLMC) and multi-layer microchannels (MLMC) with optimized thermal performance for the three-dimensional integrated circuit, wherein the plurality of integrated double-layer microchannels (DLMC) and multi-layer microchannels (MLMC) are located above the substrate.

In an embodiment, the three-dimensional integrated circuit can comprise a metal-oxide semiconductor-integrated circuit.

In an embodiment, a heat source can be uniformly distributed in each layer of a plurality of layers of the three-dimensional integrated circuit and can be conducted through the plurality of layers down to the substrate and up to a spreader and a heat sink, and eventually to ambient air through forced convective heat transfer above the heat sink and natural convective heat transfer under the substrate.

In an embodiment, a three-dimensional integrated circuit apparatus, can include a three-dimensional integrated circuit including a group of integrated double-layer microchannels (DLMC) and multi-layer microchannels (MLMC) with optimized thermal performance for the three-dimensional integrated circuit.

In an embodiment, chip-size integrated double-layer microchannels (DLMC) and multi-layer microchannels (MLMC) can be used to optimize the thermal performance of three-dimensional integrated circuits (3D ICs). The chip-size integrated DLMC without a heat spreader and a heat sink can reduce the hotspot temperature for a nominal 3D IC structure.

In an embodiment, the size is significantly smaller than copper heat sinks and the weight of the chip-size integrated DLMC can be reduced by 99.9%.

Furthermore, in an embodiment, two chip-size integrated DLMCs can lower the hotspot temperature compared with utilizing just one integrated DLMC on top of the chip structure. Results show that the disclosed multi-layer microchannels (MLMC) have a great effect on reducing the hotspot temperature.

The particular values and configurations discussed in these non-limiting examples can be varied and are cited merely to illustrate one or more embodiments and are not intended to limit the scope thereof.

Subject matter will now be described more fully hereinafter with reference to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific example embodiments. Subject matter may, however, be embodied in a variety of different forms and, therefore, covered or claimed subject matter is intended to be construed as not being limited to any example embodiments set forth herein; example embodiments are provided merely to be illustrative. Likewise, a reasonably broad scope for claimed or covered subject matter is intended. Among other things, for example, subject matter may be embodied as methods, devices, components, or systems. Accordingly, embodiments may, for example, take the form of hardware, software, firmware, or any combination thereof (other than software per se). The following detailed description is, therefore, not intended to be interpreted in a limiting sense.

Throughout the specification and claims, terms may have nuanced meanings suggested or implied in context beyond an explicitly stated meaning. Likewise, phrases such as “in one embodiment” or “in an example embodiment” and variations thereof as utilized herein do not necessarily refer to the same embodiment and the phrase “in another embodiment” or “in another example embodiment” and variations thereof as utilized herein may or may not necessarily refer to a different embodiment. It is intended, for example, that claimed subject matter include combinations of example embodiments in whole or in part. In addition, identical reference numerals utilized herein with respect to the drawings can refer to identical or similar parts or components.

In general, terminology may be understood, at least in part, from usage in context. For example, terms such as “and,” “or,” or “and/or” as used herein may include a variety of meanings that may depend, at least in part, upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B, or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B, or C, here used in the exclusive sense. In addition, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the”, again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

Embodiments relate to a chip-size integrated double-layer microchannels (DLMC) and multi-layer microchannels (MLMC) that can optimize the thermal performance of three-dimensional integrated circuits (3D ICs). In an example embodiment, the chip-size integrated DLMC without a heat spreader and a heat sink reduced the hotspot temperature by almost 15 K for a nominal 3D IC structure. Meanwhile, the size is significantly smaller than the copper heat sinks and the weight of the chip-size integrated DLMC was reduced by 99.9%. Furthermore, two chip-size integrated DLMCs can lower the hotspot temperature by another 6.77 K compared with utilizing just one integrated DLMC on top of the chip structure. The results also show that the multi-layer microchannels (MLMC) have a great effect on reducing the hotspot temperature. We have established that the optimal layout is 4 layers. The hotspot temperature can be reduced by 21 K and 102 times lighter in weight compared to nominal 3D IC structure. The proposed structure and results presented herein can pave the way for major innovations in resolving the thermal issues for the 3D ICs.

illustrates a schematic diagram of the structure of a three-dimensional integrated circuit, in accordance with an embodiment. The three-dimensional integrated circuitcan include a substrateupon which a variety of layers and components may be configured. A layercomprising a TIM layer with C4 bump can be configured above the substrate. A first die layercan be configured on and above the layer. A device layercan be formed above the first die layer. A layercomprising a TIM layer with microbump(s) can be configured above the layer.

A second die layercan be formed above the layer. A device layercan be formed above the second die layer. A layercomprising a TIM layer with microbump(s) can be formed above the device layer. A third die layercan be configured above the layer. A device layercan be formed above layer. A layercomprising a TIM layer with microbump(s) can be formed above the layer. A heat spreadercan be formed above the layer. A heat sinkcan be formed above the heat spreader.

Note that the term “TIM layer with microbump(s)” as utilized herein in the context of an integrated circuit (IC) formed on a substrate, can relate to a Thermal Interface Material (TIM) layer that can be utilized to improve heat dissipation and thermal conductivity between the IC and its surrounding components or heatsink.

When the IC operates, it generates heat, which needs to be efficiently dissipated to prevent overheating and maintain optimal performance. The TIM layer can act as a thermal bridge, facilitating the transfer of heat from the IC to the surrounding components or a heatsink.

Microbumps, on the other hand, are small solder or metal bumps located on the surface of the IC or substrate. They can be used to establish electrical connections between different layers or components within the IC, such as connecting the IC to a package substrate.

By combining a TIM layer with microbumps, the thermal conductivity and electrical connectivity can be simultaneously enhanced. The microbumps provide electrical connections while also creating additional contact points for heat transfer between the IC and the heatsink or other cooling mechanisms. The TIM layer can fill the gaps between the IC and the heatsink, thereby reducing thermal resistance and improving overall heat dissipation. This combination of a TIM layer with microbumps can help to address both thermal management and electrical connectivity requirements in integrated circuits, ensuring efficient heat dissipation while maintaining reliable electrical performance.

illustrates a schematic diagram of a three-dimensional integrated circuitincluding a heat pipeas a heat sink or a heat spreader, in accordance with an embodiment. The three-dimensional integrated circuitshown inis similar to the three-dimensional integrated circuitdepicted in, but with some differences including the heat pipefunctioning a heat sink or a heat spreader, and a layercomprising a flat-shaped heat pipe.

Schematics of nominal 3D IC structures are shown inand. The nominal 3D IC structure includes a substrate, thermal interface material (TIM) with C4 bumps, three layers of dies, device layers and TIM with microbumps, a heat spreader and a heat sink on top. Four core processors, fabricated on each device layer, are the main heat sources.

Table 1 displays the nominal values for different components of the 3D IC structure for nominal cases. The chip-size DLMC structure fabricated with copper [10, 15, 25-31], as illustrated inand, is 10×10 mmand the dimensions for channel width, channel height, fin width, and base and cover thickness are presented in Table 2.

The heat source is uniformly distributed [9] in each layer (e.g., 30 W each layer and 7.5 W each processor). The heat can be conducted through the layers down to the substrate and up to the spreader and the heat sink, and eventually to the ambient air through forced convective heat transfer above the heat sink and natural convective heat transfer under the substrate. Conductive heat transfer through the solid, and isotropic layers of the 3D IC can be governed by

Where

denotes the dimensionless volumetric heat generation in the central processing units and the nondimensionalized temperature and spatial coordinates are set up as:

The convective boundary conditions are

When the IC operates, it generates heat, which needs to be efficiently dissipated to prevent overheating and maintain optimal performance. The TIM layer can act as a thermal bridge, facilitating the transfer of heat from the IC to the surrounding components or a heatsink. Where n* is the normal coordinate and Bi is the dimensionless Biot number. Nominally, the heat flow occurs mainly normal to the device layers. The heat transfer and fluid flow for the DLMC needs to be accounted for. It is governed by the Navier-Stokes equation. The water as the coolant within the microchannel is pumped into the channel at 1 m/s [13]. The dimensionless Navier-Stokes equations in Cartesian coordinates are: