Integrated Circuit Device

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0056769, filed on Apr. 29, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

At least some inventive concepts relate to an integrated circuit device, for example to an integrated circuit device including an inner insulating spacer.

As miniaturization, multifunctionalization, and/or higher performance of electronic products are desired, higher capacity and higher integration of integrated circuit devices are sought after. Accordingly, it may advantageous to efficiently design wiring structures to achieve higher integration while improving functions and/or operating speeds of integrated circuit devices.

At least some inventive concepts relate to an integrated circuit device having improved performance and/or reliability.

According to some example embodiments of inventive concepts, an integrated circuit device may include a fin-type active region on a substrate and extending in a first horizontal direction; a nanosheet stack including a plurality of nanosheets, the nanosheets facing a fin upper surface of the fin-type active region and spaced apart from the fin upper surface; a gate line on the fin-type active region, the gate line least partially surrounding each of the plurality of nanosheets and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including a main gate part and a sub-gate part, the main gate part on an upper surface of the nanosheet stack and the sub-gate part between the main gate part and the fin-type active region; a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the plurality of nanosheets; and an inner insulating spacer between the sub-gate part and the source/drain region, wherein the inner insulating spacer includes a first sub-part in contact with an adjacent nanosheet from among the plurality of nanosheets, and a second sub-part at least partially overlapping with the first sub-part in a vertical direction, and a first sidewall and a second sidewall of the inner insulating spacer each include a part that is recessed toward an inside of the inner insulating spacer, the first sidewall facing the source/drain and the second sidewall opposite to the first sidewall.

According some example embodiments of inventive concepts, d an integrated circuit device may include a fin-type active region on a substrate and extending in a first horizontal direction, a channel region on the fin-type active region; a gate line at least partially surrounding the channel region on the fin-type active region and extending in a second horizontal direction that intersects the first horizontal direction; a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the channel region; and an inner insulating spacer between the gate line and the source/drain region and including a first sidewall, the first sidewall in contact with the source/drain region, wherein the inner insulating spacer includes two first sub-parts vertically apart from each other and a second sub-part vertically between the two first sub-parts, the first sidewall of the inner insulating spacer includes a part recessed toward the inside of the inner insulating spacer, and each of the two first sub-parts includes a part whose vertical thickness decreases as each first sub-part is closer to the gate line.

According to some example embodiments of inventive concepts, an integrated circuit device may include a fin-type active region on a substrate and extending in a first horizontal direction, a nanosheet stack including a plurality of nanosheets, at least one the nanosheets facing a fin upper surface of the fin-type active region and spaced apart from the fin upper surface; a gate line on the fin-type active region, at least partially surrounding each of the plurality of nanosheets, and extending in a second horizontal direction that intersects the first horizontal direction, the gate line including a main gate part on a upper surface of the nanosheet stack and a sub-gate part between the main gate part and the fin-type active region; a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the plurality of nanosheets; and an inner insulating spacer between the sub-gate part and the source/drain region, wherein the inner insulating spacer includes two first sub-parts vertically apart from each other, and a second sub-part vertically between the two first sub-parts, the two first sub-parts comprise silicon nitride, the second sub-part comprises silicon oxide, a first sidewall and second sidewall of the inner insulating spacer each include a part that is recessed toward the inside of the inner insulating spacer, the first sidewall in contact with the source/drain and the second sidewall opposite to the first sidewall, and a distance between interfaces of each of the two first sub-parts with respect to the second sub-part increases as each first sub-part is closer to the gate line.

For the sake of clarity, parts that are not connected with the description will be omitted, and the same elements or equivalents are referred to by the same reference numerals throughout the specification. Further, since, for example, sizes and/or thicknesses of constituent members shown in the accompanying drawings may be arbitrarily given for better understanding and ease of description, example embodiments are not limited to, for example, the illustrated sizes and thicknesses. In the drawings, the thickness of layers, films, panels, regions, etc., for example, are exaggerated for clarity. In the drawings, for better understanding and ease of description, sizes and/or thicknesses of some layers, areas, and the like may be excessively displayed.

It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “below,” “under,” “beneath,” another element or layer, it can be directly over, above, on, below, under, beneath to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly below,” “directly under,” “directly beneath,” another element or layer, there are no intervening elements or layers present.

It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components and/or groups thereof.

In addition, unless explicitly described to the contrary, the word “comprises”, and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

It will be understood that, although the terms first, second, third, fourth, etc. may be used herein to describe various elements, components, regions, layers and/or sections (collectively “elements”), these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element described in this description section may be termed a second element or vice versa in the claim section without departing from the teachings of the disclosure.

Singular expressions may include plural expressions unless the context clearly indicates otherwise. Terms, such as “include” or “has” may be interpreted as adding features, numbers, steps, operations, components, parts, or combinations thereof described in the specification. Singular expressions may include plural expressions unless the context clearly indicates otherwise.

It will be understood that when an element or layer is referred to as being, for example, “on”, “connected to”, “coupled to”, “attached to”, or “in contact with” another element or layer, it can be directly on, connected to, coupled to, attached to, or in contact with the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on”, “directly connected to”, “directly coupled to”, “directly attached to”, or “in direct contact with” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes. When ranges are specified, the range includes all values therebetween such as increments of 0.1%.

It will be understood that elements and/or properties thereof may be recited herein as being “the same” or “equal” as other elements, and it will be further understood that elements and/or properties thereof recited herein as being “identical” to, “the same” as, or “equal” to other elements may be “identical” to, “the same” as, or “equal” to or “substantially identical” to, “substantially the same” as or “substantially equal” to the other elements and/or properties thereof. Elements and/or properties thereof that are “substantially identical” to, “substantially the same” as or “substantially equal” to other elements and/or properties thereof will be understood to include elements and/or properties thereof that are identical to, the same as, or equal to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances. Elements and/or properties thereof that are identical or substantially identical to and/or the same or substantially the same as other elements and/or properties thereof may be structurally the same or substantially the same, functionally the same or substantially the same, and/or compositionally the same or substantially the same.

Hereinafter, at least some example embodiments of inventive concepts will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof are omitted.

is a plan layout diagram of illustrating an integrated circuit deviceaccording to some example embodiments.are cross-sectional views for explaining integrated circuit devicesaccording to some example embodiments.is an enlarged cross-sectional view for explaining an integrated circuit deviceaccording to some example embodiments.is an enlarged cross-sectional view for explaining an integrated circuit deviceaccording to some example embodiments. For example,are cross-sectional views taken along lines X-X, Y-Y, and Y-Yof, respectively.is an enlarged cross-sectional view of a region EXof.is an enlarged cross-sectional view of a region EXof.

An integrated circuit deviceincluding, for example, a field effect transistor having an active area in the shape of a nanowire or nanosheet and a gate-all-around structure including a gate surrounding (for example, at least partially surrounding) the active area is described with reference to.

The integrated circuit devicemay include a substrateand a plurality of fin-type active regions FA protruding from the substrate. A plurality of fin-type active regions FA may extend lengthwise in the first horizontal direction (X direction) on the substrateand may extend parallel to each other.

The substratemay include one or more semiconductors, such as, for example, Si or Ge, or compound semiconductors, such as, for example, SiGe, SiC, GaAs, InAs, InGaAs, or InP, but example embodiments are not limited thereto. The terms “SiGe”, “SiC”, “GaAs”, “InAs”, “InGaAs”, and “InP” used herein refer to materials composed of elements included in each term, and are not chemical formulae representing a stoichiometric relationship. The substratemay include a conductive region, for example, an impurity-doped well or an impurity-doped structure, but example embodiments are not limited thereto.

A device isolation layermay be arranged in a trench limiting (for example, defined or at least partially defined by) a plurality of fin-type active regions FA. The device isolation layermay cover a part or at least a part of the sidewalls of each of the plurality of fin-type active regions FA and may extend from the substratein the vertical direction (Z direction). The device isolation layermay, for example, include a silicon oxide layer, but example embodiments are not limited thereto. The device isolation layermay include a material, for example, having an etch selectivity different from that of the substrate.

As illustrated in, a plurality of gate linesmay be on the plurality of fin-type active regions FA. Each of a plurality of gate linesmay extend lengthwise in a second horizontal direction (Y direction) crossing (for example, intersecting or intersecting with) the first horizontal direction (X direction). In regions where the plurality of fin-type active regions FA and the plurality of gate linescross (for example, overlap with) each other, a plurality of nanosheet stacks NSS may be on a fin upper surface FT of each of the plurality of fin-type active regions FA. Each of the plurality of nanosheet stacks NSS may include at least one nanosheet facing (for example, having at least one surface facing toward) the fin upper surface FT at a position spaced apart from the fin upper surface FT of each of the fin-type active regions FA in the vertical direction (Z direction). In the present specification, the term “nanosheet” may refer to a conductive structure having a cross-section perpendicular or substantially perpendicular to a direction in which a current flows. It should be understood that the nanosheet includes nanowires.

As illustrated in, each of the plurality of nanosheet stacks NSS may include a first nanosheet N, a second nanosheet N, and a third nanosheet Noverlapping or at least partially overlapping with each other in the vertical direction (Z direction) on each of the fin-type active regions FA. The first nanosheet N, the second nanosheet N, and the third nanosheet Nmay have different vertical distances (Z-direction distances) from the fin upper surface FT of each of the fin-type active regions FA. Each of the plurality of gate linesmay surround or at least partially surround the first nanosheet N, the second nanosheet N, and the third nanosheet Nincluded in the nanosheet stack NSS and overlapping with each other in the vertical direction (Z direction).

Althoughillustrates a case in which a planar shape of the nanosheet stack NSS is approximately rectangular, example embodiments are not limited thereto. The nanosheet stacks NSS may have various planar or substantially planar shapes according to a planar or substantially planar shape of each of the fin-type active regions FA and/or gate lines. In some example embodiments, each of a plurality of nanosheet stacks NSS and each of a plurality of gate linesare on a fin-type active region FA, and each of a plurality of nanosheet stacks NSS is, for example, arranged in a line in a first horizontal direction (X direction) on a fin-type active region FA. However, the number of nanosheet stacks NSS and the number of gate linesplaced on one fin-type active regions FA are not particularly limited.

Each of the first nanosheet N, the second nanosheet N, and the third nanosheet Nincluded in the nanosheet stack NSS may function or be configured to function as a channel region. According to some example embodiments, each of the first nanosheet N, the second nanosheet N, and the third nanosheet Nmay have a thickness selected from a range of, for example, about 4 nm to about 6 nm, but is not limited thereto. Here, the thickness of each of the first nanosheet N, the second nanosheet N, and the third nanosheet Nmeans a magnitude in the vertical direction (Z direction). According to some example embodiments, the first nanosheet N, the second nanosheet N, and the third nanosheet Nmay have the same or substantially the same thickness in the vertical direction (Z direction). According to some example embodiments, at least some of the first nanosheet N, the second nanosheet N, and the third nanosheet Nmay have different or substantially different thicknesses in the vertical direction (Z direction). According to some example embodiments, each of the first nanosheet N, the second nanosheet N, and the third nanosheet Nincluded in the nanosheet stacks NSS may include, for example, a Si layer, a SiGe layer, or a combination thereof, but example embodiments are not limited thereto.

As illustrated in, the first nanosheet N, the second nanosheet N, and the third nanosheet Nincluded in one nanosheet stack NSS may have the same or similar sizes in the first horizontal direction (X direction). In some example embodiments, unlike illustrated in, at least some of the first nanosheet N, the second nanosheet N, and the third nanosheet Nincluded in one nanosheet stack NSS may have different sizes in the first horizontal direction (X direction). In, a case where each of the plurality of nanosheet stacks NSS includes three nanosheets has been illustrated, but example embodiments are not limited to those illustrated. For example, the nanosheet stack NSS may include, for example, at least one nanosheet, and the number of nanosheets constituting the nanosheet stack NSS is not particularly limited.

As illustrated in, the plurality of gate linesmay include a main gate partM and a plurality of sub-gate partsS, respectively. The main gate partM may extend lengthwise in a second horizontal direction (Y direction) and cover or at least partially cover the upper surface of the nanosheet stack NSS. The plurality of sub-gate partsS may be connected (for example, integrally connected) to the main gate partM, and each of the plurality of sub-gate partsS may be respectively arranged between the first nanosheet Nand the second nanosheet N, between the second nanosheet Nand the third nanosheet N, and between the first nanosheet Nand each of the fin-type active regions FA. In the vertical direction (Z direction), a thickness of each of the plurality of sub-gate partsS may be less than a thickness of the main gate partM.

Each of the plurality of gate linesmay include a metal, for example, a metal nitride, a metal carbide, and/or a combination thereof, but example embodiments are not limited thereto. The metal may be selected from, for example, Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from, for example, TiN and TaN. The metal carbide may be, for example, TiAlC. However, the material(s) constituting the plurality of gate linesis not limited to the above examples.

As illustrated in, a plurality of first recesses (or recessed areas) Rmay be formed on (for example, defined or at least partially defined by) the fin-type active regions FA, respectively. A vertical level of the lowest surface of each of the plurality of first recesses Rmay be lower than a vertical level of the fin upper surface FT of each of the fin-type active regions FA.

As illustrated in, a plurality of source/drain regionsmay be arranged in the plurality of first recesses R, respectively. Each of the plurality of source/drain regionsmay be arranged at a position adjacent to at least one gate lineselected from among the plurality of gate lines. The plurality of source/drain regionsmay have surfaces being, for example, in contact (for example, direct contact) with the first nanosheet N, the second nanosheet N, and/or the third nanosheet Nincluded in the adjacent nanosheet stack NSS, respectively. The plurality of source/drain regionsmay be, for example in contact (for example, direct contact) with the first nanosheet N, the second nanosheet N, and/or the third nanosheet Nincluded in the adjacent nanosheet stack NSS, respectively. However, example embodiments are not limited thereto.

As illustrated in, the source/drain regionsmay include a plurality of protrusions P protruding toward the plurality of sub-gate partsS, respectively. The plurality of protrusions P may be arranged within a plurality of second recesses (or recessed areas) R, respectively. The plurality of protrusions P may overlap or at least partially overlap with the plurality of sub-gate partsS in the first horizontal direction (X-direction), respectively. The plurality of protrusions P may respectively overlap or at least partially overlap with the first nanosheet N, the second nanosheet N, and the third nanosheet Nincluded in the nanosheet stack NSS in the vertical direction (Z direction). The plurality of protrusions P may be respectively arranged between the first nanosheet Nand the second nanosheet N, between the second nanosheet Nand the third nanosheet Nincluded in the nanosheet stack NSS, and between the first nanosheet Nand the fin-type active regions FA.

A gate dielectric layermay be arranged between the nanosheet stack NSS and the gate line. According to some example embodiments, the gate dielectric layermay have, for example, a stacked structure of or including an interface dielectric layer and a high dielectric layer. The interface dielectric layer may include, for example, a low dielectric material layer having a dielectric constant of about 9 or less, for example, a silicon oxide layer, a silicon oxynitride layer, or a combination thereof, but example embodiments are not limited thereto. According to some example embodiments, the interface dielectric layer may be omitted. The high dielectric layer may be made of, for example, a material having a higher dielectric constant than that of a silicon oxide layer. For example, the high dielectric layer may have a dielectric constant of about 10 to about 25, but example embodiments are not limited thereto. The high dielectric layer may be made of hafnium oxide, but is not limited thereto.

For example, the gate dielectric layermay include hafnium oxide. For example, the gate dielectric layermay include a material different from those of a first sub-part_and a second sub-part_of the inner insulating spacer.

As illustrated inandCan upper surface of each of the gate dielectric layerand the gate linemay be covered or at least partially covered with a capping insulating pattern. The capping insulating patternmay include, for example, a silicon nitride layer, but example embodiments are not limited thereto.

Both sidewalls of each of the gate lineand the capping insulating patternmay be covered or at least partially covered with an outer insulating spacer. The outer insulating spacermay cover or at least partially cover one or both sidewalls of the main gate partM on the upper surface of each of the plurality of nanosheet stacks NSS. The outer insulating spacermay be, for example, spaced apart from the gate linewith the gate dielectric layertherebetween.

As illustrated in, an inner insulating spacermay be arranged between each of the plurality of sub-gate partsS and one corresponding source/drain region. For example, the inner insulating spacermay be arranged between the protrusion P of the source/drain regionand each of the plurality of sub-gate partsS. For example, the inner insulating spacermay be spaced apart from the sub-gate partS in the first horizontal direction (X direction) with the gate dielectric layertherebetween. Hereinafter, the inner insulating spacerwill be described in detail.

Referring to, the inner insulating spacermay be arranged between the source/drain regionand the sub-gate partS in the first horizontal direction (X-direction). For example, the inner insulating spacermay include a first sidewall_Sfacing the source/drain regionand a second sidewall_Sfacing the sub-gate partS. The first side wall_Sand the second side wall_Smay be opposite to each other in the first horizontal direction (X direction).

In some example embodiments, the first sidewall_Smay contact (for example, directly contact) the source/drain region. For example, the first sidewall_Smay contact (for example, directly contact) the protrusion P of the source/drain region. As described above, as the protrusion P protrudes toward the sub-gate partS, the first sidewall_Scontacting the protrusion P may be recessed toward the inside of the inner insulating spacer(for example, recessed inwardly). For example, the first side wall_Smay include a part recessed toward the inside of the inner insulating spacer.

In some example embodiments, the second sidewall_Smay be in contact (for example, direct contact) with the gate dielectric layer. The second sidewall_Smay be recessed toward the inside of the inner insulating spacer. For example, the second side wall_Smay include a part recessed toward the inside of the inner insulating spacer(for example, recessed inwardly). For example, a part of the second side wall_Sthat is recessed toward the inside of the inner insulating spacermay be a part of the second sub-part_. For example, apart of the second sidewall_Sthat is recessed toward the inside of the inner insulating spacermay be a sidewall of the second sub-part_toward (for example, facing) the sub-gate partS. From a cross-sectional perspective, the sidewall facing the sub-gate partS of the second sub-part_may not include a part that is coplanar with the sidewall of the first sub-part_facing the sub-gate partS.

In some example embodiments, the width of the inner insulating spacerin the first horizontal direction (X direction) may not be constant, as the first and second sidewalls_Sand_Sof the inner insulating spacerinclude parts recessed toward the inside of the inner insulating spacer, respectively. For example, the width of the inner insulating spacerin width in the first horizontal direction (X direction) may decrease and then increase in (for example, when moving in) the vertical direction (Z direction). For example, the inner insulating spacermay include a part the width in the first horizontal direction (X direction) of which decreases and then increases in (for example, when moving in) the vertical direction (Z direction).

In some example embodiments, as the second sidewall_Sof the inner insulating spacerfacing the sub-gate partS is recessed toward the inside of the inner insulating spacer, the sub-gate partS may have a convex shape toward (for example, with respect to) the inner insulating spacer. Accordingly, the width of the sub-gate partS in the first horizontal direction (X direction) may not be constant in (for example, when moving in) the vertical direction (Z direction). For example, the width of the sub-gate partS in the first horizontal direction (X direction) may increase and then decrease in (for example, when moving in) the vertical direction (Z direction). For example, the sub-gate partS may include a part the width in the first horizontal direction (X direction) of which increases and then decreases in (for example, when moving in) the vertical direction (Z direction) (for example, according to vertical level).

In some example embodiments, the inner insulating spacermay include the first sub-part_and the second sub-partarranged in the vertical direction (Z direction) (for example, overlap or at least partially overlap with each other in the vertical direction). For example, the inner insulating spacermay include the first sub-partthat contacts (for example, directly contacts) an adjacent nanosheet among the plurality of nanosheets N, N, and N. For example, the inner insulating spacermay include two first sub-parts_contacting the adjacent second nanosheet Nand the third nanosheet N, respectively, among the plurality of nanosheets N, N, and N. The two first sub-parts_of the inner insulating spacermay overlap or at least partially overlap with each other in the vertical direction (Z direction).

The second sub-part_of the inner insulating spacermay be arranged between the two first sub-parts_. For example, the second sub-part_may be arranged between the two first sub-parts_in the vertical direction (Z direction). The second sub-part_may overlap or at least partially overlap with the two first sub-parts_in the vertical direction (Z direction).

In some example embodiments, the second sub-partmay not directly contact adjacent nanosheets among the plurality of nanosheets N, N, and N. For example, the second sub-part_may not directly contact the adjacent second nanosheet Nand the adjacent third nanosheet Namong the plurality of nanosheets N, N, and N. For example, the second sub-partmay be spaced apart from the second nanosheet Nwith the first sub-part_therebetween. For example, the second sub-part_may be spaced apart from the third nanosheet Nwith the first sub-part_therebetween, but example embodiments are not limited thereto.

The first sub-part_and the second sub-part_may each include, for example, one or more insulating materials. The first sub-part_and the second sub-partmay each include different insulating materials. For example, the first sub-part_may include silicon nitride, and the second sub-partmay include silicon oxide. For example, the first sub-part_may include polysilicon, and the second sub-part_may include oxide. However, example embodiments are not limited thereto.

In some example embodiments, referring also to, the first sub-partmay include a first part_Sthat is part of the first sidewall_S. The second sub-part_may include a second part_Sthat is part of the first sidewall_S. In other words, two first parts_Sand one second part_Smay be understood as constituting or at least partially constituting the first sidewall_S.

The first part_Smay include a part recessed toward the inside of the first sub-part_. The second part_Smay include a part recessed toward the inside of the second sub-part_.

In some example embodiments, as illustrated in, interfaces_between the first sub-part_and the second sub-part_may not be parallel to interfaces between the inner insulating spacerand the adjacent nanosheets among the plurality of nanosheets N, N, and N, but example embodiments are not limited thereto.

Accordingly, the vertical thickness of the first sub-partmay not be constant. For example, the vertical thickness of the first sub-partmay decrease toward (for example, when horizontally moving towards) the sub-gate partS. For example, the first sub-part_may include a part the vertical thickness of which decreases toward (for example, when moving towards or as the first sub-partis closer to) the sub-gate partS.