Microelectronic Devices Including Contact Structures and Interconnect Structures, and Related Methods

This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application Ser. No. 63/641,300, filed May 1, 2024, the disclosure of which is hereby incorporated herein in its entirety by this reference.

Embodiments disclosed herein relate to microelectronic devices and microelectronic device fabrication. More particularly, embodiments of the disclosure relate to microelectronic devices including a low-resistivity and increased electrical performance contact structure having little or no intervening material between conductive materials of interconnect structures and conductive contact materials of the contact structures, and to related methods.

Memory devices provide data storage for electronic systems. A Flash memory device is one of various memory device types and has numerous uses in modern computers and other electrical devices. A conventional Flash memory device includes a memory array that has a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In a NAND architecture type of Flash memory, memory cells arranged in a column are coupled in series, and a first memory cell of the column is coupled to a data line (e.g., a bit line). In a three-dimensional NAND (3D NAND) memory device, a type of vertical memory device, not only are the memory cells arranged in row and column fashion in a horizontal array, but tiers of the horizontal arrays are stacked (e.g., vertically stacked) over one another to provide a three-dimensional array of the memory cells. The tiers include alternating conductive materials with insulating (e.g., dielectric) materials. The conductive materials function as control gates for, e.g., access lines (e.g., word lines) of the memory cells. Vertical structures (e.g., pillars including channel materials) extend along the vertical string of the memory cells. A drain end of a string is adjacent to one of the top and bottom of the vertical structure (e.g., pillar), while a source end of the string is adjacent to the other of the top and bottom of the pillar. The drain end is operably connected to a bit line, while the source end is operably connected to a source line. 3D NAND memory devices also include electrical connections between the access lines and other conductive structures of the device so that the memory cells of the vertical strings can be selected for writing, reading, and erasing operations. String drivers drive the access line voltages to write to or read from the memory cells of the vertical string. 3D NAND memory devices may also include multiple decks, one or more decks including one or more memory devices, which may overly a complementary metal-oxide semiconductor (CMOS) region, such as a CMOS under array (CUA) region.

As memory density increases in the 3D NAND memory devices, interconnect structures may be fabricated to minimize signal delay and to optimize packing density. Increased aspect ratios of interconnects (e.g., the length of the interconnect versus the width of the interconnect opening) also occurs. The reliability and performance of integrated circuits may be affected by the quality of the interconnect structures, their contacts, and amounts of resistance between them. However, as the aspect ratios of interconnects increases, possibilities for misalignment, voids, and reduced conductive connectivity also increases.

A microelectronic device (e.g., an apparatus, an electronic device, a portion of an electronic device, a semiconductor device, a memory device, etc.) is disclosed that includes a microelectronic device structure having an interconnect structure that exhibits a reduced electrical resistance relative to a contact structure of the microelectronic device structure. The materials of the interconnect structure are formed within an interconnect opening and adjacent to a dielectric liner and include a conductive fill material and an interconnect liner. As a thickness of the interconnect liner relative to a critical dimension (CD) of the interconnect opening increases, a probability of increased electrical interference in the microelectronic device increases. In other words, as the thickness of the interconnect liner increases relative to a volume of the conductive fill material in the interconnect opening, electrical interference in the microelectronic device increases. To offset increasing electrical interference, electrical resistivities of materials of the interconnect structure relative to materials of the contact structure are reduced. For example, the interconnect structure may be formed in an array region of the microelectronic device structure and comprises two or more materials, such as a material of the interconnect liner having a relatively higher electrical resistivity than a material of the conductive fill material of the interconnect structure. The contact structure may be formed in a source material of the microelectronic device structure and comprises two or more materials, such as a dielectric film material having a higher electrical resistivity than a metal material of the contact structure. To improve electrical performance, forming the interconnect structure and the contact structure of the microelectronic device structure includes removing a portion of the first interconnect material (e.g., the liner, or the higher electrical resistivity material) from intervening between the interconnect metal material (e.g., the fill, or the lower electrical resistivity material) and the metal contact material (i.e., lower electrical resistivity material) of the contact structure.

In some embodiments, a bottom portion of an interconnect liner may be selectively removed to expose the metal contact material of the contact structure, such that when the metal fill material of the interconnect structure is deposited, a portion directly contacts the metal contact material of the contact structure. In other embodiments, an amount of interconnect liner directly contacting the metal contact material of the contact structure is reduced (i.e., relative to conventional contact structures), such that an overall electrical resistivity relative to the contact structure is reduced. Reducing overall electrical resistivity increases the memory array performance (e.g., tWR—recovery write time).

The following description provides specific details, such as material types, material thicknesses, and process conditions in order to provide a thorough description of embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without employing these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques employed in the semiconductor industry. In addition, the description provided herein does not form a complete description of a microelectronic device or a complete process flow for manufacturing the microelectronic device and the structures described below do not form a complete microelectronic device. Only those process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts to form a complete microelectronic device may be performed by conventional techniques.

Drawings presented herein are for illustrative purposes only and are not meant to be actual views of any particular material, component, structure, microelectronic device, or microelectronic system. Variations from the shapes depicted in the drawings as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or nonlinear features, and a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims. The drawings are not necessarily to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, the singular forms of the terms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, the terms “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, the term “array region” means and includes a region of a microelectronic device including memory cells of a memory array. The array region of the microelectronic device includes active circuitry.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term “configured” refers to a size, shape, material composition, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a pre-determined way.

As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct ohmic connection or through an indirect connection (e.g., by way of another structure).

As used herein, the term “microelectronic device” includes, without limitation, an electronic device, such as a memory device, as well as a semiconductor device which may or may not incorporate memory, such as a logic device, a processor device, or a radiofrequency (RF) device. Further, a microelectronic device may incorporate memory in addition to other functions such as, for example, a so-called “system on a chip” (SoC) including a processor and memory, or a microelectronic device including logic and memory. The microelectronic device includes tiers of alternating conductive materials and dielectric materials.

As used herein, the term “microelectronic device structure” means and includes a precursor structure to the microelectronic device.

As used herein, the term “multi-deck assembly” means and includes one or more stacks connected to at least another microelectronic device structure. The at least another stack or the at least another microelectronic device structure may be integrated to form a memory device, or may comprise a portion of the memory device, such as a CMOS device including control logic or circuitry.

As used herein, the term “non-array region” means and includes a region of the microelectronic device proximal to the array region.

As used herein, reference to an element as being “on” or “over” another element means and includes the element being directly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to), underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to), underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” or “directly adjacent to” another element, no intervening elements are present.

As used herein, the term “selectively etchable” means and includes a material that exhibits a greater etch rate responsive to exposure to a given etch chemistry and/or etch conditions relative to another material exposed to the same etch chemistry and/or etch conditions. For example, the material may exhibit an etch rate that is at least about five times greater than the etch rate of another material, such as an etch rate of about ten times greater, about twenty times greater, or about forty times greater than the etch rate of the another material. Etch chemistries and etch conditions for selectively etching a desired material may be selected by a person of ordinary skill in the art.

As used herein, the term “selectively removable” means and includes a material that exhibits a greater removal rate responsive to exposure to a removal chemistry and/or removal conditions, collectively referred to herein as process conditions, relative to another material exposed to the same removal chemistry and/or removal conditions. A material that is selectively removable relative to another material is substantially completely removable without removing substantially any of the another material.

As used herein, the term “stack” means and includes multiple (e.g., two or more) tiers of alternating nitride materials and dielectric materials (e.g., relative to a microelectronic device structure) or alternating conductive materials and dielectric materials (e.g., relative to a microelectronic device).

As used herein, the term “step” means and includes an offset between sidewalls of vertically adjacent materials. For instance, the sidewalls of one of the materials of the vertically adjacent materials are not substantially aligned with the sidewalls of the other material.

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, or even at least 99.9% met.

As used herein, the term “substrate” means and includes a material (e.g., a base material) or construction upon which additional materials are formed. The substrate may be a microelectronic substrate, a semiconductor substrate, a base semiconductor layer on a supporting structure, an electrode, an electronic substrate having one or more materials, layers, structures, or regions formed thereon, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. The materials on the microelectronic substrate or semiconductor substrate may include, but are not limited to, semiconductive materials, insulating materials, conductive materials, etc. The substrate may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by Earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure (e.g., parallel to the Z-axis). The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. The height of a respective material or feature (e.g., structure) may be defined as a dimension in a vertical plane.

The following description provides specific details, such as material types and processing conditions, in order to provide a thorough description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, a person of ordinary skill in the art will understand that the embodiments of the apparatus and methods may be practiced without employing these specific details. Indeed, the embodiments of the apparatus and methods may be practiced in conjunction with conventional semiconductor fabrication techniques employed in the industry.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. Unless the context indicates otherwise, the removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization, or other known methods.

A top view of a microelectronic device structure,′,″,′″ that includes one or more stacks, a memory array region, an edge of array (EOA) region, and a periphery regionis depicted in. The stackincludes alternating dielectric and conductive materials. The EOA regionand the periphery regionconstitute a non-array region of the microelectronic device structure. The memory array regionincludes memory cell pillarsthat form strings of memory cells arranged in columns, and interconnect structureshaving one or more liner materials, such as dielectric liner. The interconnect structuresmay, for example, include the dielectric liner, a first interconnect liner, and a conductive fill material. A material of the interconnect structuresmay exhibit a lower electrical resistivity than other of the materials of the interconnect structures. Although the memory array regionof the microelectronic device structure,′,″,′″ is depicted as having the interconnect structures, the EOA regionand the periphery regionmay also include additional interconnect structures, having the dielectric liner, additional liner materials, or fewer liner materials.

To form the microelectronic device structure,′,″,′″, tiers (not shown) of nitride materials and dielectric materials are formed, with the nitride materials subsequently replaced with conductive materials using slitsas part of a so-called “replacement gate” (RG) or “gate last” process. The nitride materials of the tiers may be removed by exposing the nitride materials to a wet etchant comprising one or more of phosphoric acid, sulfuric acid, hydrochloric acid, nitric acid, or another etch chemistry, such as a so-called “wet nitride strip” comprising a wet etchant comprising phosphoric acid. Tiersof alternating conductive materialsand dielectric materialsare subsequently formed by forming the conductive materialsin spaces resulting from the removed nitride materials. After the RG process, the slitsmay be filled with a dielectric or insulation material. Although the slitsare depicted as formed along a length, or parallel with the y-axis, of the microelectronic device structure,′,″,′″, in other embodiments, the slitsmay be formed along a width, or parallel to the x-axis.

The interconnect structuremay be formed after conducting the RG process, and before the microelectronic device structure,′,″,′″ is electrically connected to additional decks of a multi-deck assembly (see). Alternatively, the interconnect structure, or at least a portion thereof, may be formed before the RG process.

Referring to, the dielectric linermay be formed on sidewalls and bottom surfaces of an interconnect opening, which may have been formed in the tiersof the alternating conductive materialsand dielectric materials(e.g., through use of a conventional patterned mask material formation and a selective etch process). The interconnect openingmay be a high aspect ratio (HAR) opening. For example, the AR of the interconnect openingmay be 5:1, 10:1, 15:1, 20:1, 30:1, 40:1, 50:1, 60:1, 70:1, 80:1, 90:1, 100:1, 200:1, or more. In some embodiments, the AR of the interconnect openingmay be from about 10:1 to about 30:1. The dielectric liner, the first interconnect liner, and the conductive fill materialare formed in the interconnect opening. The dielectric linermay be conformally formed along an exposed surface of a conductive barrier materialand on sidewalls of the tiersof the alternating conductive materialsand dielectric materialsby an ALD process, or by a CVD process. The dielectric linermay be formed to surround, annularly, or be laterally adjacent to and vertically adjacent to (e.g., at the bottom surface of the interconnect opening) the materials that define the interconnect openings. During formation of the microelectronic device structure,′,″,′″, the dielectric linermay form a substantially continuous material over a cap dielectric material, portions of which may be removed (e.g., portions that are outside or above the interconnect openings) through a chemical or mechanical material removal process, such as a chemical mechanical polishing (CMP) planarization process.

Althoughdepicts the interconnect structuresas circular (i.e., top view of right-cylindrical structures) and having annular-shaped portions of the dielectric liner, anddepict the materials of the interconnect structures(e.g., dielectric linerand fill material) as having a rectangular shape, other shapes and configurations are contemplated and included herein. For example, the interconnect structuresmay be configured to have square, triangular, rectangular, trapezoidal, annular, ellipsoidal, or truncated shapes. In some embodiments, the interconnect structuremay exhibit a right-cylindrical shape, having an annular shape of the dielectric linersurrounding, or partially surrounding an inner circumference of the right-cylindrical shape.

The dielectric linermay be a stress compensation material, such as a silicon oxide material (e.g., SiO). In some embodiments, the dielectric lineris a high-quality ALD SiOmaterial. In other embodiments, the dielectric lineris a uniform and conformal ALD silicon oxide material (e.g., a conformal SiOmaterial). The dielectric linermay exhibit a relatively higher electrical resistivity than other materials of the interconnect structure(e.g., higher than the first interconnect linerand the conductive fill material). The dielectric linermay be from about 70 nanometers to about 100 nanometers in thickness, such as from about 80 nanometers to about 90 nanometers in thickness, or from about 83 to about 87 nanometers in thickness.

The stacksof the microelectronic device structure,′,″,′″ include the tiersof the alternating conductive materialsand dielectric materialsformed adjacent to (e.g., vertically adjacent to, over) a conductive material of a source materialadjacent to (e.g., on) a substrate (not shown). The source materialis formed vertically adjacent to additional insulation materialand the substrate by conventional techniques. The alternating conductive materialsand dielectric materialsof the tiersare formed adjacent to (e.g., vertically adjacent to, or on) the source materialby conventional techniques. For example, the multiple tiersof alternating conductive materialsand dielectric materialsmay be formed from alternating nitride materials (not shown) and dielectric materials. The nitride material may be, for example, a silicon nitride (SiN). The dielectric materialsmay be an electrically insulative material. By way of non-limiting example, the dielectric materialsmay be formed of and include a dielectric oxide material (e.g., one or more of SiO, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO, HfO, NbO, TiO, ZrO, TaO, and a MgO), a dielectric oxynitride material (e.g., SiON), a dielectric oxycarbide material (e.g., SiOC), a hydrogenated dielectric oxycarbide material (e.g., SiCOyH), or a dielectric carboxynitride material (e.g., SiOCzN). In some embodiments, the dielectric materialis SiO. The dielectric materialmay be configured to electrically isolate conductive materials. In some embodiments, the source materialis a polysilicon material.

The cap dielectric materialmay have the same material composition as the dielectric materialor a different material composition than the dielectric material. For instance, the cap dielectric materialand the dielectric materialsmay be formed of different materials (e.g., different material compositions) having sufficiently different etch rates. Alternatively, the cap dielectric materialand the dielectric materialsmay be formed of similar materials (e.g., similar material compositions) by different techniques that result in the materials having sufficiently different etch rates to be selectively etchable relative to one another or to other materials of the microelectronic device structure,′,″,′″. By way of non-limiting example, the cap dielectric materialmay be formed of and include a silicon oxide, a silicon oxycarbide, or a silicon oxynitride. The cap dielectric materialmay be doped or undoped to achieve the desired etch selectivity relative to the dielectric materials. In some embodiments, the cap dielectric materialis formed of and includes silicon dioxide. The cap dielectric materialmay be homogeneous in material composition or may be heterogeneous in material composition.

The cap dielectric materialmay include a sacrificial material (not shown) at an upper portion thereof to form a bonding surface for bonding another microelectronic device structure above the microelectronic device structure,′,″,′″, such as another microelectronic device structure (e.g., second deck, see) or a CMOS structure for a CMOS over array (“CoA”) device (not shown). The sacrificial material may be substantially the same material composition as the cap dielectric material, or the material composition of the sacrificial material may be different than the composition of the cap dielectric material. In some embodiments, the sacrificial material may overlie horizontal boundaries of each of the regions,, and. In addition, the substrate or the source materialmay include a sacrificial material for bonding another microelectronic device structure to the bottom of the microelectronic device structure,′,″,′″.

Contact structures,(collectively referred to herein as contact structures) are located adjacent to (e.g., below) an end of the interconnect structures. The contact structuresare electrically coupled to the interconnect structures. The contact structuresmay be located below the tiersand may be formed of and include multiple contact materials, such as an optional conductive barrier material, a conductive contact material, and a metal nitride material. One or more of the contact materialsmay exhibit a higher electrical resistivity than other of the contact materials. In some embodiments, the conductive barrier material, if present, has a higher electrical resistivity than the conductive contact material. In some embodiments, the contact structuresare configured as select line conductive contact structures

The conductive barrier materialmay be a conductive material that has higher electrical resistivity than the conductive contact material. For example, the conductive barrier materialmay include a conductive metal nitride, a conductive metal silicide, or a conductively doped semiconductor material. By way of non-limiting example, the conductive barrier materialmay be formed of and include one or more of tungsten (W), tungsten nitride (WN), nickel (Ni), tantalum (Ta), tantalum nitride (TaN), tantalum silicide (TaSi), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tungsten silicide (WSi), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), molybdenum nitride (MoN), iridium (Ir), iridium oxide (IrO), ruthenium (Ru), ruthenium oxide (RuO), polysilicon, and conductively doped silicon (where x, y, and z include stoichiometric and non-stoichiometric amounts of the components). In some embodiments, the conductive barrier materialis a tungsten silicide (e.g., WSi), which has an electrical resistivity of from about 60 μΩ·cm to about 80 μΩ·cm.

The conductive barrier materialmay be optional, depending on materials used to form the contact structuresand the interconnect structures. In some embodiments, the conductive barrier materialis present to reduce or prevent diffusion or electrical leakage from a conductive material (e.g., copper) of the interconnect structure.

The conductive contact materialmay include any suitable conductive material having a relatively low electrical resistivity relative to other of the contact materials. The conductive contact materialmay include one or more metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.); metal-containing compounds (e.g., metal silicide metal nitride, metal carbide, etc.); and/or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). For example, the conductive contact materialmay have the lowest electrical resistivity relative to the other contact materialsof the contact structuresand less than or equal to the electrical resistivity of the conductive fill material of the interconnect structures. In some embodiments, the conductive contact materialis tungsten, which has an electrical resistivity of from about 5.0 E-4 μΩ·cm to about 6.0 E-4 μΩ·cm.

The metal nitride materialmay have an electrical resistivity that is relatively higher than the electrical resistivity of the conductive contact material. By way of a non-limiting example, the metal nitride materialmay be titanium nitride (TiN), boron nitride (BN), germanium nitride (GeN), aluminum nitride (AlN), or molybdenum nitride (MoN), where each of x, y, z is independently an integer or a non-integer. Alternatively, the metal nitride materialmay be a carbonitride material (e.g., silicon carbonitride (SiCN)), where each of x, y, z is independently an integer or a non-integer. The metal nitride materialmay be a binary or multinary (e.g., ternary) compound. The material of the metal nitride materialmay be the same as, or different than, the material of the conductive barrier material. In some embodiments, the metal nitride materialis titanium nitride (TiN), which has an electrical resistivity of about 25 μΩ·cm.

Referring to, contact structuresof a microelectronic device structure,′,″,′″ are similar to contact structuresand include multiple contact materials, such as the optional conductive barrier material, the conductive contact material, and the metal nitride material. The contact structuresdiffer from the contact structuresin that at least a portion of the source materialintervenes between a bottom surface (e.g., vertically) of the dielectric linerand a top surface of the conductive barrier material. The contact structuresalso differ from the contact structuresby the presence of an additional material, such as a conductive coating material, adjacent to the source material. The formation of the contact structuresand the contact structuresmay also differ. In some embodiments, the contact structuresare configured as access line conductive contact structures

In some embodiments, the dielectric lineris silicon oxide, the source materialis polysilicon, the first interconnect lineris titanium nitride, the conductive fill materialis tungsten, the conductive barrier materialis tungsten silicide, the conductive contact materialis tungsten, and the metal nitride materialis titanium nitride.

The microelectronic device structures,′,″,′″,,′,″,′″ may also differ in the interconnect structures. For instance, the interconnect structuresmay differ in one or more of an extent (e.g., a depth) to which the conductive fill materialextends into surrounding materials or a diameter (e.g., width) of the conductive fill material. By way of example only, the conductive fill materialmay extend to, but not through, the conductive barrier material, as shown in. Alternatively, the conductive fill materialmay extend through the conductive barrier materialand into the conductive contact material, as shown in. The conductive fill materialmay exhibit a substantially uniform diameter along its depth (see) or may exhibit a changing (e.g., non-uniform) diameter along its depth (see,). The interconnect structuresmay be electrically coupled to the contact structures.

The microelectronic device structures,′,″,′″,,′,″,′″ including the interconnect structuresand the contact structures,according to embodiments of the disclosure, may provide increased electrical performance to electronic devices containing the interconnect structuresand the contact structures. Relative dimensions of the materials of the interconnect structuresand the contact structures,may be reduced (e.g., reduced in size) without decreasing electrical performance of the electronic devices. The reduced dimensions of the materials of the interconnect structuresmay be relative to dimensions of conventional interconnect structures and conventional contact structures. The conductive fill materialmay be in direct contact with the conductive barrier materialor the conductive contact material, in comparison to conventional interconnect structures where an interconnect liner separates the interconnect structures from conductive materials of the conventional electronic devices. Since the conductive fill materialhas a relatively lower electrical resistivity compared to the electrical resistivity of the first interconnect liner, the interconnect structuresand the contact structures,provide increased electrical performance to the microelectronic device structures,′,″,′″,,′,″,′″. In some embodiments, the conductive fill materialexhibits the lowest electrical resistivity out of the materials of the interconnect structure. Therefore, the conductive fill materialmay be in direct contact with a material (e.g., the conductive barrier material, the conductive contact material) that has less electrical resistivity relative to the first interconnect liner.

,,, andare partial, cross-sectional views of embodiments of contact structuresand interconnect structuresdepicted at various stages during the process of forming embodiments of the microelectronic device structure,′,″,′″.,,, andare enlargements of the portion of the microelectronic device structure,′,″,′″ indicated by the dashed box in.,,, andillustrate earlier process acts andillustrate the microelectronic device structure,′,″,′″ including the contact structuresand the interconnect structuresin relation to the source material. The contact materialsof the contact structure, including the conductive barrier material, the conductive contact material, and the metal nitride material, are shown in relation to the dielectric liner, the conductive fill material, and the first interconnect linerof the interconnect structures.

Referring to, the dielectric lineris formed (e.g., conformally formed) in a first interconnect openingand has a first lateral thickness, W, a second lateral thickness, W, and a third lateral thickness, W, where Wis substantially equal to a CD of the first interconnect opening. Wand Wmay be substantially equal to one another and Wmay be greater than Wor W. The dielectric lineris formed on opposite sidewalls of the tiersand source materialthrough which the first interconnect openingextends and partially fills the first interconnect opening. As the thickness of the dielectric linerrelative to the CD of the first interconnect opening(e.g., W) increases, a higher probability exists of reduced electrical connectivity between an interconnect structureand a contact structure. To compensate for the reduced electrical connectivity, portions of materials that intervene between a conductive fill material(see) of the interconnect structureand a lower electrical resistivity material of the contact materialsof the contact structureare selectively removed, as described in detail below.

Referring to, a first material removal act is conducted and selectively removes a bottom portion of the dielectric liner, extending a depth of the first interconnect openingand forming a second interconnect opening. The first material removal act removes horizontally oriented portions of the dielectric liner, exposing the conductive barrier material, if present, without substantially removing the dielectric lineron the sidewalls of the tiersand source materialand without substantially removing the conductive barrier material. The second interconnect openingterminates at an upper surface of the conductive barrier material. If no conductive barrier materialis present, the first material removal act terminates at an upper surface of the metal nitride material. A depthmay be an additional depth beyond the initial depth of the interconnect opening, where the additional depth is substantially equivalent to the thickness of the dielectric liner.