Semiconductor Device Structure and Methods of Forming the Same

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.

Therefore, there is a need to improve processing and manufacturing ICs.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments of the present disclosure provide a method to form a semiconductor device structure. The method includes patterning a sacrificial layer to form one or more sacrificial gate electrode layers. The patterning process uses a mask structure including an oxide layer having a thickness ranging from about 60 nm to about 65 nm. The oxide layer having such thickness may help minimize residue formed on the one or more sacrificial gate electrode layers. As a result, gate electrode layer defects and electrical short between the gate electrode layer and the source/drain region are reduced.

While the embodiments of this disclosure are discussed with respect to nanostructure channel FETs, such as Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, Forksheet FETs, implementations of some aspects of the present disclosure may be used in other processes and/or in other devices, such as FinFETs, planar FETs, and other suitable devices. A person having ordinary skill in the art will readily understand other modifications that may be made are contemplated within the scope of this disclosure. In cases where gate all around (GAA) transistor structures are adapted, the GAA transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

show exemplary processes for manufacturing a semiconductor device structureaccording to embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown by, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes is not limiting and may be interchangeable.

are perspective views of various stages of manufacturing a semiconductor device structure, in accordance with some embodiments. As shown in, a semiconductor device structureincludes a stack of semiconductor layersformed over a front side of a substrate. The substratemay be a semiconductor substrate. The substratemay include a crystalline semiconductor material such as, but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In some embodiments, the substrateis a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer.

The substratemay include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on circuit design, the dopants may be, for example phosphorus for an n-type field effect transistors (NFET) and boron for a p-type field effect transistors (PFET).

The stack of semiconductor layersincludes alternating semiconductor layers made of different materials to facilitate formation of nanostructure channels in a multi-gate device, such as nanostructure channel FETs. In some embodiments, the stack of semiconductor layersincludes first semiconductor layersand second semiconductor layers. In some embodiments, the stack of semiconductor layersincludes alternating first and second semiconductor layers,. The first semiconductor layersand the second semiconductor layersare made of semiconductor materials having different etch selectivity and/or oxidation rates. For example, the first semiconductor layersmay be made of Si and the second semiconductor layersmay be made of SiGe. In some examples, the first semiconductor layersmay be made of SiGe and the second semiconductor layersmay be made of Si. Alternatively, in some embodiments, either of the semiconductor layers,may be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combinations thereof.

The first and second semiconductor layers,are formed by any suitable deposition process, such as epitaxy. By way of example, epitaxial growth of the layers of the stack of semiconductor layersmay be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes.

The first semiconductor layersor portions thereof may form nanostructure channel(s) of the semiconductor device structurein later fabrication stages. The term nanostructure is used herein to designate any material portion with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including, for example, a cylindrical in shape or substantially rectangular cross-section. The nanostructure channel(s) of the semiconductor device structuremay be surrounded by a gate electrode. The semiconductor device structuremay include a nanostructure transistor. The nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistors having the gate electrode surrounding the channels. The use of the first semiconductor layersto define a channel or channels of the semiconductor device structureis further discussed below.

Each first semiconductor layermay have a thickness in a range between about 5 nm and about 30 nm. Each second semiconductor layermay have a thickness that is equal, less, or greater than the thickness of the first semiconductor layer. In some embodiments, each second semiconductor layerhas a thickness in a range between about 2 nm and about 50 nm. Three first semiconductor layersand three second semiconductor layersare alternately arranged as illustrated in, which is for illustrative purposes and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of first and second semiconductor layers,can be formed in the stack of semiconductor layers, and the number of layers depending on the predetermined number of channels for the semiconductor device structure. As shown in, an oxide layeris formed on the topmost first semiconductor layer, and a nitride layeris formed on the oxide layer. The oxide layermay be silicon oxide and may have different etch selectivity compared to the nitride layer. The nitride layermay include any suitable nitride material, such as silicon nitride. In some embodiments, the oxide layerand the nitride layermay be a mask structure.

In, fin structuresare formed from the stack of semiconductor layers. Each fin structurehas an upper portion including the semiconductor layers,and a substrate portionformed from the substrate. The fin structuresmay be formed by patterning a hard mask layer, such as the oxide layerand the nitride layer, using multi-patterning operations including photo-lithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. The photo-lithography process may include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing post-exposure bake processes, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the masking element may be performed using an electron beam (e-beam) lithography process. The etching process forms trenchesin unprotected regions through the hard mask layer, through the stack of semiconductor layers, and into the substrate, thereby leaving the plurality of extending fin structures. The trenchesextend along the X direction. The trenchesmay be etched using a dry etch (e.g., RIE), a wet etch, and/or combination thereof.

In, after the fin structuresare formed, an insulating materialis formed on the substrate. The insulating materialfills the trenchesbetween neighboring fin structuresuntil the fin structuresare embedded in the insulating material. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and/or an etch-back method, is performed such that the top of the fin structuresis exposed. The insulating materialmay be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-K dielectric material, or any suitable dielectric material. The insulating materialmay be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or flowable CVD (FCVD).

In, the insulating materialis recessed to form isolation regions. The recess of the insulating materialexposes portions of the fin structures, such as the stack of semiconductor layers. The recess of the insulating materialreveals the trenchesbetween the neighboring fin structures. The isolation regionsmay be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. A top surface of the insulating materialmay be level with or below a surface of the second semiconductor layersin contact with the substrate portionformed from the substrate. In some embodiments, the isolation regionsare the STI. In some embodiments, the oxide layerand the nitride layerare also removed during the recessing of the insulating material.

In, a first sacrificial layeris formed on the exposed surfaces of the semiconductor device structure, and a second sacrificial layeris formed on the first sacrificial layer. In some embodiments, the first sacrificial layerincludes a dielectric material, such as an oxide, for example silicon oxide. The first sacrificial layermay be formed by any suitable process, such as CVD or PECVD. In some embodiments, the first sacrificial layeris a conformal layer formed by a conformal process, such as atomic layer deposition (ALD). The first sacrificial layermay have a thickness in the Z direction ranging from about 3 nm to about 5 nm. In some embodiments, the second sacrificial layerincludes a semiconductor material, such as polysilicon. The second sacrificial layermay be formed by any suitable process, such as CVD, PECVD, ALD, or PVD. The second sacrificial layermay be first deposited to embed the fin structures, followed by a planarization process, such as a CMP process. In some embodiments, the second sacrificial layermay have a thickness in the Z direction ranging from about 50 nm to about 60 nm.

is a cross-sectional side view of the semiconductor device structuretaken along line A-A of, in accordance with some embodiments.are cross-sectional side views of various stages of manufacturing the semiconductor device structuretaken along line A-A of, in accordance with some embodiments.illustrate a method to form one or more sacrificial gate electrode layers() having minimum amount of residue. As shown in, a plurality of mask layers are formed on the second sacrificial layer. In some embodiments, the plurality of mask layers includes a first mask layerdisposed on the second sacrificial layer, a second mask layerdisposed on the first mask layer, a third mask layerdisposed on the second mask layer, a fourth mask layerdisposed on the third mask layer, a fifth mask layerdisposed on the fourth mask layer, and a sixth mask layerdisposed on the fifth mask layer. In some embodiments, the fourth mask layer, the fifth mask layer, and the sixth mask layerform a resist structure. For example, the resist structure may be a tri-layer photoresist. The fourth mask layermay be a bottom layer, the fifth mask layermay be a middle layer, and the sixth mask layermay be a photoresist layer. The fourth mask layerand the fifth mask layerare made of different materials such that the optical properties and/or etching properties of the fourth mask layerand the fifth mask layerare different from each other. In some embodiments, the fourth mask layermay be a carbon layer, and the fifth mask layermay be a silicon-rich layer designed to provide an etch selectivity between the fifth mask layerand the fourth mask layer. The sixth mask layermay be a chemically amplified photoresist layer and can be a positive tone photoresist or a negative tone photoresist. The sixth mask layermay include a polymer, such as phenol formaldehyde resin, a poly(norbornene)-co-malaic anhydride (COMA) polymer, a poly(4-hydroxystyrene) (PHS) polymer, a phenol-formaldehyde (bakelite) polymer, a polyethylene (PE) polymer, a polypropylene (PP) polymer, a polycarbonate polymer, a polyester polymer, or an acrylate-based polymer, such as a poly (methyl methacrylate) (PMMA) polymer or poly (methacrylic acid) (PMAA). The sixth mask layermay be formed by spin-on coating. The sixth mask layermay be patterned to have openingsformed therein.

In some embodiments, the first mask layermay be a SiN layer and has a thickness ranging from about 20 nm to about 30 nm, the second mask layermay be an oxide layer, such as a silicon oxide layer, and has a thickness ranging from about 60 nm to about 65 nm, the third mask layermay include the same material as the first mask layerand has a thickness ranging from about 20 nm to about 30, the fourth mask layerhas a thickness ranging from about 40 nm to about 50 nm, and the fifth mask layerhas a thickness ranging from about 20 nm to about 30 nm.

As shown in, the openingsare extended through the fifth mask layer. In some embodiments, a first etch process is performed to remove portions of the fifth mask layer. The first etch process may be any suitable process. In some embodiments, a plasma etch process is performed to extend the openingsthrough the fifth mask layer. The plasma etch process may use a carbon-based etchant, such as CHF, CHF, CF, and/or CF. Carrier gas or passivation gas, such as Nand/or He, may flow along with the etchant. The plasma power of the plasma etch process may range from about 500 W to about 2000 W, and the process pressure may range from about 10 mT to about 50 mT.

As shown in, the openingsare extended through the fourth mask layer. In some embodiments, a second etch process is performed to remove portions of the fourth mask layer. The second etch process may be any suitable process. In some embodiments, a plasma etch process is performed to extend the openingsthrough the fourth mask layer. The plasma etch process may use an oxygen-based etchant, such as SOand/or O, and He may flow along with the etchant to assist with the plasma etch process. The plasma power of the second etch process may be greater than the plasma power of the first etch process. In some embodiments, the plasma power of the second etch process ranges from about 1000 W to about 4000 W. The process pressure of the second etch process may be less than the process pressure of the first etch process. In some embodiments, the process pressure of the second etch process ranges from about 1 mT to about 20 mT.

As shown in, the openingsare extended through the third mask layer. In some embodiments, a third etch process is performed to remove portions of the third mask layer. The third etch process may be any suitable process. In some embodiments, a plasma etch process is performed to extend the openingsthrough the third mask layer. The plasma etch process may use the same etchant and other gases as the first etch process, with the exception of Ngas. In some embodiments, additional etchants, such as HBr and/or O, may be used in the third etch process. The plasma power of the third etch process may be less than the plasma power of the second etch process. In some embodiments, the plasma power of the third etch process ranges from about 500 W to about 2000 W. The process pressure of the third etch process may be substantially the same as the process pressure of the second etch process.

As shown in, the openingsare extended through the second mask layer. In some embodiments, a fourth etch process is performed to remove portions of the second mask layer. The fourth etch process may be any suitable process. In some embodiments, a plasma etch process is performed to extend the openingsthrough the second mask layer. The plasma etch process may use a carbon-based etchant, such as CHF, CHF, CF, and/or CF. Carrier gas or passivation gas, such as Ar and/or O, may flow along with the etchant. The plasma power of the fourth etch process may be less than the plasma power of the first etch process. In some embodiments, the plasma power of the fourth etch process ranges from about 10 W to about 100 W. The process pressure of the fourth etch process may be substantially the same as the process pressure of the third etch process.

As described above, in some embodiments, the thickness of the second mask layerranges from about 60 nm to about 65 nm. The fourth etch process is performed to extend the openingsthrough the second mask layerhaving the thickness ranging from about 60 nm to about 65 nm. In some embodiments, the thickness of the second mask layerranges from about 90 nm to about 150 nm. In such embodiment, a fifth etch process is performed to remove portions of the thicker second mask layer. The fifth etch process is different from the fourth etch process. The fifth etch process may include the same etchant and other gases as the fourth etch process. However, the process pressure of the fifth etch process is higher than that of the fourth etch process. Furthermore, the process time of the fifth etch process is substantially longer than the fourth etch process. With the thicker second mask layer, the aspect ratio of the openingsis higher after the formation of the sacrificial gate electrode layers() compared to the aspect ratio of the openingswith the thinner second mask layer. The high aspect ratio of the openingscan lead to residue formed in corners of the subsequently formed sacrificial gate electrode layers(), which can lead to defective gate electrode layers(). By reducing the thickness of the second mask layer, the aspect ratio of the openingsis lowered. The lowered aspect ratio of the openingsmay help minimize residue formed in the corners of the sacrificial gate electrode layers. Thus, the fourth etch process is different from the fifth etch process due to the different thicknesses of the second mask layer. The lower process pressure of the fourth etch process can enhance vertical ions in the plasma. Furthermore, in some embodiments, the flow rates of the etchants and/or other gases of the fourth etch process may be substantially slower than those of the fifth etch process.

As shown in, the openingsare extended through the first mask layerto expose portions of the second sacrificial layer. In some embodiments, a sixth etch process is performed to remove portions of the first mask layer. The sixth etch process may be any suitable process. In some embodiments, the sixth etch process is similar to the third etch process, with the exception of using Ar instead of HBr and He.

As shown in, the openingsare extended through the second sacrificial layerto form the sacrificial gate electrode layers. In some embodiments, multiple processes are performed to remove portions of the second sacrificial layer. The multiple processes may include a main etching process, a breakthrough process, a soft landing process, and an over etching process. The main etching process may be a plasma etch process and may utilize etchants and other gases such as Cl, HBr, CHF, CHF, CHF, O, and/or Ar. The process pressure of the main etching process may range from about 40 mT to about 800 mT, and the plasma power of the main etching process may range from about 200 W to about 1500 W. The breakthrough process may be performed after the main etching process. In some embodiments, the breakthrough process is a plasma etch process and may utilize etchants and other gases such as CF, CF, CHClF, and/or Ar. The process pressure of the breakthrough process may range from about 1 mT to about 100 mT, and the plasma power of the breakthrough process may range from about 50 W to about 1000 W. In some embodiments, an ash process may be performed between the main etching process and the breakthrough process. The ash process may be a plasma process and may utilize gases such as CO, CH, SO, and/or Ar. The process pressure of the ash process may range from about 1 mT to about 100 mT, and the plasma power of the ash process may range from about 500 W to about 4000 W.

After the breakthrough process, the soft landing process may be performed. The soft landing process may be a plasma etch process and may utilize etchants and gases such as Cl, HBr, CHF, CF, CF, CHClF, HF, O, and/or Ar. In some embodiments, the soft landing process has a plasma power ranging from about 100 W to about 500 W. The plasma power may be generated by a first radio frequency (RF) power source, and the plasma power may be pulsed. In some embodiments, the soft landing process has a bias power ranging from about 600 W to about 1200 W. The bias power may be generated by a second RF power source that is different from the first RF power source. The plasma power and the bias power may be pulsed.illustrates pulsing schemes of the plasma power and the bias power.

As shown in, in some embodiments, the plasma power Ws and the bias power Wbhas the same pulsing scheme. The pulsing scheme shown inis for a time period T. In some embodiments, the time period T ranges from about 5 ms to about 15 ms, such as about 10 ms. Within the time period T, the pulsing scheme has an active period and an off period. In some embodiments, the active period is about 80 percent to about 90 percent of the time period T, while the off period is about 10 percent to about 20 percent of the time period T. The off period may follow the active period. As shown in, during the active period, the plasma power Ws has a duty cycle of about 1 percent to about 6 percent, such as about 3 percent. In other words, the plasma power is pulsed multiple times during the active period. During the off period, the plasma power Ws is turned off. As shown in, during the active period, the bias power Wbhas duty cycle of about 1 percent to about 8 percent, such as about 4 percent. In other words, the bias power is pulsed multiple times during the active period. During the off period, the bias power Wbis turned off. The pulsing scheme in time period T may be repeated multiple times during the soft landing process. In some embodiments, the soft landing process has a time duration ranging from about 10 s to about 60 s.

In some embodiments, due to the smaller thickness of the second mask layer, the openingshave a smaller aspect ratio, which can lead to re-deposition of byproducts. During the plasma etch processes, byproducts, such as SiO, SiO—Cl, SiO—HBr, SiO—N, or SiO—Ar, may be formed and may re-deposit on the surfaces of the semiconductor device structure. These byproducts may negatively affect the etching of the second sacrificial layer. The pulsing schemes of the plasma power Ws and the bias power Wbhelp reduce the re-deposition of byproducts. For example, during the off period, the plasma power Ws and the bias power Wbare turned off, and the vacuum pump is still running to remove byproducts from the processing chamber. As a result, re-deposition of byproducts is reduced.

In some embodiments, an optional passivation process may be performed after the soft landing process, and an optional second soft landing process may be performed after the passivation process. The passivation process protects the vertical surfaces of the second sacrificial layer. In some embodiments, the passivation process is a plasma treatment process using a nitrogen-containing plasma. The plasma power of the passivation process may range from about 500 W to about 4000 W and has a duty cycle ranging from about 3 percent to about 20 percent. The process pressure of the passivation process may range from about 50 mT to about 300 mT. The optional second soft landing process may be the same as the soft landing process described above.

Next, a flush process is performed. The flush process may be a plasma etch process that removes the byproducts from the surfaces of the semiconductor device structure. The flush process may utilize etchants such as CFand/or CFand may have a plasma power ranging from about 50 W to about 1000 W. The process pressure of the flush process may range from about 1 mT to about 100 mT. By removing the byproducts from the semiconductor device structure, less residue may be formed in the corners of the subsequently formed sacrificial gate electrode layer.

After the flush process, the over etching process is performed. The over etching process may be a plasma etch process and may utilize etchants and gases such as Cl, HBr, CHF, CF, CF, CHClF, HF, O, and/or Ar. The process pressure of the over etching process may range from about 40 mT to about 800 mT. The plasma power of the over etching process may range from about 300 W to about 1000 W. In some embodiments, in order to further remove the byproducts, a second bias power source may be used to provide a second bias power during the over etching process. For example, the over etching process may include a first bias power ranging from about 400 W to about 1200 W and a second bias power ranging from about 10 W to about 200 W. The duty cycles of the plasma power, the first bias power, and the second bias power may range from about 3 percent to about 20 percent.

illustrates pulsing schemes of a plasma power and two bias powers of the over etching process, in accordance with some embodiments. As shown in, in some embodiments, the plasma power Ws of the over etching process and the first bias power Wbof the over etching process has the same pulsing scheme, while the second bias power Wbof the over etching process has a different pulsing scheme compared to those of the plasma power Ws and the first bias power Wb. In some embodiments, the duty cycles of the plasma power Ws and the first bias power Wbare 20 percent, while the duty cycle of the second bias power is 10 percent. In some embodiments, the second bias power Wbis turned on after the first bias power Wbis turned off, as shown in.

After the over etching process, the second sacrificial layeris patterned to form two or more sacrificial gate electrode layers, as shown in. The third, fourth, fifth and sixth mask layers,,,may be removed during or before the patterning of the second sacrificial layer. The first and second mask layers,may remain on the sacrificial gate electrode layers, as shown in. As a result of the thinner second mask layerand the processes to pattern the second sacrificial layer, the residue formed in the corner of the sacrificial gate electrode layermay be reduced or eliminated. For example, the pulsing schemes of the plasma power and the bias power of the soft landing process include an off period, which helps to remove the byproducts. The flush process also removes the byproducts. Furthermore, the additional bias power applied during the over etching process further removes the byproducts. The low aspect ratio of the openingsalong with the reduced amount of byproducts lead to the sacrificial gate electrode layerswith small amount or free of residue in the corners.

are various views of one of various stages of manufacturing the semiconductor device structure, in accordance with some embodiments. The first and second mask layers,are omitted infor clarity.is a top view of the semiconductor device structureshown in, andis a cross-sectional side view of the semiconductor device structuretaken along line A′-A′ of. As shown in, the first sacrificial layermay be also patterned by an etch process. A small amount of residuewhich may be a portion of the second sacrificial layer, may be formed in the corners between the sacrificial gate electrode layerand the stack of semiconductor layers. The residuemay be formed on the insulating material(). In some embodiments, due to the minimized residuein the corners, the side surfaces of the remaining first sacrificial layermay be substantially aligned with the corresponding side surfaces of the sacrificial gate electrode layers, as shown in. In some embodiments, a lateral distance between the side surface of the remaining first sacrificial layerand the corresponding side surface of the sacrificial gate electrode layermay range from about 0 nm to about 2 nm. Furthermore, the side surface of the sacrificial gate electrode layermay be substantially straight, as a result of minimized residuein the corners. In some embodiments, an angle A is formed between the side surface of the sacrificial gate electrode layerand the top surface of the topmost first semiconductor layer, and the angle A ranges from about 95 degrees to about 105 degrees, as shown in. The sacrificial gate electrode layer, the portion of the first sacrificial layerdisposed under the sacrificial gate electrode layer, and the first and second mask layers,(not shown) form a sacrificial gate structure. While two sacrificial gate structuresare shown in, three or more sacrificial gate structuresmay be arranged along the X direction in some embodiments.

In some embodiments, as shown in, an angle B is formed between the side surface of the second semiconductor layerand the side surface of the sacrificial gate electrode layer. As shown in, the side surface of the top second semiconductor layerand the side surface of the sacrificial gate electrode layerform the angle B, the side surface of the middle second semiconductor layerand the side surface of the residueform the angle B, and the side surface of the bottom second semiconductor layerand the side surface of the residueform the angle B. The angle Bmay range from about 90 degrees to about 92 degrees, the angle Bmay range from about 90 degrees to about 94 degrees, and the angle Bmay range from about 90 degrees to about 98 degrees. In some embodiments, the angles B, B, Bare substantially the same due to the minimum amount of residueIn some embodiments, the angle Bis greater than the angle B, which is greater than the angle B, due to the existence of the residue

Next, as shown in, gate spacersare formed on sidewalls of the sacrificial gate structures. The first and second mask layers,are omitted infor clarity. The gate spacersmay be formed by conformally depositing one or more layers, such as first gate spacerA and second gate spacerB, as shown in, and then anisotropically etching the one or more layers, for example. The gate spacersA,B may be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof. The portions of the fin structuresthat are covered by the sacrificial gate electrode layerof the sacrificial gate structureserve as channel regions for the semiconductor device structure.

As shown in, the portions of the fin structuresnot covered by the sacrificial gate structureand the gate spacersare recessed to a level above, at, or below the top surfaces of the isolation regions. The recess of the portions of the fin structurescan be done by an etch process, either isotropic or anisotropic etch process, and the etch process may be selective with respect to one or more crystalline planes of the substrate. The etch process may be a dry etch, such as a RIE, NBE, or the like, or a wet etch, such as using tetramethyalammonium hydroxide (TMAH), ammonium hydroxide (NHOH), or any suitable etchant. Next, edge portions of each second semiconductor layerof the stack of semiconductor layersare removed horizontally along the X direction. The removal of the edge portions of the second semiconductor layersforms cavities. In some embodiments, the portions of the second semiconductor layersare removed by a selective wet etch process. In cases where the second semiconductor layersare made of SiGe and the first semiconductor layersare made of silicon, the second semiconductor layercan be selectively etched using a wet etchant such as, but not limited to, ammonium hydroxide (NHOH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions.

After removing edge portions of each second semiconductor layers, a dielectric layer is deposited in the cavities to form dielectric spacers, as shown in. The dielectric spacersmay be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacersmay be formed by first forming a conformal dielectric layer using a conformal deposition process, such as ALD, followed by an anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacers. The dielectric spacersare protected by the first semiconductor layersduring the anisotropic etching process. The remaining second semiconductor layersare capped between the dielectric spacersalong the X direction.

As shown in, the top first semiconductor layerhas a width W, the middle first semiconductor layerhas a width W, and the bottom first semiconductor layerhas a width W. A distance Dis between horizontally adjacent top first semiconductor layers, a distance Dis between horizontally adjacent middle first semiconductor layers, a distance Dis between horizontally adjacent bottom first semiconductor layers, and a distance Dbetween horizontally adjacent substrate portions. The distance Dis measured at a location about haft of the height H, which is measured from the bottom of the bottom second semiconductor layerto the bottom of the opening. In some embodiments, because the thickness of the second mask layer() is reduced, the process to recess the exposed portions of the fin structuresis performed in the openingshaving a low aspect ratio, compared to the thicker second mask layer. With the low aspect ratio openings, the side surfaces of the first semiconductor layersare substantially straight, as shown in. In some embodiments, the widths W, W, Wmay be substantially the same, and the distances D, D, Dmay be substantially the same. In some embodiments, the difference between Wand Wmay range from about 0 nm to about 1 nm. In some embodiments, the distance Dis less than the distance D, D, D, and the difference between the distance Dand the distance D, D, Dis less than about 2 nm.

As shown in, source/drain (S/D) regionsare formed from the substrate portion. The S/D regionsmay grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the material used for the first semiconductor layers. In this disclosure, a source region and a drain region are interchangeably used, and the structures thereof are substantially the same. Furthermore, source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context. The S/D regionsmay be made of one or more layers of Si, SiP, SiC and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For p-channel FETs, p-type dopants, such as boron (B), may also be included in the S/D regions. The S/D regionsmay be formed by an epitaxial growth method using CVD, ALD or MBE.

Next, as shown in, a contact etch stop layer (CESL)is conformally formed on the exposed surfaces of the semiconductor device structure. The CESLcovers the sidewalls of the sacrificial gate structure, the insulating material, and the S/D regions. The CESLmay include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layeris formed on the CESLover the semiconductor device structure. The materials for the ILD layermay include compounds including Si, O, C, and/or H, such as silicon oxide, SiCOH, or SiOC. Organic materials, such as polymers, may also be used for the ILD layer. The ILD layermay be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the ILD layer, the semiconductor device structuremay be subject to a thermal process to anneal the ILD layer.

After the ILD layeris formed, a planarization operation, such as CMP, is performed on the semiconductor device structureuntil the sacrificial gate electrode layeris exposed, as shown in.

are cross-sectional top views of the semiconductor device structuretaken along line B-B and line C-C of, respectively, in accordance with some embodiments.is a cross-sectional top view of a portion of the semiconductor device structuretaken along line B-B of, which is across the bottommost second semiconductor layer. As shown in, in some embodiments, the residueremains adjacent the bottommost second semiconductor layer. In some embodiments, because of the existence of the residuethe portion of the first gate spacerA includes a straight portion in contact with the sidewall of the sacrificial gate electrode layerand an end portion in contact with the S/D region, and an angle C is formed between the straight portion and the end portion. In some embodiments, the angle C is an obtuse angle due to the existence of the residueas shown in. For example, the angle C may range from about 95 degrees to about 130 degrees. In some embodiments, the angle C is less than 130 degrees. If the angle B is greater than about 130 degrees, the gap between the first gate spacerA and the first sacrificial layermay be too large. As a result, the first sacrificial layermay be removed to expose the S/D regionduring the removal of the sacrificial gate structure. With the angle C being less than about 130 degrees, the gap between the first gate spacerA and the first sacrificial layeris small, and the portion of the first sacrificial layerin contact with the S/D regionis not removed during the removal of the sacrificial gate structure. Furthermore, because of the small gap between the first gate spacerA and the first sacrificial layer, the process window for removing the sacrificial gate structuremay be enlarged.

is a cross-sectional top view of a portion of the semiconductor device structuretaken along line C-C of, which is across the topmost second semiconductor layer. As shown in, the residueis not present adjacent the topmost second semiconductor layer. Without the residuethe portion of the first sacrificial layeris removed during the patterning of the first sacrificial layernot covered by the sacrificial gate electrode layer. Thus, the first sacrificial layeris not located between the gate spacerand the dielectric spacer. As a result, the angle C between the straight portion and the end portion of the first gate spacerA is less than the angle C located adjacent the bottommost second semiconductor layer(). In some embodiments, the angle C adjacent the topmost second semiconductor layeris a right angle. The angle C adjacent the middle second semiconductor layermay be between the angle C adjacent the topmost second semiconductor layerand the angle C adjacent the bottommost second semiconductor layer. In other words, the angle C increases in a direction towards the substrate.

As shown in, the sacrificial gate structureand the second semiconductor layersare removed. The removal of the sacrificial gate structureand the semiconductor layersforms an opening between gate spacersand between first semiconductor layers. The ILD layerprotects the S/D regionsduring the removal processes. The sacrificial gate structurecan be removed using plasma dry etching and/or wet etching. The sacrificial gate electrode layermay be first removed by any suitable process, such as dry etch, wet etch, or a combination thereof, followed by the removal of the exposed portions of the first sacrificial layer, which may also be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layerbut not the gate spacers, the ILD layer, and the CESL.

The second semiconductor layersmay be removed using a selective wet etching process. In cases where the second semiconductor layersare made of SiGe and the first semiconductor layersare made of Si, the chemistry used in the selective wet etching process removes the SiGe while not substantially affecting Si, the dielectric materials of the gate spacers, and the dielectric spacers. In one embodiment, the second semiconductor layerscan be removed using a wet etchant such as, but not limited to, hydrofluoric (HF), nitric acid (HNO), hydrochloric acid (HCl), phosphoric acid (HPO), a dry etchant such as fluorine-based (e.g., F) or chlorine-based gas (e.g., Cl), or any suitable isotropic etchants.

After the formation of the nanostructure channels (i.e., the exposed portions of the first semiconductor layers), a gate dielectric layeris formed to surround the exposed portions of the first semiconductor layers, and a gate electrode layeris formed on the gate dielectric layer. The gate dielectric layerand the gate electrode layermay be collectively referred to as a gate structure. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layerand the exposed surfaces of the first semiconductor layers. In some embodiments, the gate dielectric layerincludes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-K dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-K dielectric material include HfO, HfSiO, HfSiON, HfTaO, HfTIO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO—AlO) alloy, other suitable high-K dielectric materials, and/or combinations thereof. The gate dielectric layermay be formed by CVD, ALD or any suitable deposition technique. The gate electrode layermay include one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or any combinations thereof. The gate electrode layermay be formed by CVD, ALD, electro-plating, or other suitable deposition technique. The gate electrode layermay be also deposited over the upper surface of the ILD layer. The gate dielectric layerand the gate electrode layerformed over the ILD layerare then removed by using, for example, CMP, until the top surface of the ILD layeris exposed.

As shown in, as mentioned above, the low aspect ratio openingsmay lead to substantially straight side surfaces of the first semiconductor layersand the second semiconductor layers. After forming the dielectric spacers, the side surfaces of the dielectric spacersare also substantially straight. In some embodiments, the dielectric spacerlocated below the bottom first semiconductor layerhas a side surface that forms an angle D with a plane P defined by the bottom surface of the gate dielectric layer. The dielectric spacerlocated above the bottom first semiconductor layer has a side surface that forms an angle E with the plane P, and the dielectric spacerlocated below the top first semiconductor layerhas a side surface that forms an angle F with the plane P. The angle F may range from about 90 degrees to about 90.5 degrees, the angle E may range from about 90.5 degrees to about 91 degrees, and the angle D may range from about 94 degrees to about 97 degrees. In some embodiments, the angle D is substantially greater than the angle E, which is substantially greater than the angle F. In some embodiments, because the distances D, D, Dare substantially the same, the portion of the S/D regionlocated between the horizontally adjacent first semiconductor layersmay have a substantially constant width along the X direction.

are cross-sectional top views of the semiconductor device structuretaken along line D-D and line E-E of, respectively, in accordance with some embodiments.is a cross-sectional top view of a portion of the semiconductor device structuretaken along line D-D of, which is across the portion of the gate electrode layerlocated below the bottommost first semiconductor layer. As shown in, the portion of the first sacrificial layerlocated between the gate spacerand the dielectric spacerremains and separates the gate dielectric layerand the S/D region. In some embodiments, the thickness of the portion of the first sacrificial layerlocated between the gate spacerand the dielectric spaceralong the Y direction is less than about 1 nm, such as from about 0.3 nm to about 1 nm. In some embodiments, the first sacrificial layeris in contact with the S/D region, the first gate spacerA, and the dielectric spacer. In some embodiments, the gate dielectric layerincludes a first portion located adjacent the gate spacerand a second portion located adjacent the dielectric spacer. An angle G may be formed between the first and second portions of the gate dielectric layer, as shown in. In some embodiments, the angle G ranges from about 150 degrees to about 165 degrees.