Method for Modifying Metal-Including Material in Semiconductor Manufacturing Process

This application is a divisional application of U.S. patent application Ser. No. 17/731,057, filed on Apr. 27, 2022, the content of which is incorporated herein by reference in its entirety.

Along with increasing demands on more advanced semiconductor devices, manufacturing processes thereof also encounter a lot of challenges. To overcome such challenges, the industry has put much effort in developing different techniques applicable to methods for manufacturing semiconductor devices.

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “on,” “above,” “top,” “bottom,” “upper,” “lower,” “over,” “beneath,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The present disclosure is directed to a method for manufacturing a semiconductor device, in which a surface of a metal-including layer is modified by forming an amphiphilic polymer layer between the metal-including layer and a hydrophobic polymer layer (e.g., bottom anti-reflective coating (BARC)) so as to enhance a bonding force therebetween. The present disclosure provides an exemplary method to manufacture, for example, but not limited to, a metal-oxide-semiconductor field effect transistor (MOSFET), such as a planar MOSFET, a fin-type FET (FinFET), a gate-all-around (GAA) nanosheet FET, or other suitable semiconductor devices.

is a flow diagram illustrating a method for manufacturing the semiconductor device in accordance with some embodiments.illustrate schematic views of the intermediate stages of the method in accordance with some embodiments. Some repeating structures are omitted infor the sake of brevity. Additional steps can be provided before, after or during the method, and some of the steps described herein may be replaced by other steps or be eliminated.

Referring toand the example illustrated in, the method begins at step, where a semiconductor structure is formed.is an enlarged top view of the semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate(see), a plurality of semiconductor fins, a dummy portion, a plurality of isolation portions, a plurality of fin sidewalls, and two gate spacers.

The semiconductor substratemay be made of elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The material for forming the semiconductor substratemay be doped with p-type impurities or n-type impurities, or undoped. In addition, the semiconductor substratemay be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. Other suitable materials for the semiconductor substrateare within the contemplated scope of the present disclosure.

The semiconductor finsare formed on the semiconductor substrate, and may be made from a material the same or different from that of the semiconductor substrate. Since suitable materials for the semiconductor finsare similar to those for the semiconductor substrate, the details thereof are omitted for the sake of brevity. Other suitable materials for the semiconductor finsare within the contemplated scope of the present disclosure. In some embodiments, the semiconductor finsextend in an X direction, and are spaced apart from each other in a Y direction transverse to the X direction. Although two of the semiconductor finsare shown in, the number of the semiconductor finscan be varied according to the layout design of the semiconductor structure.

The isolation portionsare formed on the semiconductor substrateto isolate the semiconductor finsfrom each other. The isolation portionsmay each be a portion of a shallow trench isolation (STI), a deep trench isolation (DTI), or other suitable structures, and may be made of an oxide material (for example, silicon oxide), a nitride material (for example, silicon nitride), or a combination thereof. Other suitable materials for the isolation portionsare within the contemplated scope of the present disclosure.

The dummy portionextends in the Y direction, and is formed over the semiconductor fins. In some embodiments, the dummy portionincludes a hard mask, a dummy gate(see) formed beneath the hard mask, and a dummy gate dielectric (not shown) formed beneath the dummy gateto separate the dummy gatefrom the semiconductor fins. In some embodiments, the hard maskmay include silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof; the dummy gatemay include polycrystalline silicon, single crystalline silicon, amorphous silicon, or combinations thereof; and the dummy dielectric may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant (k) materials, or combinations thereof. Other suitable materials for the dummy portionare within the contemplated scope of the present disclosure.

The gate spacersare formed at two opposite sides of the dummy portion, and each of the semiconductor finshas two recessed fin portionsexposed from the dummy structureand the gate spacers. At two opposite sides of each of the recessed fin portions, two corresponding ones of the fin sidewallsare formed. Each of the gate spacersand the fin sidewallsmay include silicon oxide, silicon nitride, or a combination thereof. Other suitable materials for the gate spacersand the fin sidewallsare within the contemplated scope of the present disclosure.

In some embodiments, the semiconductor structure may be formed by (i) patterning the semiconductor substrateto form the semiconductor fins, (ii) forming an isolation layer over the semiconductor substrateand the semiconductor finsfollowed by a planarization process, for example, but not limited to, chemical mechanism polishing (CMP), to form the isolation portions, (iii) recessing the isolation portionsto expose upper portions of the semiconductor fins, (iv) forming the dummy portionover the semiconductor finssuch that each of the semiconductor finshas two fin portions exposed from and located at two opposite sides of the dummy portion, (v) forming, the two gate spacersat two opposite sides of the dummy portion, and the two fin sidewallsat two opposite sides of each of the fin portions of the semiconductor fins, and (vi) recessing the fin portions of each of the semiconductor finsto form the recessed fin portions. Other suitable processes for forming the semiconductor structureare within the contemplated scope of the present disclosure.

Referring toand the example illustrated in, the method proceeds to step, where a plurality of source/drain portionsare respectively formed in the recessed fin portions. In some embodiments, two or more adjacent ones of the source/drain portionsmay be merged to form a merged portionA according to designs. For instance, as shown in, two of the source/drain portionsare merged to form a diamond-like shape structure, and two merged portionsA shown inare formed at two opposite sides of the dummy portion. Please note that each of the merged portionsA (including a plurality of the source/drain portions) may also be referred to as a source/drain portion.

In some embodiments, each of the source/drain portionsmay include multiple epitaxial layers, each may include silicon, silicon germanium, silicon carbide, germanium, III-V compound semiconductors, or combinations thereof. Other suitable materials for the epitaxial layers are within the contemplated scope of the present disclosure. For an n-FET device, each of the epitaxial layers may be doped with an n-type impurity, for example, but not limited to, phosphorus. For a p-FET device, each of the epitaxial layers may be doped with a p-type impurity, for example, but not limited to, boron. The semiconductor epitaxial layer may include silicon, silicon germanium, silicon carbide, germanium, III-V compound semiconductors, or combinations thereof. Other suitable materials for the p-type impurity and/or the n-type impurity are within the contemplated scope of the present disclosure.

Referring toand the example illustrated in, the method proceeds to step, where a contact etch stop layer (CESL)and a dielectric layerare sequentially formed over the structure shown in. In some embodiments, the dielectric layeris known as the interlayer dielectric (ILD) layer.is a cross sectional view taken along line A-A of the structure shown in. In, some elements, such as the CESL, the fin side walls, and so on, are not shown for the sake of clarity. In some embodiments, stepis performed by sequentially depositing the CESLand the dielectric layerusing a blanket deposition process, such as, but not limited to, chemical vapor deposition (CVD), high density plasma CVD (HDPCVD), sub-atmospheric CVD (SACVD), or molecular layer deposition (MLD), followed by a planarization process, for example, but not limited to, CMP, thereby exposing the dummy gate. In other words, the hard maskshown inis removed after step. Other suitable processes for forming the CESLand the dielectric layerare within the contemplated scope of the present disclosure.

In some embodiments, the CESLincludes, for example, but not limited to, silicon nitride, carbon-doped silicon nitride, other suitable materials, or combinations thereof. The dielectric layerincludes a dielectric material such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. Other suitable materials for forming the CESLand the dielectric layerare within the contemplated scope of the present disclosure.

Referring toand the example illustrated in, the method proceeds to step, where a replacement gate (RPG) process is performed to replace the remaining of the dummy portion(i.e., the dummy gateand the dummy dielectric) with a gate portionwhich includes a gate electrodeand a gate dielectric. In some embodiments, stepincludes (i) removing the dummy gateand the dummy dielectric to form a trench (not shown) using dry etching, wet etching, other suitable processes, or combinations thereof, (ii) sequentially depositing layers of the gate dielectricand the gate electrodeto fill the trench by a blanket deposition process, such as CVD, HDPCVD, SACVD, MLD, or physical vapor deposition (PVD), and (iii) performing a planarization process, for example, but not limited to, CMP, to remove excesses of the gate electrodeand the gate dielectricand to expose the dielectric layer. Other suitable processes for forming the gate portionare within the contemplated scope of the present disclosure.

In some embodiments, the gate dielectricincludes silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant (k) materials, other suitable materials, or combinations thereof, and the gate electrodeincludes aluminum, tungsten, copper, other suitable materials, or combinations thereof. Other suitable materials for forming the gate portionare within the contemplated scope of the present disclosure.

Referring toand the example illustrated in, the method proceeds to step, where a plurality of trenches(one of which is shown) are formed in the dielectric layer.is a view similar to that of, but illustrating the structure after completing step. For better understanding,illustrate structures subsequent to the structure shown in(i.e., after step).

Each of the trenchesextends through the dielectric layerand the CESLto expose a corresponding one of the source/drain portionsA. In some embodiments, stepincludes (i) forming a patterned mask layer (not shown) to cover a top surface of the structure shown in, the patterned mask layer being a patterned photoresist or a patterned hard mask and having openings in positions respectively corresponding to the source/drain portionsA, (ii) etching the dielectric layerand the CESLthrough the openings of the patterned mask layer using dry etching, wet etching, other suitable processes, or combinations thereof, to form the trenchesuntil the source/drain portionsA are exposed from the trenches, and (iii) removing the patterned mask layer. Other suitable processes for forming the trenchesare within the contemplated scope of the present disclosure.

Referring toand the example illustrated in, the method proceeds to step, where a silicide layeris formed over the dielectric layerand in the trenchescovering a trench sidewall and a trench bottom of each of the trenches. The silicide layermay include silicon and at least one metallic element, for example, but not limited to, titanium (Ti), nickel (Ni), other suitable materials, or combinations thereof. Other suitable materials for forming the silicide layerare within the contemplated scope of the present disclosure. The silicide layermay be formed by any suitable processes. In some embodiments, the silicide layerformed on the trench bottom may have a thickness larger than that of the silicide layerformed on the trench sidewall. This is to facilitate stepto be performed subsequently, and will be discussed hereinafter.

Referring toand the example illustrated in, the method proceeds to step, where a first metallic layer, which is a metal-including layer, is formed over the semiconductor substratein the trenchesand covers the silicide layer. The first metallic layerincludes at least one of tungsten, tungsten nitride, aluminum oxide, titanium nitride, aluminum, tantalum nitride, cobalt, titanium, tantalum, nickel, molybdenum, copper, and the like. Other suitable materials for forming the first metallic layerare within the contemplated scope of the present disclosure. The first metallic layermay be formed by, for instance, PVD. Other suitable processes for forming the first metallic layerare within the contemplated scope of the present disclosure. It is noted that the first metallic layerhas a hydrophilic surface, which in some cases, includes an oxide or hydroxide of the metal present therein. In some embodiments, the first metallic layerformed on the trench bottom may have a thickness larger than that of the first metallic layer formed on the trench sidewall. This is to facilitate stepto be performed subsequently, and will be discussed hereinafter.

Referring toand the example illustrated in, the method proceeds to step, where the first metallic layeris subjected to a modification process. In some embodiments, the modification process is performed by forming an amphiphilic polymer layerover the first metallic layer. Stepmay include the following substeps: (i) forming a solution including an amphiphilic polymer material; (ii) applying the solution over the first metallic layer; and (iii) performing a drying process so as to obtain the amphiphilic polymer layerincluding the amphiphilic polymer material. In substep (i), the solution may be formed by dissolving the amphiphilic polymer material in a suitable organic solvent (determined according to practical needs). In substep (ii), in some embodiments, the solution may be applied by, for instance, evenly spraying over the first metallic layerat a suitable temperature, for instance but not limited to, room temperature (about 25° C. to about 40° C.). In substep (iii), the drying process may include, but not limited to, air drying, thereby forming the amphiphilic polymer layer. The formation of the amphiphilic polymer layergenerally does not require any heating (may be adjusted according to practical needs), and makes it easy to modify the first metallic layer. Other suitable processes for forming the amphiphilic polymer layerare within the contemplated scope of the present disclosure.

In some embodiments, the amphiphilic polymer material for forming the amphiphilic polymer layerincludes a polymer backbone, hydrophobic groupsattached to the polymer backbone, and hydrophilic groupsattached to the polymer backbone(see). A number of the hydrophobic groupsis greater than that of the hydrophilic groups. The amphiphilic polymer layermay be present as a self-assembled monolayer (SAM).

In some embodiments, the hydrophobic groupseach independently is a saturated alkyl, a phenyl, or the likes. For hydrophobic groupsthat are saturated alkyl, a number of carbon atom may range from one to three. That is, each of the hydrophobic groupsmay be a short saturated alkyl chain. Such short alkyl chain may avoid undesired aggregation of the alkyl chain as occurred in long alkyl chain. In addition, the saturated alkyl is relatively unreactive compared to unsaturated hydrocarbons such as alkenyl or alkynl, which is conducive to avoiding reactions with any other species. Example of the phenyl may include, but not limited to, benzene, which is also considered as an unreactive species. Other suitable materials for forming the hydrophobic groupsare within the contemplated scope of the present disclosure. The hydrophobic groupsmay be bonded to other species by van Der Waals force. In some embodiments, the hydrophobic groupsare evenly distributed along the polymer backbone.

In some embodiments, the hydrophilic groupseach independently is hydroxyl, carboxyl, amide or amino. Other suitable materials for forming the hydrophilic groupsare within the contemplated scope of the present disclosure. The hydrophilic groupsmay be bonded to other species by hydrogen bond.

Referring toand the example illustrated in, the method proceeds to step, where a hydrophobic polymer layeris formed over the amphiphilic polymer layer.

In some embodiments, the hydrophobic polymer layerincludes a bottom anti-reflective coating (BARC) material. BARC is a porous polymer prepared from, for example, but not limited to, styrene monomers and epoxy cross-linkers, and is relatively hydrophobic compared to the first metallic layer. Other suitable materials for forming the hydrophobic polymer layerare within the contemplated scope of the present disclosure.

Referring toand the example illustrated in, the method proceeds to step, where an upper portion of the hydrophobic polymer layeris removed, and a remaining lower portion of the hydrophobic polymer layeris denoted by the numeral′. The hydrophobic polymer layer′ covers a second portionof the first metallic layer, leaving a first portionof the first metallic layerbeing exposed from the hydrophobic polymer layer. In addition, the silicide layerhas a first portionlocated beneath the first portionof the first metallic layer, and a second portionlocated beneath the second portionof the first metallic layer. The upper portion of the hydrophobic polymer layermay be removed by, for instance, an etching process using any suitable etchants which have a high etch selectivity for the hydrophobic polymer layerrelative to the first metallic layer. Other suitable processes for removing the hydrophobic polymer layerare within the contemplated scope of the present disclosure.

is a schematic diagram demonstrating the role of the amphiphilic polymer layerformed between the hydrophobic polymer layer′ and the first metallic layer. A surface of the amphiphilic polymer layerthat confronts the first metallic layeris hydrophilic, and the hydrophilic groupsof the amphiphilic polymer layermay form hydrogen bond with the metal oxide and/—or metal hydroxide, or the likes located on the hydrophilic surface of first metallic layer, leaving the hydrophobic groupsof the amphiphilic polymer layeropposite to the first metallic layer. As such, the amphiphilic polymer layerpermits a hydrophobic surface to be formed over the first metallic layer. In addition, a surface of the amphiphilic polymer layerthat confronts the hydrophobic polymer layer′ is hydrophobic, and the hydrophobic groupsof the amphiphilic polymer layermay be bonded to the styrene molecules by van der Waal force in the case of the hydrophobic polymer layer′ being made of BARC. As such, the amphiphilic polymer layeris capable of simultaneously bonding to both the hydrophobic polymer layer′ and the first metallic layer, thus enhancing a bonding force between the first metallic layerand the hydrophobic polymer layer′.

Referring toand the examples illustrated in, the method proceeds to step, where the first portionof the first metallic layerand the first portionof the silicide layerare removed, leaving the second portionof the first metallic layerand the second portionof the silicide layer. The second portionof the first metallic layerhas a sidewall regionB located on the trench sidewall, and a bottom regionA located on the trench bottom. The second portionof the silicide layerhas a sidewall regionB located on the trench sidewall, and a bottom regionA located on the trench bottom.

In some embodiments, the removal of the first portions,of the first metallic layerand the silicide layeris performed by wet etching using any suitable wet etchant which has a high etching selectivity for the first metallic layerand the silicide layerrelative to the other elements, such as the dielectric layer. Stepalso aims to retain the second portionof the first metallic layer, however, considering the hydrophobic polymer layer′ being a porous layer, the wet etchant may pass through the hydrophobic polymer layer′ and reach the second portionof the first metallic layer. In the case of omitting the amphiphilic polymer layer, the wet etchant may unintentionally etch away the second portions,of the first metallic layerand the silicide layer. Referring to, by including the amphiphilic polymer layer, the wet etchant (denoted by the numeral) will first reach the amphiphilic polymer layerafter passing through the hydrophobic polymer layer′. Since the surface of the amphiphilic polymer layerthat confronts the hydrophobic polymer layer′ is hydrophobic, the amphiphilic polymer layermay serve as a waterproof layer to hinder, or slow down, the wet etchantsfrom reaching and undesirably damaging the second portionof the first metallic layer. That is, the first metallic layercovered by the amphiphilic polymer layer, i.e., the modified first metallic layer, exhibits improved chemical resistance to wet etchants. For instance, in a peeling test to evaluate a resisting time period for the first metallic layerto be observed with bubble defect when a wet etchant (for example, an etchant for a standard clean or a RCA clean) is applied thereon (indicating that the wet etchant penetrates through the hydrophobic polymer layer′ and damages the first metallic layer), a sample that includes the amphiphilic polymer layerbetween the first metallic layerand the hydrophobic polymer layer′ may have a resisting time period much longer than a sample without the amphiphilic polymer layer. For example, but not limited to, the resisting time period of the sample with the amphiphilic polymer layermay be approximately 1.5 times to 2.5 times of that of the sample without the amphiphilic polymer layer.

Referring toand the example illustrated in, the method proceeds to step, where the hydrophobic polymer layer′ is removed by, for example but not limited to, an ashing process. Other suitable processes for removing the hydrophobic polymer layer′ are within the contemplated scope of the present disclosure.

Considering that stepaims to remove the first portion, and to retain the second portionof the first metallic layer, an experiment is performed to evaluate film loss of the first metallic layer.is a graph showing film loss of the bottom regionA of the first metallic layerwith and without inclusion of the amphiphilic polymer layerin accordance with some embodiments of the present disclosure. Film loss refers to a thickness of the bottom regionA of the first metallic layerthat is etched away by the wet etchant used in step. The results show that the film loss of the bottom regionA after stepmay be effectively reduced with the presence of the amphiphilic polymer layer. This suggests that the amphiphilic polymer layermay avoid or slow down penetration of the wet etchant to the second portionof the first metallic layer, and is beneficial to permit the bottom regionA of the first metallic layerto remain intact, so as to facilitate subsequent steps.

Referring toand the examples illustrated in, the method proceeds to step, where the second portions,of the first metallic layerand the silicide layerare partially removed such that the sidewall regionB of the first metallic layerand the sidewall regionB of the silicide layerare removed while the bottom regionA of the first metallic layerand the bottom regionA of the silicide layerremain.

In some embodiments, stepmay be performed by any suitable etching process, such as an isotropic etching process which has substantially same etching selectivity and etching rate over each of the first metallic layerand the silicide layerformed on the trench bottom, i.e., the bottom regionsA,A, and on the trench sidewall, i.e., the sidewall regionsB,B. In such case, by forming the bottom regionsA,A thicker than the sidewall regionsB,B, the sidewall regionsB,B may be completely removed in step, while a sufficient thickness of each of the bottom regionsA,A may be retained, so as to facilitate stepto be performed subsequently. Any other suitable processes for removing the sidewall regionB of the first metallic layerand the sidewall regionB of the silicide layerare within the contemplated scope of the present disclosure.

Referring toand the example illustrated in, the method proceeds to step, where a second metallic layeris formed on the remaining bottom regionA of the first metallic layer.

Stepmay include sub-steps of: (i) filling a second metallic material in the trenchby, for example, but not limited to, a CVD process, or any other suitable processes, and (ii) planarizing (by e.g., CMP) the second metal-including material to remove an excess thereof, thereby obtaining the second metallic layer. The second metallic material is used to form the second metallic layer, and may include, for example, tungsten. Other suitable materials and processing for forming the second metallic layerare within the contemplated scope of the present disclosure.

It is noted that in some embodiments, in sub-step (i), the second metallic material (made of, e.g., tungsten) growing on merely the bottom regionA of the first metallic layer(made of, e.g., another form of tungsten) has improved growth performance than directly growing on both the sidewall regionB and the bottom regionA, and is beneficial for obtaining a semiconductor device with improved electrical properties.

In some embodiments, the second metallic layermay serve as a “metal-to-device (MD) contact”, i.e., contact to conductive region of the semiconductor device such as the source/drain portions.

It should be noted that some steps in the method may be modified, replaced, or eliminated without departure from the spirit and scope of the present disclosure, and those steps may not be in the order mentioned above. In alternative embodiments, other suitable methods may also be applied for forming the semiconductor device.

For example, step, which involves modifying the first metallic layer (i.e., metal-including layer) by forming an amphiphilic polymer layerthereon, as mentioned in the exemplary embodiment above, permits the metal-including layerto have improved adhesion with the hydrophobic polymer layerincluding, e.g., BARC, and may also be applied in any other suitable manufacturing methods of semiconductor devices involving application of the hydrophobic polymer layer, e.g., but not limited to, BARC, over the metal-including layer.is a schematic diagram illustrating an intermediate step of another exemplary embodiment of a method for manufacturing another semiconductor device, e.g., a GAA nanosheet FET, in which a step of patterning a portion of a metal-including layeris shown, and which involves the formation of the amphiphilic polymer layerbetween the metal-including layerand the hydrophobic polymer layer.

As shown in, a first nanounitis formed on a first regionA of a semiconductor substrate, and a second nanounitis formed on a second regionB of the semiconductor substrate. The metal-including layeris formed over the semiconductor substrate, and includes a first portioncovering the first nanounit, and a second portioncovering the second nanounit. In some embodiments, the first nanounitis a portion of an n-type device, and the second nanounitis a portion of a p-type device, or vice versa. Each of the first and second nanounits,includes a plurality of nanosheetswhich are spaced apart from each other, a plurality of metal plugswhich are disposed to alternate with the nanosheets, a plurality of first gate dielectric portionswhich respectively surround the nanosheetsto separate the nanosheetsfrom the metal plugs, and a second gate dielectric portiondisposed between each of first and second portions,of the metal-including layerand a corresponding one of the first and second regionsA,B of the semiconductor substrate. In some embodiments, the metal-including layermay serve as a work function metal for the second nanouniton the second regionB of the semiconductor substrate, and may include titanium nitride (TiN), tungsten nitride (WN), or combinations thereof. In some embodiments, each of the nanosheetsincludes a semiconductor material, such as silicon, and the first gate dielectric portionsand the second gate dielectric portioneach may include a material similar to that for the gate dielectricas described above. The metal plugsmay include any suitable material serving as a work function metal. In some embodiments, an interfacial layer (IL)is formed between each of the nanosheetsand a corresponding one of the first gate dielectric portions, and may include, for example, but not limited to, silicon oxide. In addition, a plurality of isolation portionsare disposed on the semiconductor substrateto alternate with the first and second regionsA,B, and an additional ILis formed on each of the first and second regionsA,B to interconnect the isolations portionsat two opposite sides of a corresponding one of the first and second regionsA,B. The semiconductor substrate(including the first and second regionsA,B) and the isolation portionsshown inmay include materials similar to those for the semiconductor substrateand the isolation portionsshown in. Other suitable materials for forming each of the first and second nanounits,and the metal-including layerare within the contemplated scope of the present disclosure.

The metal-including layeris modified by forming an amphiphilic polymer layerover the metal-including layerusing an amphiphilic polymer material. Details of the formation of the amphiphilic polymer layeris similar to that of stepas described in the exemplary embodiment (i.e., for forming the FinFET), and are omitted herein for the sake of brevity.

A hydrophobic polymer layeris formed to cover the second portionof the metal-including layer, leaving the first portionexposed from the hydrophobic polymer layer. The hydrophobic polymer layermay be similar to that described in step, and may include a BARC material. The hydrophobic polymer layerand a hard mask layerformed thereon may be formed by (i) forming a hydrophobic polymer material (not shown, for forming the hydrophobic polymer layer) over the semiconductor substrateto cover the first and second nanounits,, (ii) forming a hard mask material (not shown, for forming the hard mask layer) on the hydrophobic polymer material, (iii) forming a patterned photoresist layer (not shown) on the hard mask material to expose the hard mask material on the first regionA of the semiconductor substrate, (iv) partially removing the hydrophobic polymer material and the hard mask material exposed from the patterned photoresist layer so that the hydrophobic polymer material is patterned into the hydrophobic polymer layerand the hard mask material is patterned into the hard mask layer, and (v) removing the patterned photoresist layer. The patterned hard mask layermay include aluminum oxide. Other suitable materials and processes for forming the hydrophobic polymer layerand/or the hard mask layerare within the contemplated scope of the present disclosure.

The first portionof the metal-including layeris removed by, for example, but not limited to, wet etching using any suitable wet etchants. This step aims to remove merely the first portionof the metal-including layer, and to retain the second portion. In the case of omitting the step of modifying the metal-including layer, the wet etchant may pass through the hydrophobic polymer layerand undesirably damaging the second portion. In the case of including the step of modifying the metal-including layer, the hydrophobic polymer layermay have improved adhesion to the metal-including layer, while the amphiphilic polymer layerprovides a hydrophobic surface to hinder or slow down passage of the wet etchant.

Apart from the application in improving adhesion between a metal-including layer and a hydrophobic polymer layer (e.g., BARC) as described in the present disclosure, such modification of the metal-including layer by forming the amphiphilic polymer layer thereon may also be applied in many other aspects, such as metal surface modification, or selective protection of water sensitive metal films.

The embodiments of the present disclosure have the following advantageous features. By virtue of including the step of modifying the metal-including layer by forming an amphiphilic polymer layer thereon, adhesion between the metal-including layer and the hydrophobic polymer layer is effectively improved. In addition, such modification permits a more hydrophobic surface to be formed over the metal-including layer prior to the modification, so as to have an improved chemical resistance to wet etchants.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes forming a metal-including layer over a semiconductor substrate; forming a hydrophobic polymer layer over the metal-including layer; and forming an amphiphilic polymer layer between the metal-including layer and the hydrophobic polymer layer so as to enhance a bonding force therebetween.