Die Crack Detection System

This application claims benefit to the filing date of prior U.S. Patent Application No. 63/644,255, filed on 2024 May 8 (the “Provisional Application”), the contents of which are hereby incorporated by reference as if entirely set forth herein. In the event of conflict between the meaning of a term used in this document and the same or a similar term used in the Provisional Application or in another document incorporated herein by reference, the meaning associated with this document shall control.

During the process in which a silicon wafer is sliced to produce individual integrated circuit dies, cracks can occur in the dies. While large cracks can be detected using known techniques at the time of manufacture, existing quality control methods often do not detect small cracks that may occur near the edges of a die. For example, a small crack located near the edge of a die that does not affect logic circuitry in the die will not be detected by conventional automated test equipment (“ATE”) at the time of manufacture because the tests run by such equipment only cover functional correctness of the logic circuitry of the die.

Moreover, after a die has been packaged and has been embedded in a product that is deployed in the field, repeated heating and cooling of the die during operation of the product can cause a small crack to increase in size. Eventually, the crack may corrupt logic circuitry on the die and cause it to fail.

A need therefore exists for techniques that can be used to detect die cracks both at the time of manufacture and also during the life of a product that has been deployed in the field.

This disclosure describes multiple embodiments by way of example and illustration. It is intended that characteristics and features of all described embodiments may be combined in any manner consistent with the teachings, suggestions, and objectives contained herein. Thus, phrases such as “in an embodiment,” “in one embodiment,” and the like, when used to describe embodiments in a particular context, are not intended to limit the described characteristics or features only to the embodiments appearing in that context.

The phrases “based on” or “based at least in part on” refer to one or more inputs that can be used directly or indirectly in making some determination or in performing some computation. Use of those phrases herein is not intended to foreclose using additional or other inputs in making the described determination or in performing the described computation. Rather, determinations or computations so described may be based either solely on the referenced inputs or on those inputs as well as others.

The phrase “configured to” as used herein means that the referenced item, when operated, can perform the described function. In this sense, an item can be “configured to” perform a function even when the item is not operating and therefore is not currently performing the function. Use of the phrase “configured to” herein does not necessarily mean that the described item has been modified in some way relative to a previous state.

“Coupled” as used herein refers to a connection between items. Such a connection can be direct or can be indirect, such as through connections with other intermediate items.

Terms used herein such as “including,” “comprising,” and their variants, mean “including but not limited to.”

Articles of speech such as “a,” “an,” and “the” as used herein are intended to serve as singular as well as plural references except where the context clearly indicates otherwise. For example, articles of speech such as “a,” “an,” and “the,” when used in a claim or sentence subsequent to words such as “including,” “comprising,” or their variants, mean “one or more.”

is an oblique view of an example integrated circuit (“IC”) packagein accordance with embodiments. The package includes a substratehaving one or more integrated circuit dies mounted thereon, such as an integrated circuit die, and having a set of externally accessible conductors disposed on one or more sides thereof. At least some of the conductors are coupled to circuitry disposed on or inside the die. The package may be constructed using any of a variety of known packaging techniques, and the externally accessible conductors may be arranged on the package in any suitable fashion. For example, the conductors may be arranged in a pin grid array (“PGA”) fashion or in a ball grid array (“BGA”) fashion.

A first subsetof the externally accessible conductors is dedicated to Joint Test Action Group (“JTAG”) functionality and is therefore referred to herein as a JTAG port. A second subsetof the externally accessible conductors, distinct from the first subset, provides a data transfer port by means of which data unrelated to JTAG functionality may be communicated into or out of the integrated circuit package. In some embodiments, the data transfer port may comprise a Peripheral Component Interconnect Express (“PCIe”) port. In other embodiments, other types of data transfer ports may be used.

is a schematic view conceptually illustrating several components of die. The die includes a seal ring areaaround its peripheral edges and an elongate conductive trace. The elongate conductive trace may be disposed in a variety of locations on or within the die and may have any size and shape suitable to the application. In some embodiments, for example, the trace may have a width on the order of 0.08 micrometers and may have a length much longer than its width. In the embodiment shown, the elongate conductive trace is disposed adjacent to each of the four peripheral edges of the die near the seal ring area. In other embodiments, the elongate conductive trace may be disposed completely or partially within the seal ring area itself. In the illustrated embodiment, the elongate conductive trace forms a two-ended ring. Each of its two ends,is coupled to die crack test logic. The die crack test logic is, in turn, coupled to other in-package circuitryby one or more communication lines or buses.

In some embodiments, coaxial shielding may be added around the elongate conductive trace to reduce the coupling of electromagnetic interference noise onto the elongate conductor. Such shielding may be particularly beneficial, for example, for embodiments in which a digital signal is communicated through the elongate trace at a relatively high frequency. An example of such shielding is shown in the drawing and is illustrated in more detail atand, which are top and side views, respectively, of the portion of the elongate conductive trace enclosed by the dashed circle of.

In general, such coaxial shielding may constructed by providing one or more conductive ground traces on or in the die such that the ground traces are oriented coaxially with the elongate conductive trace but are separated from the trace by dielectric boundaries. By way of example,illustrates a left conductive traceand a right conductive trace. Each is oriented coaxially with elongate conductive trace, and each is coupled to an electrical ground as indicated atand. Dielectric boundaries,separate the left and right conductive ground traces from elongate conductive trace. By way of further example,illustrates an upper conductive traceand a lower conductive trace. Each is oriented coaxially with elongate conductive trace, and each is coupled to an electrical ground as indicated atand. Dielectric boundaries,separate the upper and lower conductive ground traces from elongate conductive trace. In other embodiments, other structures may be employed to achieve coaxial shielding if such shielding is desired.

In various embodiments, more than one elongate conductive trace may be implemented on different layers of a single integrated circuit die, with corresponding test logic, driving circuitry, data registers, control registers, and interfaces provided for each of the respective elongate test traces on the die.

is a block diagram schematically illustrating the die crack test logic ofin more detail. The die crack test logic is configured to perform a die crack test by applying an electrical test pattern to one end (e.g., end) of elongate conductive traceand by sensing an electrical response pattern at the other end (e.g., end) of the conductive trace. In general, the test pattern may comprise any electrical signal. In some embodiments, the test pattern may comprise a first binary sequence, such as any series of logical ones and zeroes. In the latter embodiments, the response pattern may comprise a second binary sequence.

The test pattern may be clocked through the elongate conductive trace at any suitable speed, taking into account an upper limit determined by the resistive-capacitive (“RC”) constant represented by the elongate conductive trace, and by employing one or more driver stages (to be further described below) to accommodate the RC load represented by the trace. The two binary sequences may be tested for equality and, if they are found to be equal, a result of the die crack test result may indicate that the no crack has been detected on the die. If, on the other hand, the test pattern and the response pattern are found to be not equal, then a die crack test result may indicate that a crack has been detected on the die.

In some embodiments, the die crack test logic itself may be configured to compare the test pattern with the response pattern and to thereby determine whether a crack has been detected on the die. In other embodiments, the die crack test logic may simply communicate the response pattern to other logic located elsewhere in the integrated circuit package or in a host system, and the other logic may make the determination as to whether a crack has been detected on the die. In any such embodiments, a die crack test result may include the response pattern, or may simply include a pass/fail result, or may include both a pass/fail result as well as the response pattern.

In the illustrated embodiment, test logicis configured to transmit the test pattern via a transmit pathdisposed between the test logic and the first endof the elongate conductive trace, and to receive the response pattern via a receive pathdisposed between the test logic and the second endof the elongate conductive trace. In some embodiments, the die crack test logic may also include a loopback mode (to be further described below). In such embodiments, when the loopback mode is active, test logicreceives the response pattern via a loopback paththat bypasses the elongate conductive trace. The loopback mode may be used, for example, during tests whose purpose is to verify correct behavior of the die crack detection system itself.

Test logicis communicatively coupled to JTAG logicand to a set of data and/or control registers, as shown. The JTAG logic provides a JTAG mode data out signaland a JTAG mode loopback enable signalto the test logic, and receives the response patternfrom the test logic at a JTAG mode response pattern input. The data/control registers provide a field test mode data out signal, a field test mode loopback enable signal, and a JTAG override signalto the test logic. The data/control register receive the response pattern from the test logic at a field test mode response pattern input. The test logic, in turn, provides a loopback enable signalto the receive path.

By way of example, the JTAG logic may include one or more JTAG data registers and one or more JTAG control registers. Similarly, data/control register logicmay include one or more field test data registers and one or more field test control registers. By way of example, the JTAG data registers may include a JTAG test pattern register configured to supply a test pattern to the test logic via JTAG mode data out signal, and may include a JTAG response pattern register configured to receive a response pattern via JTAG response pattern input. The JTAG control registers may include a JTAG control register configured to supply a value to JTAG mode loopback enable signal. Similarly, the field test data registers may include a first field test data register configured to supply a test pattern to the test logic via field test mode data out signal, and may include a second field test data register configured to receive a test pattern via response pattern input. The field test control registers may include a field test control register configured to supply a value to field test mode loopback enable signal. A further control register may be configured to supply a value to JTAG override signal. Any such registers may be accessed via one or more address/data buses coupled to the data/control register logic and to the JTAG logic.

In operation, an entity such as a hardware test controller or software executing in a host computer system may write a test pattern into one or more of the data registers and may read a response pattern from another one or more of the data registers. Such an entity may also write control values into any one or more of the control registers in the same manner. In some embodiments, the data registers may comprise one or more shift registers so that, for example, the contents of a test pattern register may be clocked onto the transmit path, and the state of the receive path may be clocked into a response pattern register. Similarly, any of the aforementioned entities may write control information, such as a JTAG override bit and/or a loopback enable bit, into one or more of the control registers as appropriate to configure the operation of the die crack detection system.

is a block diagram schematically illustrating an example embodiment of the test logic and of the transmit, receive, and loopback paths ofin more detail. As can be seen in the drawing, the test logic includes a test pattern multiplexerand a loopback enable multiplexer, while the receive path includes a receive path multiplexer. The data output of the test pattern multiplexer is coupled to the first endof the elongate conductive trace via several buffer/driver stages/. The data output of the receive path multiplexer provides a response pattern signalvia several buffer/driver stages/. In various embodiments, different numbers of buffer/driver stages may be used than are shown in the illustrated embodiment. Note that, in the illustrated embodiment, the same number of buffer/driver stages are included in the receive path as are included in the transmit path. In addition, a driver stageis included in loopback pathsuch that, when loopback mode is enabled, the bypassed transmit path includes the same number of buffer/driver stages as does the receive path. Note also that, in the illustrated embodiment, several of the driver stages are logical inverters, and the same number of logical inverters are included in the receive path as are included in transmit path and in the loopback path. In other embodiments, other numbers and types of driver stages may be used.

The test pattern multiplexer and the loopback enable multiplexer both have their select inputs coupled to JTAG override signal. Accordingly, when the JTAG override signal is not asserted, the field test mode data out signal provides the content for the transmit path, and the field test mode loopback enable signal determines the state of loopback enable signal. When the JTAG override signal is asserted, however, JTAG mode data out signalprovides the content for the transmit path, and the JTAG mode loopback enable signal determines the state of loopback enable signal. In this sense, the JTAG override signal serves as a manufacturing test mode enable signal.

The select input of the receive path multiplexer is coupled to loopback enable signal. Accordingly, when the loopback enable signal is not asserted, the content of the receive path is provided by the second endof the elongate conductive trace. When the loopback enable signal is asserted, however, the content of the receive path is provided by loopback path, which follows the state of the transmit path via a tapinto the transmit path located upstream of the first endof the elongate conductive trace.

In some embodiments, a static discharge protection diodemay be coupled between the second endof the elongate conductive trace and an electrical ground node, as shown. The breakdown voltage of the diode may be chosen such that the diode does not conduct when the voltage levels at nodeare within expected operational limits, but does conduct when the voltage on the node exceeds such limits. As a non-limiting example, a breakdown voltage on the order of 5V may be chosen in embodiments for which Vdd and logic levels are expected to be lower than 5V. In this way, a static discharge from the elongate conductive trace may be safely shunted away from the data input of the receive path multiplexer, thus protecting the multiplexer from damage.

is a block diagram schematically illustrating an example die crack detection systemthat includes a host computer systemand the integrated circuit packageof, in accordance with some embodiments. The host computer system may take a variety of forms. In some embodiments (for example, in a manufacturing test environment), the host computer may correspond to an ATE platform. In other embodiments (for example, in field environments), the host computer may correspond to a controller onboard a product that has been released from manufacture and is operating in the field. An example of the latter class of embodiments is a vehicle in which integrated circuit packageis mounted to perform a control function in the vehicle and in which the host computer system corresponds to a primary control computer onboard the vehicle.

In any such embodiments, the host computer system includes a central processing unit (“CPU”), a memory controller, an input/output (“I/O”) controller, and a memory. The CPU is coupled to the memory controller and to the I/O controller, is able to write and read data to and from the memory via the memory controller, and is able to write and read data to and from the integrated circuit package via the I/O controller.

The JTAG logic within die crack test logicis coupled to JTAG portvia a hardware test controllerand a JTAG interface. Similarly, the data and control registers within die crack test logicare coupled to data transfer portvia the hardware test controller and a data transfer interface. By way of example, the high speed interface, the JTAG interface, and the various controllers may be implemented as described in Jagannadha, et al., “Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms,” 2019 IEEE 37VLSI Test Symposium (IEEE 2019), the contents of which are hereby incorporated by reference as if entirely set forth herein. In other embodiments, other implementations of those components may be used.

The integrated circuit package also includes functional logic, which is distinct from die crack test logic. The functional logic is coupled to the data transfer port (via data transfer interface) and to the JTAG port (via JTAG interface) and may be coupled to the hardware test controller also. The functional logic is both physically and conceptually distinct from the die crack test logic. Whereas the die crack test logic exists to verify the integrity of the integrated package itself, the functional logic exists to perform the operations for which the package was intended in the context of its field application—e.g., to control the operations of a subsystem onboard a vehicle. Thus, as will be further described below, while the die crack test logic is configured to communicate test-related data through one or the other of the JTAG port or the data transfer port of the IC package, the functional logic is configured to communicate non-test data through the data transfer port of the IC package. An example of such non-test data would be data related to the subsystem of the vehicle that the IC package is intended to control while the vehicle is in operation.

In the illustrated embodiment, a die crack test resultis communicated from the IC package to the host computer system, either via the JTAG port or via the data transfer port, and is stored at a predetermined location in the memory of the host computer system. This may be accomplished, for example, by means of a direct memory access (“DMA”) transaction initiated by the IC package.

In some embodiments, the test pattern used during the die crack test may be permanently stored or otherwise configured within the IC package itself. In other embodiments, the IC package may retrieve the test pattern to be used during the die crack test from the memory of the host computer system prior to performing the die crack test. In such embodiments, a test pattern may be stored by the host computer system at a predetermined location within its memory for this purpose, as indicated at.

In various embodiments, the IC package may include one or more fuse elementsoperable to enable or disable JTAG functionality in the package. The fuse elements may be placed in a first state when the IC package is being tested in a manufacturing environment so that the JTAG port and the JTAG functionality in the device are enabled and are accessible. Once manufacturing test has been completed, the fuse elements may be placed in a second state in which the JTAG port and the JTAG functionality in the device are disabled and are inaccessible. In such embodiments, once the IC package has been deployed in a field application, the JTAG port of the IC package would no longer be used.

Finally, a boot processormay also be included in the IC package. As will be further described below, the boot processor may be configured to coordinate the activities of the subsystems within the IC package during power on so as to place them in an intended operating state after initial power-on self testing has been completed within the device.

is a flow diagram illustrating example functionality of IC packagein the context of the die crack detection system of. The IC package is configured to operate in at least a manufacturing test mode or in a field test mode. The manufacturing test mode may be used, for example, primarily in a pre-release time frame during which the functional correctness and the physical integrity of the IC package are verified and after which the package may be released from manufacture and deployed in a field application, provided the unit has passed its functional and physical testing. The functionality of the IC package when in manufacturing mode may include, for example, at least its JTAG functionality, but may also include other test-related functionality. The field test mode may be used primarily in a post-release time frame during which the IC package is deployed in a field application.

In some embodiments, the host system may interact with the packaged integrated circuit die as described, for example, in Yilmaz, et al., “NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links,” IEEE Design & Test, vol. 40, no. 4, pp. 25-33 (IEEE 2023), the contents of which are hereby incorporated by reference as if entirely set forth herein. In other embodiments, other forms of interaction may be used.

Referring now to the diagram of, when the IC package is initially powered on at step, the device enters either the manufacturing test modeor the field test mode, depending on whether its JTAG port is enabled (decision) and, if so, whether its JTAG port is active (decision). If in the manufacturing test mode, the device will perform JTAG functions at step, which may include performing a die crack test as described above (step), and communicating a result of the die crack test to a host system via its JTAG port (step). If in the field test mode, however, the device will perform a die crack test as described above (step) and will communicate a result of the die crack test to the host system via its data transfer port (step). In embodiments in which the IC package itself is configured to interpret the response pattern as representing a passed or a failed test, the IC package may thereafter perform a fail safe action if a crack in the die has been detected (decisionand step). An example of such a fail safe operation performed by the IC package itself would be to power itself down or to disable its functional logic. But if it is determined that a crack in the die has not been detected, then the IC package may enter a function modein which the device begins performing the functions it is intended to perform in its field application.

is a block diagram schematically illustrating an example application of die crack detection systemin which IC packageis deployed in a vehicle, such as in an automobile. In the illustrated example, the vehicle includes a vehicle computer system, which in this context may be configured similarly to host computer systemand may perform the same functions as described above in relation to the host computer system of.

is a flow diagram illustrating example functionality of the vehicle and die crack detection system of. In the drawing, the functions of the vehicle computer system are illustrated vertically in the left-hand column, while the functions of the IC package are illustrated vertically in the right-hand column. Time proceeds downward in both columns.

At timesand, power is applied to the vehicle computer system and to the IC package, respectively. As the vehicle computer system boots and initializes systems (time), the IC package enters field test mode as described above (time). In embodiments in which a die crack test pattern is stored in the host computer system memory and is retrieved therefrom by the IC package as described above, the IC package may read the test pattern from the vehicle computer system memory at time, such as by means of a DMA transaction. The IC package may then perform a die crack test at timeand may write a result of the die crack test to the vehicle computer system memory, also as described above, at time.

At time, the vehicle computer system accesses the die crack test result from its memory and determines, based on the accessed result, whether or not the die crack test passed (decision). If the vehicle computer system determines that the die crack test passed, then it may enable normal vehicle operation (step). If, on the other hand, the vehicle computer system determines that the die crack test failed, then it may perform a fail safe action (step). A first example of a fail safe operation performed by the vehicle computer system would be to disable operation of the vehicle. A second example would be to indicate that an error has occurred, such as displaying a warning on a user interface of the vehicle and/or by recording the failure in a non-volatile vehicle datastore. In other embodiments, other fail safe operations may be performed by the vehicle computer system.

In embodiments in which the IC package is configured to determine internally whether the die crack test has passed or has failed (decision), the IC package may independently perform a fail safe operation of its own at, such as any of those described above. But if the IC package determines that the die crack test has passed, then it may enter its function mode at.

Multiple specific embodiments have been described above and in the appended claims. Such embodiments have been provided by way of example and illustration. Persons having skill in the art and having reference to this disclosure will perceive various utilitarian combinations, modifications and generalizations of the features and characteristics of the embodiments so described. For example, steps in methods described herein may generally be performed in any order, and some steps may be omitted, while other steps may be added, except where the context clearly indicates otherwise. Similarly, components in structures described herein may be arranged in different positions or locations, and some components may be omitted, while other components may be added, except where the context clearly indicates otherwise. The scope of the disclosure is intended to include all such combinations, modifications, and generalizations as well as their equivalents.