Test Method and Test Apparatus for Chip, Upper Computer, Chip, and Device

This application is a continuation of International Application No. PCT/CN2023/073352, filed on Jan. 20, 2023, the entire content of which is incorporated herein by reference.

The present application relates to the field of battery management technologies, and in particular, to a test method and test apparatus for a chip, an upper computer, a chip, and a device.

Energy conservation and emission reduction are the key to the sustainable development of the automobile industry. Electric vehicles, with their advantages of energy conservation and environmental protection, have emerged as an important component for the sustainable development in the automobile industry. For the electric vehicles, battery technology is also an important factor about their development.

In the field of battery management, various chips usually need to be used to sample a battery to collect various states of the battery. However, a chip used in the field of battery management often faces a scenario of hot-swapping or hot-plugging, and a more severe test is imposed on voltage withstanding performance of the chip. Therefore, a solution for effectively testing a chip is expected.

The present application is intended to resolve at least one of technical problems existing in the related art. Therefore, an objective of the present application is to provide a test method and test apparatus for a chip, and an upper computer, a chip and a device, so as to effectively test performance of the chip.

An example of a first aspect of the present application provides a test method for a chip, including: determining a configuration mode of a test circuit, where the test circuit includes at least one chip and at least one battery module, and the at least one chip is configured to be connected to the at least one battery module according to the configuration mode; connecting the at least one chip to the at least one battery module based on at least one working condition corresponding to the configuration mode; determining whether an operation termination condition is satisfied; and testing the performance of the at least one chip in response to determining that the operation termination condition is satisfied.

In the technical solution of this embodiment of the present application, a standard hot-plugging test device solution is provided, to standardize a hot-plugging test. In actual application, test differentiation between different chip manufacturers may be reduced, and a standardized and normalized chip test may be implemented.

In some embodiments, the test circuit further includes a switch matrix, the switch matrix is between the at least one chip and the at least one battery module, and the switch matrix is configured to connect the at least one chip to the at least one battery module according to the configuration mode; and the connecting the at least one chip to the at least one battery module includes: performing a closing operation used for closing at least two switches in the switch matrix.

According to such an embodiment, a chip test can be flexibly performed based on a switch matrix, a complex manual plugging process can be avoided, a required scenario and working condition can be flexibly simulated, and a hot-plugging function of an AFE can be tested accurately and quickly and closer to a realistic application situation.

In some embodiments, the at least one chip includes a first chip, the at least one battery module includes a first battery module, and the hot-plugging test bench requirements include a first configuration mode, where the first configuration mode indicates that the first chip is configured to be connected to corresponding switches of the switch matrix, to enable sampling channel lines of the first chip to be respectively connected to corresponding sampling leads of the first battery module when the corresponding switches are turned on.

According to such an embodiment, a normalized test based on a use scenario can be implemented. Particularly, a common chip use scenario can be simulated by enabling a configuration mode of a test circuit to be close to a chip use scenario, so that a relatively reliable test result can be obtained.

In some embodiments, in response to the determining that the test circuit is built according to a first configuration mode, the performing the closing operation includes: closing, if none of switches corresponding to remaining sampling channel lines other than a pair of sampling channel lines associated with a maximum battery potential difference in the first chip is closed, a pair of switches corresponding to the pair of sampling channel lines.

According to such an embodiment, for a simulated use scenario, a test can be further performed on a working condition occurring in an application scenario. Particularly, a test working condition corresponds to a configuration mode of the circuit, that is, a common working condition corresponding to a current use scenario of the chip can be simulated, thereby obtaining a realistic and reliable test result. According to such an embodiment, a maximum voltage difference on the chip may be caused by first closing switches of a pair of sampling channel lines associated with a maximum battery potential difference. Therefore, according to such an embodiment, a functional test of the chip is better facilitated by simulating a severest working condition, and a chip obtained after such a test still has satisfactory reliability even when dealing with an extreme working condition.

In some embodiments, in response to the determining that the test circuit is built according to a first configuration mode, the performing the closing operation further includes: randomly closing the switches corresponding to the remaining sampling channel lines in the first chip after the pair of switches corresponding to the pair of sampling channel lines are closed.

According to such an embodiment, for a simulated use scenario, a test can be further performed on a working condition occurring in an application scenario, and a common working condition corresponding to a use scenario of the chip is simulated, thereby obtaining a realistic and reliable test result. Specifically, after a severest working condition in which switches at two ends are first closed is simulated, remaining switches are randomly closed, so that not only a severe working condition can be covered, but also other common plug-in working conditions can be covered. In addition, a simulation result may be more realistic and comprehensive by using a logic of random closing.

In some embodiments, in response to the determining that the test circuit is built according to a first configuration mode, the performing the closing operation includes: randomly closing a switch corresponding to a sampling channel line of the first chip.

According to such an embodiment, for a simulated use scenario, by randomly closing switches corresponding to all sampling channel lines, a more common plugging working condition can be simulated, so that a simulation result is more realistic and comprehensive. In addition, a chip with a reliable function is obtained, thereby reducing possible faults in a use process of the chip.

In some embodiments, the at least one chip includes a first chip, the at least one battery module includes at least two battery modules connected in series, and the hot-plugging test bench requirements include a second configuration mode, where the second configuration mode indicates that the first chip is configured to be connected to corresponding switches of the switch matrix, to enable sampling channel lines of the first chip to be respectively connected to corresponding sampling leads of the at least two battery modules when the corresponding switches are turned on.

According to such an embodiment, a normalized test based on a use scenario can be implemented, to cover a scenario in which the quantity of sampling channel lines of the first chip is greater than the quantity of sampling leads of a single battery module or another scenario in which one chip may be used for sampling two or more batteries, thereby implementing realistic and reliable simulation and test of this common use scenario.

In some embodiments, in response to the determining that the test circuit is in a second configuration mode, the performing the closing operation includes: closing, if none of switches corresponding to sampling leads of a positive-electrode-side battery module of the at least two battery modules is closed, switches corresponding to sampling leads of remaining battery modules other than the positive-electrode-side battery module of the at least two battery modules; and closing a switch corresponding to a sampling lead associated with a highest battery potential of the positive-electrode-side battery module after the switches corresponding to the sampling leads of the remaining battery modules are closed for a first time delay.

According to such an embodiment, a working condition occurring in an application scenario can be further tested for a simulated use scenario, and a relatively severe working condition can be simulated for a scenario in which one chip is connected to two or more battery modules, thereby improving reliability of a chip obtained by using such a test method.

In some embodiments, the performing the closing operation further includes: randomly closing, after the switch corresponding to the sampling lead associated with the highest battery potential is closed, switches corresponding to remaining sampling leads other than the sampling lead associated with the highest battery potential of the positive-electrode-side battery module.

According to such an embodiment, for a simulated use scenario, a test can be further performed on a working condition occurring in an application scenario, and a simulation result may be more realistic and comprehensive by using a logic of random closing. Specifically, for the first simulation working condition of the second exemplary scenario, risks to be borne by sampling channel lines other than a sampling channel line that will bear a maximum voltage difference may be further simulated, so that risk test and evaluation can be performed on sampling channel lines and corresponding circuit parts of the chip, to obtain a more reliable test result.

In some embodiments, in response to the determining that the test circuit is in a second configuration mode, the performing the closing operation includes: closing, if none of switches corresponding to sampling leads of a negative-electrode-side battery module of the at least two battery modules is closed, switches corresponding to sampling leads of remaining battery modules other than the negative-electrode-side battery module of the at least two battery modules; and closing a switch corresponding to a sampling lead associated with a lowest battery potential of the negative-electrode-side battery module after the switches corresponding to the sampling leads of the remaining battery modules are closed for a second time delay.

According to such an embodiment, another relatively severe working condition can be simulated for a second scenario in which one chip is connected to two or more battery modules.

In some embodiments, the performing the closing operation further includes: randomly closing, after the switch corresponding to the sampling lead associated with the lowest battery potential is closed, switches corresponding to remaining sampling leads other than the sampling lead associated with the lowest battery potential of the negative-electrode-side battery module.

According to such an embodiment, for a simulated use scenario, a test can be further performed on a working condition occurring in an application scenario, and a simulation result may be more realistic and comprehensive by using a logic of random closing. Specifically, for the second simulation working condition of the second exemplary scenario, risks to be borne by sampling channel lines other than a sampling channel line that will bear a maximum voltage difference may be further simulated, to obtain a more reliable test result.

In some embodiments, the at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, and the obtaining a test circuit which is built according to hot-plugging test bench requirements includes determining that the test circuit is built according to a third configuration mode, where the third configuration mode indicates that the first chip and the second chip are configured to be connected to corresponding switches of the switch matrix, to enable the first chip and the second chip to be connected to corresponding sampling leads of the first battery module when the corresponding switches are turned on.

According to such an embodiment, a scenario in which the quantity of sampling channel lines of the first chip is less than the quantity of sampling leads of a single battery module or another scenario in which two or more chips may be used for sampling a single battery can be covered, thereby implementing realistic and reliable simulation and test of this common use scenario.

In some embodiments, a first sampling channel line of the first chip and a second sampling channel line of the second chip are configured to be connected to a first sampling lead and a second sampling lead of the first battery module that are adjacent to each other, a third sampling channel line of the first chip and a fourth sampling channel line of the second chip are configured to be connected to a third sampling lead and a fourth sampling lead of the first battery module that are associated with a maximum battery potential difference, and in response to the determining that the test circuit is built according to a third configuration mode, the performing the closing operation includes: closing switches corresponding to the first sampling channel line and the second sampling channel line if none of switches corresponding to remaining sampling channel lines of the first chip and the second chip other than the first sampling channel line and the second sampling channel line is closed; and closing a switch corresponding to the third sampling channel line and a switch corresponding to the fourth sampling channel line after the switches corresponding to the first sampling channel line and the second sampling channel line are closed for a third time delay.

According to such an embodiment, a test effect and reliability of a chip obtained through a test can be improved by simulating a severe scenario, and a chip obtained after such a test still has satisfactory reliability even when dealing with an extreme working condition.

In some embodiments, the performing the closing operation further includes: randomly closing switches corresponding to remaining sampling channel lines of the first chip and the second chip other than the first sampling channel line, the second sampling channel line, the third sampling channel line, and the fourth sampling channel line after the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed.

According to such an embodiment, for a simulated use scenario, a test can be further performed on a working condition occurring in an application scenario; and a simulation result may be more realistic and comprehensive by using a logic of random closing. In other words, for the first simulation working condition of the third exemplary scenario, risks to be borne by sampling channel lines other than a sampling channel line that will bear a maximum voltage difference may be further simulated, to fully test the tolerance of the chip.

In some embodiments, in response to the determining that the test circuit is built according to a third configuration mode, the performing the closing operation includes: randomly closing switches corresponding to sampling channel lines of the first chip and the second chip.

According to such an embodiment, in addition to the provided severest working condition, other working conditions that are more common in practice may be further simulated in a test. According to such an embodiment, other common plugging working conditions can be covered. In addition, a simulation result may be more realistic by using a logic of random closing, and therefore a reliable and comprehensive test result is obtained.

In some embodiments, a first sampling channel line of the first chip and a second sampling channel line of the second chip are configured to be connected to a first sampling lead and a second sampling lead of the first battery module that are adjacent to each other, a third sampling channel line of the first chip and a fourth sampling channel line of the second chip are configured to be connected to a third sampling lead and a fourth sampling lead of the first battery module that are associated with a maximum battery potential difference, and the third configuration mode further indicates that the first sampling channel line is electrically connected to the second sampling channel line.

According to such an embodiment, an exemplary scenario in which the chip is short-circuited in advance can be further considered, so that scenarios that the chip may face can be covered more comprehensively, thereby obtaining a reliable test result.

In some embodiments, in response to the determining that the test circuit is built according to a third configuration mode, the performing the closing operation includes: closing switches corresponding to sampling channel lines of the second chip if none of switches corresponding to sampling channel lines of the first chip is closed; and closing a switch corresponding to the third sampling channel line after the switches corresponding to the sampling channel lines of the second chip are closed for a third time delay.

According to such an embodiment, a severe working condition that can be withstood during hot-swapping when the chip is short-circuited can be simulated, so as to obtain a reliable test result.

In some embodiments, the performing the closing operation further includes: randomly closing switches corresponding to remaining sampling channel lines of the first chip other than the third sampling channel line after the switch corresponding to the third sampling channel line is closed.

According to such an embodiment, other common plugging working conditions and sampling channel lines can be covered, so that risk test and evaluation can be performed on sampling channel lines and corresponding circuit parts of the chip, to obtain a more reliable test result.

In some embodiments, the operation termination condition includes at least one of the following: a quantity of execution times of a closing operation for the at least one chip reaches a first threshold, or a quantity of execution times of a closing operation based on a particular configuration mode reaches a second threshold for the particular configuration mode.

According to such an embodiment, chip testing can be further normalized by defining a termination condition.

In some embodiments, the test method further includes in response to determining that an operation termination condition is not satisfied: performing a power-off operation on the at least one chip; discharging a capacitor in the at least one chip; and repeatedly performing the steps of performing a closing operation used for closing at least two switches in the switch matrix and testing performance of the at least one chip, where the operation termination condition includes at least one of the following: a quantity of execution times of a closing operation for the at least one chip reaches a first threshold, or a quantity of execution times for each working condition of the at least one working condition reaches a second threshold for the working condition.

According to such an embodiment, impact of capacitor charging can be reduced, thereby obtaining a more realistic test effect.

In some embodiments, the test method further includes: regulating, in response to that the step of determining that the at least one chip is connected to the at least one battery module is performed for the first time, a cell voltage of a battery in the at least one battery module to a specified value before the testing performance of the at least one chip. According to such an embodiment, stability of the test can be ensured.

In some embodiments, the testing performance of the at least one chip includes performing a supply voltage range test on the at least one chip.

An example of a second aspect of the present application provides a test apparatus for a chip, including: at least one battery module; a switch matrix; and an upper computer, where the upper computer is configured to control an operation on at least one switch in a switch matrix, the switch matrix is configured to connect at least one chip to at least one battery module, and the upper computer is configured to perform the method according to the embodiments of the present application.

In some embodiments, the test apparatus further includes at least one discharging unit, where the at least one discharging unit is configured to discharge a corresponding capacitor in the at least one chip when the at least one discharging unit is switched on.

According to such an embodiment, impact of capacitor charging can be reduced, thereby obtaining a more realistic test effect.