Gate in Panel Driving Circuit and Display Apparatus Having Thereof

This is a continuation of U.S. patent application Ser. No. 18/389,106, filed Nov. 13, 2023, and also claims priority to and the benefit of Republic of Korea Patent Application No. 10-2022-0187718, filed on Dec. 28, 2022, the contents of both of which are incorporated herein by reference in its entirety.

The present invention relates to a GIP circuit capable of driving two transistors with one gate electrode and adjusting a threshold voltage, and a display apparatus including the same.

Recently, as a display apparatus have become thinner, a Gate In Panel (GIP) driving unit in which a gate driving unit is embedded in a display panel has been proposed. The GIP driving unit includes an inverter unit which is a latch circuit and maintains the original value unless input is applied from the outside.

Meanwhile, recently, a structure in which an inverter unit is formed of a pMOS transistor having a polycrystalline semiconductor and an nMOS transistor having an oxide semiconductor has been proposed. However, since the inverter unit of this structure is formed of two transistors, there is a problem in that the area is increased by the two transistors and the threshold voltage is shifted due to deterioration of the nMOS transistor having the oxide semiconductor.

Accordingly, embodiments of the present disclosure are directed to a gate in panel driving circuit and a display apparatus having the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.

Additional features and aspects will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and attained by the structure particularly pointed out in the written description, or derivable therefrom, and the claims hereof as well as the appended drawings.

To achieve these and other aspects of the inventive concepts, as embodied and broadly described herein, a GIP circuit according to the present invention includes a substrate, a first semiconductor layer on the substrate, a gate electrode over the first semiconductor layer, a second semiconductor layer over the gate electrode, a gate control electrode over the second semiconductor layer, a gate control signal being applied to the gate control electrode, an insulating layer over the gate control electrode, and a first drain electrode, a second drain electrode, a first source electrode, and a second source electrode over the insulating layer.

The first semiconductor layer is formed of a polycrystalline semiconductor and the second semiconductor layer is formed of an oxide semiconductor.

The first semiconductor layer and the second semiconductor layer are respectively activated as a negative (−) input voltage and a positive (+) input voltage are applied to the gate electrode.

The first drain electrode is contacted with a drain region of the first semiconductor layer and the first source electrode is contacted with a source region of the first semiconductor layer.

The first source electrode is contacted with a source region of the first semiconductor layer and the second source electrode is contacted with a source region of the second semiconductor layer.

The first source electrode and the second source electrode are electrically connected over the insulating layer.

A gate control line is disposed over the insulating layer to supply the gate control signal to the gate control electrode, and the gate control signal is a voltage of opposite sign to a bias voltage applied to the second semiconductor layer.

A display apparatus according to the present invention comprise a display panel, a driving unit outside the display panel, and a GIP circuit in the driving unit.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed

Advantages and features of the present invention, and a method for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains. It is provided to inform the person of the scope of the present invention. The present invention is only defined by the scope of the claims.

Since the shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to the matters shown in the drawings. Throughout the specification, like elements may be referred to by like reference numerals. In addition, when describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When ‘including’, ‘having’, ‘consisting’, etc. mentioned in this specification are used, other parts may be added unless the expression ‘only’ is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting components, it should be interpreted as including a range of errors, even if there is no explicit description.

For example, when the positional relationship of two parts is described as ‘on’, ‘upper’, ‘lower’, ‘beside’, etc., the expression ‘directly’ or ‘directly’ is used Unless otherwise stated, one or more other parts may be positioned between the two parts.

Spatially relative terms “below”, “beneath”, “lower”, “above”, “upper”, etc. may be used to easily describe the correlation between one element or components and another element or components as shown in the drawings. In addition to the directions shown in the drawings, relative terms should be understood as terms that include different orientations of the element during use or operation. For example, when the element shown in the figure is turned over, the other element described as “beneath” may be placed “above” another element. Accordingly, the exemplary term “beneath” may include both directions above and below. Likewise, the exemplary terms “above” or “on” may include both directions above and below.

In the case of a description of a temporal relationship, for example, ‘immediately’ or ‘directly’ when a temporal relationship is described with ‘after’, ‘following’, ‘after’, ‘before’, etc. It may include cases that are not continuous unless the expression”

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of “at least one of the first, second, and third items” means a combination of all items that can be presented from two or more of the first, second and third items, as well as each of the first, second or third items.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

When adding reference numerals to components of each drawing describing embodiments of the present invention, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings.

In embodiments of the present invention, the source electrode and the drain electrode are merely distinguished for convenience of description, and the source electrode and the drain electrode may be interchanged. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. In addition, the source electrode of one embodiment may be a drain electrode in another embodiment, and the drain electrode of one embodiment may be a source electrode in another embodiment.

In some embodiments of the present invention, for convenience of description, a source region and a source electrode are distinguished and a drain region and a drain electrode are distinguished, but embodiments of the present invention are not limited thereto. The source region may be a source electrode, and the drain region may be a drain electrode. Also, the source region may be the drain electrode, and the drain region may be the source electrode.

Each of the features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and may be technically variously interlocked and driven by those skilled in the art, and each embodiment may be implemented independently of each other or together in a related relationship.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

is view showing a block diagram showing the display apparatusaccording to the present invention.

As shown in, the display apparatusincluding a display panel PNL and a driving unit for applying data of an input image to a pixel area AA of the display panel PNL.

The display panel PNL may includes various display panel such as an organic light emitting display panel, a liquid crystal display panel, a quantum dot display panel, a micro-LED display panel, and a min-LED display panel.

The display panel PNL includes a plurality of data lines D, a plurality of gate lines G arranged vertically to the plurality of data lines D, and a pixel area AA having a plurality of pixels in a matrix form which are defined by the plurality of data lines D and gate lines G.

The driving circuit of the display panel PNL includes a data driving circuit DDU for supplying data voltages to the plurality of data lines D, a gate driving circuit GDU for supplying sequentially gate signals synchronized with the data voltages to the plurality of gate lines G, and a timing controlling unit TCON.

At this time, the gate driving circuit GDU is a GIP (Gate In Panel) driving circuit DDU disposed around the pixel area AA of the display panel PNL to supply the gate signal via a plurality of gate lines D.

The timing controlling unit TCON transmits data of the input image received from an external host system to the data driving circuit DDU and the gate driving circuit GDU. The timing controlling unit TCON receives timing signals such as a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock which are synchronized with the input image from the external host system.

The timing controlling unit TCON generates various control signals for controlling operation timings of the data driving circuit GDU and the gate driving circuit GDU based on the input timing signal. That is, the timing controlling unit TCON generates a data driving control signal DDC for controlling the data driving circuit DDU and a gate driving control signal GDC for controlling the gate driving circuit GDU.

The timing controlling unit TCON may be disposed in the outside of the display panel PNL. Specifically, the timing controlling unit TCON is disposed on a pad unit such as a printed circuit board. The timing controlling unit TCON transmits the data driving control signal DDC to the data driving circuit DDU and transmits the gate driving control signal GDC to the gate driving circuit GDU from the outside of the display panel PNL.

The data driving circuit DDU receives data of the input image and a data driving control signal DDC from the timing controlling unit TCON. The data driving circuit DDU converts the data of the input image into a gamma compensation voltage by the data driving control signal DDC transmitted from the timing controlling unit TCON to generate a data voltage, and outputs the generated data voltage to a plurality of data lines D.

The data driving circuit DDU includes a plurality of source electrode driver ICs (Integrated Circuits). The source electrode drive IC is connected to the plurality of data lines D by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate driving circuit GDU includes a GIP driving circuit and a level shifter. The level shifter may be physically separated from the GIP driving circuit. The level shifter may be disposed outside the display panel PNL, for example, on the printed circuit board.

Although the gate driving circuit GDU is disposed in one side of the pixel area AA in the drawing, the gate driving circuit GDU may be disposed in both sides of the pixel area AA.

The voltage level of the gate driving control signal GDC transmitted from the timing controlling TCON is converted by the level shifter and then input to the gate driving circuit GDU. Since the signal input to the level shifter is a digital signal, the thin film transistors of the display panel PNL cannot be driven by this digital signal. Therefore, the level shifter shifts the voltage of each gate driving control signal GDC transmitted from the timing controlling TCON to the signal having the voltage swinging between the gate low voltage VGL and the gate high voltage VGH.

The gate high voltage VGH is set to the voltage higher than the threshold voltage of the transistor formed on the display panel PNL, and the gate low voltage VGL is set to the voltage lower than the threshold voltage of the transistor.

The gate driving circuit GDU may be formed on the substrate of the display panel PNL at the same time as the pixel area AA. That is, in the gate driving circuit GDU, the GIP driving circuit may be formed in the bezel area of the display panel PNL at the same time as the pixel area AA.

is the block diagram showing the relationship between a plurality of stages of the data driving circuit DDU including the GIP driving circuit and the control signal of the GIP driving circuit according to the present invention.

The data driving circuit DDU, that is, the GIP driving circuit includes a plurality of stages STto STn. Each of the stages STto STn outputs first to nth gate pulses Goutto Goutn, respectively. The gate pulses Goutto Goutn are applied to the gate lines of the display apparatus.

The GIP driving circuit is a shift resistor SR that receives the gate driving control signal GDC and sequentially outputs gate signals to the gate lines G, G, . . . Gn. That is, the shift register SR sequentially supplies the gate signal generated by the level shifter to the gate lines G, G, . . . Gn by the gate driving control signal GDC.

The gate driving control signal GDC includes a gate start pulse VST and a clock CLK related to a shift of the gate signal.