Method of Forming Protective Layer Utilized in Silicon Remove Process

This application is a continuation application of U.S. application Ser. No. 17/880,685, filed on Aug. 4, 2022. The content of the application is incorporated herein by reference.

The present invention relates to a method of forming a protective layer, and more particularly to a method of forming a protective layer utilized in removing a silicon substrate.

Wafer bonding is the act of attaching a device wafer to another device wafer or a handling wafer so that it can be processed.

Wafer bonding provides for the packaging of semiconductor devices at a wafer level and is employed in a variety of technologies including 3D-integrated circuits (IC), chip scale package (CSP) devices, and micro-electro-mechanical systems (MEMS). The advantages of using Wafer bonding include enhancing electrical properties, providing for increased density, reducing device sizes, reducing costs, and allowing for additional testing at wafer level.

Semiconductor wafer manufacturing utilizes very sophisticated wafer processing procedures and complicated manufacturing systems. In efforts to reduce the size of the semiconductor package, manufacturers have reduced component sizes including the thickness of the wafer. However, in a conventional process, when removing the thickness of a device wafer, a surface of another device wafer is damaged.

In view of this, the present invention provides a protective layer used in a removing process to prevent the surface damage.

A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

todepict a method of forming a protective layer utilized in a silicon remove process according to a preferred embodiment of the present invention.

As shown in, a first waferand a second waferare provided. The first waferincludes a first silicon substrateand a first device structure. The first silicon substratehas a first front sideand a first back side. The first front sideis opposed to the first back side. The first device structureis disposed on and contacts the first front sideof first silicon substrate. The first device structureincludes interconnect elements, dielectric layersand transistors (not shown).

Similarly, the second waferincludes a second silicon substrateand a second device structure. The second silicon substratehas a second front sideand a second back side. The second front sideis opposed to the second back side. The second device structureis disposed on and contacts the second front sideof the second silicon substrate. The second device structureincludes interconnect elements, dielectric layersand transistors (not shown). In another case, the first wafermay be a handling wafer made of silicon. At this point, the first back sideof the first silicon substrateand the second back sideof the second silicon substrateare exposed. More specifically speaking, the first back sideof the first silicon substrateand the second back sideof the second silicon substrateare not contacted by silicon nitride or silicon oxide.

Later, the first waferis bonded to the second wafer. The first waferand the second wafermay be bonded to each other by bonding a top surface of the first device structureto a top surface of the second device structure. For example, the interconnect elementof the first device structuremay be bonded to the interconnect elementof the second device structure. Metal-to-metal bonding (such as copper-to-copper bonding) may be used. In one embodiment, oxide-to-oxide bonding between the dielectric layerof the first device structureand the dielectric layerof the second device structuremay also be used.

As shown in, a first grind processis performed to thin vertically a first back sideof the first silicon substrate. The first grind processmay be performed by using a grinding wheel. As shown in, a first trim processis performed to thin laterally an edge of the first waferand an edge of the second device structure. For instance, the first trim processmay be performed by using an edge grinding process which includes using a grinder or any other tool that is capable of mechanically wearing away the edge of the first waferand the edge of the second device structurealong their circumferences.

As shown in, a silicon oxide layeris formed to cover the first wafer, the second front sideof the second silicon substrateand the edge of the second device structure. The silicon oxide layerconformally covers the contour of the first silicon substrate, the first device structure, the second device structureand the second front sideof the second silicon substrate. The silicon oxide layermay be tetraethoxysilane (TEOS) formed by a deposition process.

As shown in, the first waferand the second waferare flipped over. Next, a protective layeris formed conformally to cover the second back sideof the second silicon substrate. The protective layeris preferably silicon oxide or silicon nitride. If the protective layeris silicon oxide, a thickness of the protective layeris advantageously between 300 and 400 angstroms. If the protective layeris silicon nitride, a thickness of the protective layeris preferably between 400 and 700 angstroms. The protective layermay be formed by a deposition process, an oxidation process or a nitriding treatment.

As shown in, the first waferand the second waferare flipped back. Subsequently, a second grind processis performed to remove the silicon oxide layeron the first back sideof the first silicon substrateand to thin vertically the first back sideof the first silicon substrate. After the second grind process, the first silicon substratewhich remains preferably has a thickness about 15 μm.

As shown in, a silicon remove processis performed to remove only the first silicon substrate. In details, the silicon remove processis performed by using tetramethylammonium hydroxide (TMAH) as an etchant to remove the first silicon substrate. Because the edge of the first device structure, the edge of the second device structureare covered by the silicon oxide layer, and the second back sideand the sidewall of the second silicon substrateare covered by the protective layer, only the first back sideof the first silicon substrateis exposed in the TMAH. Therefore, only the first silicon substrateis removed. Now, a method of forming a protective layer utilized in a silicon remove process of the present invention is completed, and a bonded wafer structureis formed.

todepict a method of forming a deep via on a bonded wafer structure according to a preferred embodiment of the present invention, wherein elements which are substantially the same as those intoare denoted by the same reference numerals; an accompanying explanation is therefore omitted.

As show in, a planarization process such as a chemical mechanical planarization (CMP) processis performed to remove the protruded silicon oxide layerat the edge of the first device structure. After the CMP process, a second trim process (not shown) is performed optionally to remove the silicon oxide layeron the edge of the first device structureand on the edge of the second device structureand to thin laterally the first device structureand the second device structure. In this embodiment, the second trim process is omitted as an example.

As shown in, a dielectric layeris formed to cover the first device structure. Later, a deep viais formed to penetrate the dielectric layerand to be disposed in the dielectric layerof the first device structure. The deep viacontacts one of the interconnectof the first device structure. Then, a conductive padis formed on a surface of the dielectric layer, and the conductive padcontacts the deep via.

The step of forming the protective layercan be formed at different stages, as long as the protective layeris formed after the first trim processand before the silicon remove process. In the embodiment illustrated above, the protective layeris formed after forming the silicon oxide layerand before the second grind process. As shown in, based on the different process designs, the protective layercan be formed after the first trim processand before forming the silicon oxide layer. On the other hand, the protective layercan be formed after the second grind processand before the silicon remove process.

Conventionally, the protective layer is formed on the second wafer at the stage of a shallow trench isolation process. After the protective layer is formed, the second wafer is absorbed on an e-chuck in front end of line (FEOL) semiconductor fabrication processes. However, because the protective layer is absorbed on the e-chuck, the surface of the protective layer is damaged. Later, after bonding the first wafer to the second wafer followed by using TMAH to etch the first silicon substrate, the TMAH may contact the second silicon substrate through the damaged regions of the protective layer. Then, the surface of the second silicon substrate is deteriorated.

The protective layer of the present invention is formed after bonding the first wafer to the second wafer. Therefore, the protective layer will not be damaged during the FEOL. In this way, the second silicon substrate can maintained its integrity.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.