Method for Manufacturing Semiconductor Package and Semiconductor Package Manufactured by Using the Same

This application claims the benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0061383, filed on May 9, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

The present disclosure relates to a method for manufacturing a semiconductor package and a semiconductor package manufactured by using the same.

With development of electronic industry, a demand for high functionalization, high speed, and miniaturization of an electronic component is increasing. To correspond to such a trend, a method of stacking and mounting multiple semiconductor chips on one package wiring structure or a method of stacking a package on another package may be used.

Meanwhile, a highly integrated semiconductor package may have difficulty with regulating heat, and warpage may occur due to a thermal expansion rate difference occurring in a semiconductor manufacturing process or heat occurring inside the semiconductor package. A stiffener may prevent the warpage of the semiconductor package. A heat slug may be used to regulate the heat of the semiconductor package by dissipating heat from the semiconductor package. Meanwhile, the heat slug which is disposed on a semiconductor chip may be effective in warpage prevention similarly to the stiffener. In addition, when other types of heat regulation is used in combination with a heat slug or a stiffener, the stiffener may be more effective in the heat dissipation when compared to the heat slug. For example, in a case of heat regulation by natural convection, the heat slug may be effective in the heat dissipation. In a case of heat regulation by forced convection such as heat regulation through a fan or liquid immersion cooling, the stiffener may be more effective in the heat dissipation than the heat slug.

An aspect of the present disclosure provides a method of manufacturing a semiconductor package having improved warpage resistance and an improved heat dissipation characteristic.

Another aspect of the present disclosure also provides a semiconductor package having improved warpage resistance and an improved heat dissipation characteristic.

However, the goals to be achieved by example embodiments of the present disclosure are not limited to the objectives described above and other objects may be clearly understood from the following example embodiments by those skilled in the art.

According to an aspect of the present disclosure, there is provided a method for manufacturing a semiconductor package, the method including mounting a first semiconductor chip on a first surface of a package substrate, forming a stiffener on a first surface of a plate, forming a first adhesive layer on the first semiconductor chip, disposing the stiffener and the plate on the package substrate such that the first surface of the plate faces the first surface of the package substrate and the stiffener is connected to the first surface of the package substrate, bonding the first surface of the plate to the first adhesive layer, and removing the plate, wherein the stiffener remains connected to the first surface of the package substrate subsequent to removing the plate.

According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor package, the method including forming a stiffener along an edge of a first surface of a plate, mounting a first semiconductor chip on a first surface of the package substrate, disposing the stiffener and the plate on the package substrate so that the first surface of the plate faces the first semiconductor chip and so that the stiffener surrounds a side surface of the first semiconductor chip, and removing the plate, wherein the stiffener remains on the package substrate subsequent to removing the plate, and wherein a thermal conductivity of the plate is less than a thermal conductivity of the stiffener.

According to still another aspect of the present disclosure, there is provided a semiconductor package including a package substrate, a first semiconductor chip disposed on a first surface of the package substrate, and a stiffener disposed on the first surface of the package substrate to be spaced apart from the first semiconductor chip and to surround the first semiconductor chip, and an upper surface of the stiffener and an upper surface of the first semiconductor chip are disposed on an identical plane, and the stiffener includes a recess formed on the upper surface of the stiffener.

Additional aspects of example embodiments will be set forth in part in the following description.

According to example embodiments, it is possible to manufacture a semiconductor package having improved warpage resistance and an improved heat dissipation characteristic.

According to example embodiment, it is possible to improve warpage resistance of a semiconductor package and improve a heat dissipation characteristic of the semiconductor package.

Before example embodiments are described, terms or words used in the present disclosure and the accompanying claims are not to be limited to general definitions or dictionary definitions. The terms and words are to be construed under a principle that an inventor may appropriately define a concept of a term in order to describe their invention in the best way. Thus, since the example embodiments described in the present disclosure and configurations illustrated in the accompanying drawings are merely most desirable example embodiments and do not represent all of the technical spirit of the present disclosure, it should be understood that various equivalents and modifications that may replace the example embodiments and configurations may be present at the time of filing the application of the present disclosure.

In the following descriptions, terms in a singular form includes terms a plural form unless an apparently and contextually conflicting description is present. Terms such as “including” or “comprising” is to indicate that a feature, a number, an operation, an action, an element, a component, or a combination thereof is present. It should be understood that the terms are not to exclude in advance a possibility that one or more other features, numbers, operations, actions, elements, components, or combinations thereof may be present or added.

In addition, it should be noted in advance that an expression such as an upper side, an upper portion, a lower side, a lower portion, a side surface, a front surface, or a rear surface is based on directions illustrated in the drawings and that the expression may be changed when a direction of a corresponding object is changed. Shapes, sizes, or the like of elements in the drawings may be exaggerated for clearer description.

Hereinafter, the example embodiments of the present disclosure will be described with reference to the drawings.

are intermediate operation diagrams illustrating a method for manufacturing a semiconductor package according to an example embodiment.

Referring to, the method for manufacturing the semiconductor package according to example embodiments of the present disclosure may include mounting a first semiconductor chipon a package substrate.

According to some example embodiments, the package substratemay be, for example, a printed circuit board (PCB), a ceramic substrate, or an interposer. Alternatively, the package substratemay be a semiconductor chip including a semiconductor device. The package substratemay function as a support substrate for the semiconductor package. The package substratemay extend in a first direction X and a second direction Y

In some example embodiments, the package substratemay be a glass substrate, the ceramic substrate, or a plastic substrate, but it is merely an example. For example, the package substratemay include a resin (e.g., prepreg, Ajinomoto Build-up Film (ABF), FR-4, or bismaleimide triazine (BT)) impregnated together with an inorganic filler in a core material such as a glass fiber (e.g., a glass cloth or a glass fabric).

According to some example embodiments, the package substratemay be, as an example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. As another example, the package substratemay be a silicon substrate. As still another example, the package substratemay include silicon germanium, a silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but it is merely an example.

According to some example embodiments, the package substratemay include a well doped with an impurity or a structure doped with an impurity. The package substratemay have various element separation structures such as a shallow trench isolation (STI) structure.

In some example embodiments, the package substratemay be formed from at least one material selected from a phenolic resin, an epoxy resin, and polyimide. The package substratemay include at least one material selected from tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine, Thermount, cyanate ester, and a liquid crystal polymer.

Although not illustrated in detail, the package substratemay include a substrate body, a lower surface pad, and an upper surface pad. Wiring patterns for electrically connecting the lower surface pad and the upper surface pad may be formed in the substrate body. The lower surface pad may be disposed on a lower surface of the substrate body. The upper surface pad may be disposed on an upper surface of the substrate body. An external connection terminal may be disposed on the lower surface pad. For example, the external connection terminal may be a solder ball or a bump.

According to some example embodiment, a first semiconductor chipmay be disposed on the package substrate. For example, the first semiconductor chipmay be mounted on an upper surface of the package substrate. The first semiconductor chipmay be mounted on the package substratethrough a flip chip bonding method. The first semiconductor chipmay be bonded on the package substrateby using a connection bump. The connection bumpmay be formed between the upper surface of the package substrateand a lower surface of the first semiconductor chip. The connection bumpmay electrically connect the first semiconductor chipand the package substrate.

According to some example embodiments, the first semiconductor chipmay be an integrated circuit (IC) in which hundreds or thousands of semiconductor devices are integrated in one chip. As an example, the first semiconductor chipmay be an application processor (AP) such as a central processing unit (CPU), a graphic processing unit (GPU), a field-programmable gate array, a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller. However, it is merely an example.

As another example, the first semiconductor chipmay be a logic chip such as an analog-digital converter (ADC) or an application-specific IC (ASIC) or may be a memory chip such as a volatile memory (e.g., a dynamic random access memory (DRAM)) or a non-volatile memory (e.g., a read-only memory (ROM), or a flash memory). In addition, the first semiconductor chipmay be configured in combination thereof.

According to some example embodiments, only one first semiconductor chipis illustrated as being formed on the package substrate, but this is merely for convenience of description. For example, a plurality of semiconductor chips may be formed side by side on the package substrateor sequentially stacked on the on the package substrate.

Then, referring to, the method for manufacturing the semiconductor package according to example embodiments of the present disclosure may include forming a stiffeneron a plate.

According to some example embodiments, the stiffenermay be formed on one surface of the plate. The stiffenermay be formed along an edge of the plate. For example, the stiffenermay be disposed along the edge of the platewhich extends in the first direction X and the second direction Y. In other words, the stiffenermay have a shape of a quadrangular ring when viewed from a plan view. A portion of the one surface of the platemay be exposed through a gap of the stiffenerwhich extends in the first direction X and the second direction Y.

Referring to, the method for manufacturing the semiconductor package according to example embodiments of the present disclosure may include forming a first adhesive layeron the upper surface of the first semiconductor chip. The first adhesive layermay cover the upper surface of the first semiconductor chip. The first adhesive layermay include a material identical to that of a second adhesive layerthat will be described below. For example, the first adhesive layermay include a pyrolytic or photolytic material.

Referring to, according to some example embodiments, the platemay include a first surface Sand a second surface S. A surface on which the stiffeneris formed may be referred to as the first surface S. For example, the one surface of the plateon which the stiffeneris formed, as described above through, may be the first surface S. A surface disposed opposite to the first surface Smay be referred to as the second surface S. A height of the first surface Smay be constant from the second surface Sof the plate. The first surface Smay not have a step difference. A thickness of the plate, between the first surface Sand the second surface S, may be constant in the first direction X. A thickness and a height, as described herein, may be measured in a third direction Z.

The platemay include, for example, copper (Cu), iron (Fe), nickel (Ni), cobalt (Co), tungsten (W), chromium (Cr), silver (Ag), gold (Au), platinum (Pt), tin (Sn), aluminum (Al), magnesium (Mg), silicon (Si), zinc (Zn), or a combination thereof. As another example, the platemay include a non-metallic substance. The platemay include stainless steel (SUS), or plastic. A thermal conductivity of the platemay be less than or equal to a thermal conductivity of the stiffener.

As an example, the stiffenermay include metal such as copper (Cu). As another example, the stiffenermay include a material identical to that of the package substrate. The stiffenerand the platemay include an identical material. For example, the stiffenerand the plateeach may include copper (Cu). In contrast, the stiffenerand the platemay include different materials. For example, the platemay include plastic, and the stiffenermay include copper (Cu).

According to some example embodiments, the stiffenermay be bonded onto the first surface Sof the plate through the second adhesive layer. The second adhesive layermay be formed between the stiffenerand the plate.

According to some example embodiments, the second adhesive layermay include a pyrolytic or photolytic material. For example, the second adhesive layermay include a pyro/photolytic epoxy resin or titanium. However, it is merely an example. The second adhesive layermay include a polymer, a resin, or a thermal interface material (TIM) including epoxy and a filling material. The filling material may include a dielectric filling material such as aluminum oxide, magnesium oxide, aluminum nitride, boron nitride, and diamond power. Also, the filling material may be a metallic filling material such as silver, copper, or aluminum.

According to some example embodiments, a third adhesive layermay be formed on one surface of the stiffener, which is disposed opposite to a surface, of the stiffener, facing the plate. The third adhesive layermay include a material different from that of the second adhesive layer. For example, the third adhesive layermay include a non-pyrolytic or non-photolytic material. The third adhesive layermay include a polymer, a resin, or a TIM including epoxy and a filling material. The filling material may include a dielectric filling material such as aluminum oxide, magnesium oxide, aluminum nitride, boron nitride, and diamond powder. The filling material may be a metal filling material such as silver, copper, or aluminum.

Then, referring to, the method for manufacturing the semiconductor package according to example embodiments of the present disclosure may include arranging the plateand the stiffeneron the package substrate.

According to some example embodiments, the plateand the stiffenermay be arranged on the package substrateso that the first surface Sof the plate faces the package substrate. The stiffenermay be arranged so as to protrude from the first surface Sof the plate toward the package substrate.

Then, referring to, the method for manufacturing the semiconductor package according to example embodiments of the present disclosure may include disposing the plateand the stiffeneron the package substrate.

According to some example embodiments, the first surface Sof the platemay be bonded to the first adhesive layeron the first semiconductor chip. The platemay be formed on the first semiconductor chipand the stiffener. The platemay overlap the first semiconductor chipand the stiffenerin the third direction Z. The third direction Z may be a direction perpendicular to the upper surface of the package substrate.

According to some example embodiments, the stiffenermay be bonded onto the package substratethrough the third adhesive layer. The stiffenermay be disposed on the package substrateto surround a side surface of the first semiconductor chip. The stiffenermay be disposed to be spaced apart from the first semiconductor chip. For example, the first semiconductor chipmay be disposed in the quadrangular ring shape which is formed by the stiffenerwhen viewed from the plan view.

According to some example embodiments, the semiconductor package may include the plateand the stiffener. The semiconductor package which includes all of the plateand the stiffenermay have an improved warpage resistance characteristic. For example, the stiffenermay suppress occurrence of warpage at an edge of the package substrate. In addition, the platewhich is disposed to overlap the first semiconductor chip, which is disposed in the gap of the stiffener, may suppress occurrence of warpage inside the stiffener. Also, heat occurring inside the semiconductor package may be transferred through the stiffenerand the plateand easily dissipated to an outside (e.g., external to the semiconductor package).

is an intermediate operation diagram illustrating a method for manufacturing a semiconductor package according to an example embodiment. For convenience of description, the following description mainly focuses on a point different from that described with reference to. For reference,is a diagram for describing an operation after that of.

Referring to, the method for manufacturing the semiconductor package according to example embodiments of the present disclosure may further include removing the plate(of).

According to some example embodiments, the removing of the plate(of) may include removing the first adhesive layer(of) and the second adhesive layer(of). As the plate(of) is removed, the first adhesive layer(of) and the second adhesive layer(of) may be removed together. For example, the first adhesive layer(of in) and the second adhesive layer(of) may be removed with heat or light. As the plate(of) is removed, an upper surface of the first semiconductor chipUS and an upper surface of the stiffenerUS may be exposed.

According to some example embodiments, from a first surface of the package substrate, which faces the first semiconductor chip, a height of the first semiconductor chipand a height of the stiffenermay be equal. Specifically, from an upper surface of the package substrate, a height of the upper surface of the first semiconductor chipUS and a height of the upper surface of the stiffenerUS may be equal.

According to some example embodiments, the plate(of) may suppress warpage of a portion of the semiconductor package to which the first semiconductor chipis disposed in a gap of the stiffener. For example, an area in which the first semiconductor chipis disposed inside the stiffenermay have a high possibility of the warpage because the first semiconductor chipand the package substrateare exposed. Meanwhile, the plate(of), which is formed to cover the first semiconductor chip, may improve warpage resistance of the semiconductor package by fixing the first semiconductor chipin the gap of the stiffenerin the third direction Z. Thus, occurrence of the warpage or twist of the semiconductor package in a semiconductor package manufacturing process may be suppressed with the plate(of). In addition, the stiffenermay have a thermal conductivity higher than that of the plate(of). Accordingly, by removing the plate(of) and exposing the stiffenerafter a manufacturing process having a condition that may allow the semiconductor package to be warped or twisted is ended, heat occurring in the semiconductor package may be easily dissipated through the stiffener.

is an intermediate operation diagram illustrating a method for manufacturing a semiconductor package according to an example embodiment. For convenience of description, the following description mainly focuses on a point different from that described with reference to. For reference,corresponds to an intermediate operation diagram illustrated in.