Three-Dimentional Pillar Type Capacitive In-Memory Computing Device, Method of Manufacturing the Same and In-Memory Computing Device Using the Same

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2024-0061077, filed on May 9, 2024, and Korean patent application number 10-2024-0182983, filed on Dec. 10, 2024, which are incorporated herein by reference in their entirety.

Embodiments of the present disclosure relate generally to a semiconductor device, and more particularly to a three-dimensional pillar type capacitive in-memory computing device, a method of manufacturing the same, and an in-memory computing device utilizing the same.

A growing interest and importance of artificial intelligence (hereinafter, AI) applications and big data analytics is driving an explosion in demand for semiconductor devices for computing and storing massive amounts of data.

Main computational methods required in the AI applications may include matrix multiplication operations. Recently, in-memory computing techniques have been studied to minimize a bottleneck of data movements and power consumption by performing matrix multiplication operations within an array of memory cells.

In the learning and inference process of the AI applications, latency and energy required for matrix multiplication operations may be closely related to the size of the in-memory computing device.

According to embodiments of the present disclosure, there is provided, a three-dimensional (3D) pillar type capacitive in-memory computing device. The 3D pillar type capacitive in-memory computing device may include a first wiring layer, a junction layer, a pillar type channel, a charge storage layer, a charge transfer layer and a second wiring layer. The junction layer may be formed on a portion of the first wiring layer in a first direction. The pillar type channel may be formed on a portion of the junction layer in the first direction. The charge storage layer may be configured to entirely surround an upper surface of the pillar type channel in the first direction and an outer surface of the pillar type channel. The charge transfer layer may be formed on a portion of the charge storage layer in the first direction. The second wiring layer may be formed on the charge transfer layer in the first direction.

According to an embodiment of the present disclosure, there is provided, a three-dimensional (3D) pillar type capacitive in-memory computing device. The 3D pillar type capacitive in-memory computing device may include a first wiring layer, a junction layer, a pillar type channel, a current blocking layer, a charge storage layer and a second wiring layer. The junction layer may be formed on a portion of the first wiring layer in a first direction. The pillar type channel may be formed on a portion of the junction layer in the first direction. The current blocking layer may be configured to entirely surround an upper surface of the pillar type channel in the first direction and an outer circumferential surface of the pillar type channel. The charge storage layer may be configured to entirely surround an upper surface of the current blocking layer in the first direction and an outer surface of the current blocking layer. The second wiring layer may be formed on a portion of the charge storage layer in the first direction.

According to an embodiment of the present disclosure, there is provided a method of manufacturing a 3D pillar type capacitive in-memory computing device. In the method of manufacturing the 3D pillar type capacitive in-memory computing device, a first wiring layer may be formed on a substrate. A junction layer may be formed on a portion of the first wiring layer in a first direction. A pillar type channel may be formed on a portion of the junction layer in the first direction. A charge storage layer may be formed to entirely surround a surface of the pillar type channel. A charge transfer layer may be formed on a portion of the charge storage layer in the first direction. A second wiring layer may be formed on a portion of the charge transfer layer in the first direction.

According to an embodiment of the present disclosure, there is provided, a computing device using a 3D pillar type capacitive in-memory computing device. The computing device may include a logic circuit, a memory cell array, a row decoder, a pre-amplifier, a multiplexer and an analog/digital (A/D) converter. The memory cell array may include a plurality of unit memory cells connected between a plurality of word lines and a plurality of bit lines. The row decoder may convert an externally provided digital input signal to an analog signal and applies the analog signal to a selected word line in accordance with a control of the logic circuit. The pre-amplifier may amplify an output signal applied to the bit line in accordance with a control of the logic circuit. The multiplexer may select at least one of the plurality of bit lines in accordance with a control of the logic circuit. The A/D converter may sense an analog signal applied to a selected bit line. The A/D converter may convert the analog signal into a digital signal. The A/D converter may then output the digital signal. The unit memory cell may include a first wiring layer, a junction layer, a pillar type channel, a charge storage layer, a charge transfer layer and a second wiring layer. The junction layer may be formed on a portion of the first wiring layer in a first direction. The pillar type channel may be formed on a portion of the junction layer in the first direction. The charge storage layer may be configured to entirely surround an upper surface of the pillar type channel in the first direction and an outer circumferential surface of the pillar type channel. The charge transfer layer may be formed on a portion of the charge storage layer in the first direction. The second wiring layer may be formed on a portion of the charge transfer layer in the first direction.

The advantages and features of the present invention, and methods of achieving them, will become apparent upon reference to the embodiments described in detail with reference to the accompanying drawings. The invention, however, is not limited to the embodiments disclosed herein, but may be embodied in many different forms, and these embodiments are provided merely to make the present disclosure complete, and to give those of ordinary skill in the art a complete idea of the scope of the invention, which is defined by the claims. The dimensions and relative sizes of the layers and regions in the drawings may be exaggerated for clarity of description. Throughout the specification, like reference numerals refer to like components.

is a perspective view illustrating an in-memory computing device in accordance with an embodiment of the present disclosure,is a cross-sectional view illustrating of an in-memory computing device along an X-direction in accordance with an example embodiment of the present disclosure, andis a cross-sectional view illustrating an in-memory computing device along a Y-direction in accordance with an embodiment of the present disclosure.

Referring to, an in-memory computing devicemay include a first wiring layer, a junction layerformed over the first wiring layer, a channelformed over the junction layer, a charge storage layer, a charge transfer layerand a second wiring layer. The first wiring layermay be formed on a substratein a first direction, such as a vertical (Z) direction. The junction layermay be formed over the first wiring layerin the first direction. The junction layermay be formed on a portion of the first wiring layer. The channelmay be formed over the junction layerin the first direction. The channelmay be formed on the junction layerin the first direction. For example, the channelmay include a pillar structure extended in the first direction. The channeland the junction layermay form a pillar structure in the first direction. The charge storage layermay entirely surround an upper surface and an outer surface of the channel. The charge transfer layermay be formed on the charge storage layeron the upper surface of the channelin the first direction. The second wiring layermay be formed on the charge transfer layerin the first direction.

In an embodiment of the present disclosure, a current blocking layermay be formed between the channeland the charge storage layer, however, the embodiment may not be limited thereto.

In an embodiment of the present disclosure, the first wiring layermay include a first signal line, such as, for example, a bit line.

In an embodiment of the present disclosure, the first wiring layermay include a silicon-base material, a metal-base material, or a combination thereof. The first wiring layermay include a polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first wiring layermay include polysilicon, titanium nitride, tungsten, or a combination thereof. In an embodiment, the first wiring layermay include a stack of titanium nitride and tungsten.

For example, the junction layermay include a polysilicon layer with N-type dopants.

Alternately, the channelmay include an undoped polysilicon layer.

In an embodiment of the present disclosure, the current blocking layermay include a high-K dielectric layer. For example, a dielectric constant (K) of the high-K dielectric layer may be greater than about 30.

In an embodiment, the current blocking layermay include hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AlO), lanthanum oxide (LaO) titanium oxide (TiO), tantalum oxide (TaO), niobium oxide (NBO), or strontium titanium oxide (SrTiO). Alternatively, the current blocking layermay be a composite layer comprising two or more layers of the aforementioned high dielectric materials.

In an embodiment, the charge storage layermay include a metal material.

In an embodiment, the charge transfer layermay include the high-K dielectric layer having a dielectric constant at a set level, e.g., greater than about.

In embodiment, the charge transfer layermay comprise hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AlO), lanthanum oxide (LaO) titanium oxide (TiO), tantalum oxide (TaO), niobium oxide (NBO), or strontium titanium oxide (SrTiO). Alternatively, the charge transfer layermay be a composite layer comprising two or more layers of the aforementioned high dielectric materials.

In an embodiment of the present disclosure, the second wiring layermay be a second signal line. The second signal line may be a word line.

In an embodiment of the present disclosure, the second wiring layermay include a metal-base material, a semiconductor material, or a combination thereof. The second wiring layermay include titanium nitride, tungsten, polysilicon, or a combination thereof. The second wiring layermay include a stack of titanium nitride and tungsten stacked sequentially.

In an embodiment of the present disclosure, the second wiring layermay be formed only on an upper end of the channel, and at the same time ensure excellent current transfer performance.

are cross-sectional views illustrating the technical concepts of the operation of an in-memory computing device in accordance with embodiments of the present disclosure.depicts an on state anddepicts an off state.

The in-memory computing deviceof an embodiment may include a single junction layer. Thus, an operating voltage may be applied to the second wiring layerto inject charges into the charge transfer layer, thereby causing polarization.

Due to a capacitive coupling effect between the current blocking layerand the charge transfer layer, the voltage in the charge storage layermay be dependent on the operating voltage applied to the second wiring layer.

In a program operation, when a voltage over a certain level may be applied to the second wiring layerto generate a burst current in the charge transfer layer, an abrupt charge injection may be generated from the second wiring layerto the charge storage layershown in. A numeral referenceofindicates the abrupt charges.

Because the charge storage layermay be floated, after the abrupt charge injection, the chargesmay accumulate in the charge storage layer. Thus, a capacitance between the second wiring layerand the first wiring layermay be maximized by the accumulated charges

may show the off state after the program operation.

Through an erasing operation, a depletion layer of negative chargemay be formed in the charge storage layer, thereby reducing the capacitance between the second wiring layerand the first wiring layer.

The difference between an on-state capacitance value Cshown inand an off-state capacitance value Cshown in FIG. may determine a memory window of the in-memory computing device.

is a view illustrating voltage and capacitance characteristics of an in-memory computing device in accordance with an embodiment of the present disclosure.

Referring to, a voltage Vapplied to second wiring layer, a voltage Vof the charge storage layerand capacitance characteristics during a program operation PGM, a read operation Read, and an erase operation ERA may be shown.

It can be seen that when the program voltage and the erase voltage may be applied to about +4V and about −3V for about 30 ms, respectively, it has a capacitive window of more than about 2, i.e., a memory window.

When an abrupt charge injection may be generated, dV/dt may be greater than dV/dt. This means that when a voltage over a certain level may be applied to the second wiring layer, the voltage Vof the charge storage layer, which follows the voltage of the second wiring layer, may increase rapidly, resulting in a value of dV/dVgreater than about 1.

is a view illustrating electron density by state of an in-memory computing device in accordance with an embodiment of the present disclosure.

An inversion layer (not shown) may be formed between the current blocking layerand the pillar type channelduring a read operation, after a program operation (CASE ON). Thus, the pillar type channelmay have an overall high electron density due to the inversion layer. In contrast, the electron density of the channelin an erased operation (CASE OFF) may be only measured to be high near the junction layer.

andare a view illustrating capacitance characteristics as a function of the channel length of an in-memory computing device in accordance with an embodiment of the present disclosure.

is a cross-sectional view illustrating an in-memory computing device having a junction layerwith a height Hof about 10 nm and a channel length that is 1×, 3×, 5×, 8×, or 12× the channel length H(T/G) when a target channel length H(T/G) may be about 40 nm.

is a graph showing on state capacitances according to variation of a CG voltage applied to the second wiring layer.

Referring to, the on-state capacitance may significantly increase as a channel length increases. The off-state capacitance (not shown) may also increase, but may have a very slow increase trend compared to the on-state capacitance. Thus, increasing the channel length of the pillar-type channelmay provide a large memory window.

andillustrate capacitance characteristics along a charge storage layer length of an in-memory computing device in accordance with an embodiment of the present disclosure.

shows cross-sectional views of the in-memory computing devices having different overlap lengths Hof the channeland the junction layer. For example,shows cases where overlap lengths Hare 50 nm, 30 nm, 0 nm and −30 nm.

shows a ratio C/Cwhen the in-memory computing device includes 40 nm of the channel width W, 40 nm of the channel length H, and 10 nm of length of the junction layer H. For example, the on-state capacitance Cmay be determined by the overlap lengths Hof the channeland the junction layer.

Referring toand, as the overlap length H, decreases, the capacitance ratio C/Cincreases.

For example, the off-state capacitance Chas a minimum value when the overlap length His 0 nm. That is, when a bottom portion of the charge storage layeris equal to an upper portion of the junction layer, a large memory window may be obtained, even though the on-state capacitance Cdecreases.

However, if the charge storage layeris underlapped rather than overlapped with the junction layer(for example, the overlap length His −30 nm in), the off-state capacitance Cmay no longer decrease rapidly.

Therefore, it may be important to determine the overlap length Hto maximize the on-state capacitance Con while ensuring the capacitance ratio C/C.