Semiconductor Structure

This application claims the benefit of Taiwan application Serial No. 113117627, filed May 13, 2024, the subject matter of which is incorporated herein by reference.

The disclosure relates to a semiconductor structure, and more particularly relates to a metal oxide semiconductor structure.

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of the transistors widely used in today's integrated circuits. MOSFETs may include three categories, planar MOSFETs, lateral diffused MOSFETs (LDMOS) and vertical diffused MOSFETs according to the structure difference. In comparison with other MOSFETs, the LDMOS is capable of delivering more current per unit area because its asymmetric structure provides a short channel between the drain and the source of the LDMOS. In existing LDMOS designs, high breakdown voltage is usually achieved by reducing the doping concentration of the N-type well and/or P-type well of LDMOS below the isolation structure. However, reducing the doping concentration of the N-type well and/or P-type well requires more masks and more process steps, which results in high manufacturing costs and is difficult to be compatible with other manufacturing processes. In addition, the breakdown voltage of existing LDMOS is still insufficient to meet demand.

According to some embodiments of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a substrate, a first well in the substrate and having a first side surface, a second well in the substrate and having a second side surface, a third well in the substrate, an isolation structure in the substrate and between the first well and the second well, a drain region in the first well, a source region in the third well, and a gate structure on the substrate. The second well is between the first well and the third well. The first side surface of the first well faces the second side surface of the second well. The first side surface of the first well is apart from the second side surface of the second well.

The above and other embodiments of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.

Various embodiments will be described more fully hereinafter with reference to accompanying drawings, which are provided for illustrative and explaining purposes rather than a limiting purpose. For clarity, the components may not be drawn to scale. In addition, some components and/or reference numerals may be omitted from some drawings. It is contemplated that the elements and features of one embodiment can be beneficially incorporated in another embodiment without further recitation. In the following methods for manufacturing semiconductor devices, there may be one or more additional operations between the operations described, and the order of the operations may vary. The illustration uses the same/similar reference numerals to indicate the same/similar elements.

As used in the specification and the appended claims, the ordinals such as “first”, “second” and the like to describe elements do not imply or represent a specific position in the structure, or the order of arrangement, or the order of manufacturing. The ordinals are only used to clearly distinguish multiple elements with the same name. As used in the specification and the appended claims, spatial relation terms such as “on”, “above”, “over”, “upper,” “top”, “below”, “beneath”, “under”, “lower”, “bottom” and the like may be used to describe the relative spatial relations or positional relations between one element(s) and another element(s) as illustrated in the drawings, and these spatial relations or positional relations, unless specified otherwise, can be direct or indirect. The spatial relation terms are intended to encompass different orientations of structures in addition to the orientation depicted in the drawings. The structure can be inverted or rotated by various angles, and the spatial relation descriptions used herein can be interpreted accordingly. As used in the specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used in the specification and the appended claims, term “adjoin” refers to “be adjacent to and contact”.

Referring to,illustrates a schematic view of a semiconductor structure according to some embodiments of the present disclosure. The semiconductor structure includes a transistor structure. The transistor structurecan be a lateral diffused MOSFET. The transistor structureincludes a substrate, a first well, a second well, a third well, an isolation structure, a drain region, a source regionand a gate structure. The substratecan be formed by a semiconductor material such as monocrystalline silicon, polycrystalline silicon, germanium, diamond, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, and any combination thereof. The substrateincludes dopant. For example, the dopant can be an electron donor or electron acceptor. The substratemay have a first conductivity type or a second conductivity type different from the first conductivity type depending on the type of the dopant. For example, the first conductivity type is N-type, and the second conductivity type is P-type. The substratehaving the first conductivity type can be used for P-type lateral diffused MOSFET. The substratehaving the second conductivity type can be used for N-type lateral diffused MOSFET. The following description uses the substratehaving the second conductivity type (P-type) and a N-type lateral diffused MOSFET as embodiments to illustrate the present disclosure, but the present disclosure can also be applied to a P-type lateral diffused MOSFET.

The first wellis in the substrate. The first wellcan be formed by introducing dopants into the substrate. The first wellhas the first conductivity type. The second wellis in the substrate. The second wellcan be formed by introducing dopants into the substrate. The second wellhas the first conductivity type. The third wellin the substrate. The third wellcan be formed by introducing dopants into the substrate. The third wellhas the second conductivity type. The second wellis between the first welland the third well. The second welladjoins the third well. A P-N junction is formed at the contact interface between the second welland the third wellsince the conductivity type of the second wellis different from the conductivity type of the third well. A P-N junction is formed at the contact interface between the first welland the substratesince the conductivity type of the first wellis different from the conductivity type of the substrate. A P-N junction is formed at the contact interface between the second welland the substratesince the conductivity type of the second wellis different from the conductivity type of the substrate. The isolation structureis in the substrateand between the first welland the second well. The first welland the second wellare separated by the isolation structure. For example, the isolation structureis a shallow trench isolation structure (STI). A portion of the first wellextends below the isolation structure. A portion of the second wellextends below the isolation structure.

The drain regionis in the first well. The drain regioncan be formed by introducing dopants into the first well. The drain regionhas the first conductivity type. The doping concentration of the drain regioncan be higher than the doping concentration of the first welland the doping concentration of the second well. The source regionin the third well. The source regioncan be formed by introducing dopants into the third well. The source regionhas the first conductivity type. The doping concentration of the source regioncan be higher than the doping concentration of the first welland the doping concentration of the second well. The gate structureis on the substrateand between the drain regionand the source region. The gate structuremay include a gate dielectric film and a gate electrode film on the gate dielectric film. The gate electrode film may have a single-layer or multi-layer structure. The gate structuremay partially overlap the third welland the isolation structurein a longitudinal direction. The gate structuremay overlap or partially overlap the second wellin the longitudinal direction. In some embodiments, the gate structureis closer to the source regionthan to the drain region.

The transistor structuremay further include a doping regionand an isolation structurein the third well. The isolation structureis between the doping regionand the source region. The doping regionand the source regionare separated by the isolation structure. The doping regioncan be formed by introducing dopants into the third well. The doping regionhas the second conductivity type. The doping concentration of the doping regioncan be higher than the doping concentration of the third well. The third wellmay cover a lower surface of the isolation structure. The doping regionmay be a body region of the lateral diffused MOSFET. For example, the isolation structureis a shallow trench isolation structure.

A depth Hof the first wellin the longitudinal direction is greater than a depth Hof the isolation structurein the longitudinal direction. A depth Hof the second wellin the longitudinal direction is greater than the depth Hof the isolation structurein the longitudinal direction. A lower surfaceL of the isolation structureis higher than a lower surfaceL of the first welland a lower surfaceL of the second well. A depth Hof the third wellin the longitudinal direction is greater than a depth Hof the isolation structurein the longitudinal direction. The depth Hof the first wellin the longitudinal direction, the depth Hof the second wellin the longitudinal direction and the depth Hof the third wellin the longitudinal direction may be the same as or different from each other. The depth Hof the isolation structurein the longitudinal direction and the depth Hof the isolation structurein the longitudinal direction may be the same as or different from each other. At least a portion of the lower surfaceL of the isolation structureis not covered by the first welland the second welland can directly contact the substrate. In the embodiment shown in, a portion of the lower surfaceL of the isolation structureis covered by the first well, another portion of the lower surfaceL of the isolation structureis covered by the second well, and yet another portion (or the other portion) of the lower surfaceL of the isolation structureis not covered by the first welland the second well.

The isolation structuremay partially overlap the first wellin a longitudinal direction. The isolation structuremay partially overlap the second wellin a longitudinal direction. The isolation structureincludes a first portion-, a second portion-and a third portion-between the first portion-and the second portion-. The first portion-overlaps the first wellin the longitudinal direction and directly contacts the first welland the drain region. The second portion-overlaps the second wellin the longitudinal direction and directly contacts the second well. The third portion-does not overlap the first welland the second wellin the longitudinal direction. The third portion-may directly contact the substrate.

The first wellhas a side surfaceS. The side surfaceS may be below the isolation structure. The second wellhas a side surfaceS. The side surfaceS may be below the isolation structure. The side surfaceS of the first wellfaces the side surfaceS of the second well. The side surfaceS of the first wellis apart from the side surfaceS of the second well. The substratemay directly contact or cover the side surfaceS of the first welland the side surfaceS of the second well.

The isolation structurehas a sidewallSand a sidewallSopposite to the sidewallS. The sidewallSof the isolation structureis covered by the first well. The sidewallSof the isolation structureis covered by the second well. A distance Gbetween the sidewallSof the isolation structureand the side surfaceS of the first wellis greater than zero. A distance Gbetween the sidewallSof the isolation structureand the side surfaceS of the second wellis greater than zero. The distances Gand Gare along the lateral direction. The lateral direction is perpendicular to the longitudinal direction. The distance Gmay be equal to the distance Gor may not be equal to the distance G.

When the transistor structureis in an “on” state, current flows from the source regionto the drain regionthrough the third well, the second well, the substrateand the first well, the current path can be represented as the current pathshown in. In some embodiments, when the transistor structureis in an “on” state, current flows from the source regionto the drain regionthrough the third well, the P-N junction between the third welland the second well, the second well, the P-N junction between the second welland the substrate(e.g. the side surfaceS), the substrate, the P-N junction between the substrateand the first well(e.g. the side surfaceS) and the first well.

Referring to,illustrates a schematic view of a semiconductor structure according to some embodiments of the present disclosure. The semiconductor structure includes a transistor structure. The transistor structurecan be a lateral diffused MOSFET. The difference between the transistor structureand the transistor structureshown inis that, the lower surfaceL of the isolation structureof the transistor structureis not coved by the first well, and the isolation structuredoes not overlap the first wellin the longitudinal direction. In the present embodiment, a portion of the lower surfaceL of the isolation structureis covered by the second well, and another portion of the lower surfaceL of the isolation structureis not covered by the first welland the second welland directly contact the substrate. The first portion-of the isolation structuredoes not overlap the first wellin the longitudinal direction and the first portion-of the isolation structuredirectly contacts the substrate. The second portion-of the isolation structureoverlaps the second wellin the longitudinal direction and directly contacts the second well. The third portion-of the isolation structuredoes not overlap the first welland the second wellin the longitudinal direction. The third portion-may directly contact the substrate.

A distance in the lateral direction between the sidewallSof the isolation structureand the side surfaceS of the first wellis equal to zero. The side surfaceS of the first wellis aligned with the sidewallSof the isolation structurein the longitudinal direction. A distance Gbetween the sidewallSof the isolation structureand the side surfaceS of the second wellis greater than zero.

When the transistor structureis in an “on” state, current flows from the source regionto the drain regionthrough the third well, the second well, the substrateand the first well, the current path can be represented as the current pathshown in. In some embodiments, when the transistor structureis in an “on” state, current flows from the source regionto the drain regionthrough the third well, the P-N junction between the third welland the second well, the second well, the P-N junction between the second welland the substrate(e.g. the side surfaceS), the substrate, the P-N junction between the substrateand the first well(e.g. the side surfaceS) and the first well.

Referring to,illustrates a schematic view of a semiconductor structure according to some embodiments of the present disclosure. The semiconductor structure includes a transistor structure. The transistor structurecan be a lateral diffused MOSFET. The difference between the transistor structureand the transistor structureshown inis that, the lower surfaceL of the isolation structureof the transistor structureis not coved by the second well, and the isolation structuredoes not overlap the second wellin the longitudinal direction. In the present embodiment, a portion of the lower surfaceL of the isolation structureis covered by the first well, and another portion of the lower surfaceL of the isolation structureis not covered by the first welland the second welland directly contact the substrate. The first portion-of the isolation structureoverlaps the first wellin the longitudinal direction and directly contacts the first well. . . . The second portion-of the isolation structuredoes not overlap the second wellin the longitudinal direction and the second portion-of the isolation structuredirectly contacts the substrate. The third portion-of the isolation structuredoes not overlap the first welland the second wellin the longitudinal direction. The third portion-may directly contact the substrate.

A distance Gbetween the sidewallSof the isolation structureand the side surfaceS of the first wellis greater than zero. A distance in the lateral direction between the sidewallSof the isolation structureand the side surfaceS of the second wellis equal to zero. The side surfaceS of the second wellis aligned with the sidewallSof the isolation structurein the longitudinal direction.

When the transistor structureis in an “on” state, current flows from the source regionto the drain regionthrough the third well, the second well, the substrateand the first well, the current path can be represented as the current pathshown in. In some embodiments, when the transistor structureis in an “on” state, current flows from the source regionto the drain regionthrough the third well, the P-N junction between the third welland the second well, the second well, the P-N junction between the second welland the substrate(e.g. the side surfaceS), the substrate, the P-N junction between the substrateand the first well(e.g. the side surfaceS) and the first well.

Referring to,illustrates a schematic view of a semiconductor structure according to some embodiments of the present disclosure. The semiconductor structure includes a transistor structure. The transistor structurecan be a lateral diffused MOSFET. The difference between the transistor structureand the transistor structureshown inis that, the lower surfaceL of the isolation structureof the transistor structureis not coved by the first welland the second well, and the isolation structuredoes not overlap the first welland the second wellin the longitudinal direction. In the present embodiment, the lower surfaceL of the isolation structureis completely not covered by the first welland the second well, and the lower surfaceL of the isolation structuredirectly contacts the substrate.

A distance in the lateral direction between the sidewallSof the isolation structureand the side surfaceS of the first wellis equal to zero. The side surfaceS of the first wellis aligned with the sidewallSof the isolation structurein the longitudinal direction. A distance in the lateral direction between the sidewallSof the isolation structureand the side surfaceS of the second wellis equal to zero. The side surfaceS of the second wellis aligned with the sidewallSof the isolation structurein the longitudinal direction.

When the transistor structureis in an “on” state, current flows from the source regionto the drain regionthrough the third well, the second well, the substrateand the first well, the current path can be represented as the current pathshown in. In some embodiments, when the transistor structureis in an “on” state, current flows from the source regionto the drain regionthrough the third well, the P-N junction between the third welland the second well, the second well, the P-N junction between the second welland the substrate(e.g. the side surfaceS), the substrate, the P-N junction between the substrateand the first well(e.g. the side surfaceS) and the first well.

Referring to,illustrates a schematic view of a semiconductor structure according to some embodiments of the present disclosure. The semiconductor structure includes a transistor structureand a transistor structure. The transistor structureis adjacent to the transistor structure. The transistor structureincludes a substrate, a first well, a second well, a third well, an isolation structure, a drain region, a source region, a gate structure, a doping regionand an isolation structure. The transistor structureand the transistor structuremay share the first well, the drain regionand the substrate. The second welland the third wellare in the substrate. The second welladjoins the third well. The second wellis between the first welland the third well. The second wellcan be formed by introducing dopants into the substrate. The second wellhas the first conductivity type. The third wellcan be formed by introducing dopants into the substrate. The third wellhas the second conductivity type. A P-N junction is formed at the contact interface between the second welland the third wellsince the conductivity type of the second wellis different from the conductivity type of the third well. A P-N junction is formed at the contact interface between the second welland the substratesince the conductivity type of the second wellis different from the conductivity type of the substrate. The isolation structureis in the substrateand between the first welland the second well. The first welland the second wellare separated by the isolation structure. For example, the isolation structuresandare shallow trench isolation structures.

The drain regionhas the first conductivity type. The doping concentration of the drain regioncan be higher than the doping concentration of the first welland the doping concentration of the second well. The source regionin the third well. The source regioncan be formed by introducing dopants into the third well. The source regionhas the first conductivity type. The doping concentration of the source regioncan be higher than the doping concentration of the first welland the doping concentration of the second well. The gate structureis on the substrateand between the drain regionand the source region. The gate structuremay include a gate dielectric film and a gate electrode film on the gate dielectric film. The gate electrode film may have a single-layer or multi-layer structure. The gate structuremay partially overlap the third welland the isolation structurein the longitudinal direction. The gate structuremay overlap or partially overlap the second wellin the longitudinal direction. In some embodiments, the gate structureis closer to the source regionthan to the drain region. The isolation structureis between the doping regionand the source region. The doping regionand the source regionare separated by the isolation structure. The doping regioncan be formed by introducing dopants into the third well. The doping regionhas the second conductivity type. The doping concentration of the doping regioncan be higher than the doping concentration of the third well. The third wellmay cover a lower surface of the isolation structure. The doping regionmay be a body region of the lateral diffused MOSFET.

The depth Hof the first wellin the longitudinal direction is greater than a depth Hof the isolation structurein the longitudinal direction. A depth Hof the second wellin the longitudinal direction is greater than the depth Hof the isolation structurein the longitudinal direction. A lower surfaceL of the isolation structureis higher than the lower surfaceL of the first welland a lower surfaceL of the second well. A depth Hof the third wellin the longitudinal direction is greater than a depth Hof the isolation structurein the longitudinal direction. The depth Hof the first wellin the longitudinal direction, the depth Hof the second wellin the longitudinal direction and the depth Hof the third wellin the longitudinal direction may be the same as or different from each other. The depth Hof the isolation structurein the longitudinal direction and the depth Hof the isolation structurein the longitudinal direction may be the same as or different from each other.

At least a portion of the lower surfaceL of the isolation structureis not covered by the first welland the second well. In the present embodiment, a portion of the lower surfaceL of the isolation structureis covered by the first well, another portion of the lower surfaceL of the isolation structureis covered by the second well, and yet another portion of the lower surfaceL of the isolation structurecan directly contact the substrate. The isolation structureincludes a first portion-, a second portion-and a third portion-between the first portion-and the second portion-. The first portion-overlaps the first wellin the longitudinal direction and directly contacts the first welland the drain region. The second portion-overlaps the second wellin the longitudinal direction and directly contacts the second well. The third portion-does not overlap the first welland the second wellin the longitudinal direction. The third portion-may directly contact the substrate.

The first wellhas a side surfaceSS. The side surfaceSS may be below the isolation structure. The second wellhas a side surfaceS. The side surfaceS may be below the isolation structure. The side surfaceSS of the first wellfaces the side surfaceS of the second well. The side surfaceSS of the first wellis apart from the side surfaceS of the second well. The substratemay directly contact or cover the side surfaceSS of the first welland the side surfaceS of the second well.

The isolation structurehas a sidewallSand a sidewallSopposite to the sidewallS. The sidewallSis covered by the first well. The sidewallSis covered by the second well. A distance Gbetween the sidewallSof the isolation structureand the side surfaceSS of the first wellis greater than zero. A distance Gbetween the sidewallSof the isolation structureand the side surfaceS of the second wellis greater than zero. The distances Gand Gare along the lateral direction. The distance Gmay be equal to the distance Gor may not be equal to the distance G. When the transistor structureis in an “on” state, the current path of the transistor structurecan be similar to the current path of the transistor structure.

In, the relative positional relationship between the isolation structure, the first welland the second wellin the transistor structure, and the manner in which the lower surfaceL of the isolation structureis covered by the first welland the second wellare similar to that of the transistor structure, but the present disclosure is not limited thereto. The relative positional relationship between the isolation structure, the first welland the second wellin the transistor structure, and the manner in which the lower surfaceL of the isolation structureis covered by the first welland the second wellmay be similar to that of transistor structureoror. In addition, the transistor structureof the semiconductor structure shown incan be replaced by the transistor structureoror.

According to the above embodiments, the transistor structure of the semiconductor structure of the present disclosure includes a first well, a second well and an isolation structure between the first well and the second well, the side surface of the first well is apart from the side surface of the second well which faces the side surface of the first well. That is, at least a portion of the lower surface of the isolation structure is not covered by the well (including the first well and the second well).

shows testing results of semiconductor structures according to some embodiments of the present disclosure. The horizontal axis inrepresents a length difference between a length of the isolation structure between a first well and a second well of a tested transistor structure in the lateral direction (or can be understood as a distance in the lateral direction between the sidewallSand the sidewallS) and a length of the isolation structure of a standard transistor structure in the lateral direction. The vertical axis inrepresents a breakdown voltage difference between a breakdown voltage of a tested transistor structure in an “OFF” state and a breakdown voltage of a standard transistor structure. The horizontal axis ina breakdown voltage difference between a breakdown voltage of a tested transistor structure in an “OFF” state and a breakdown voltage of a standard transistor structure. The vertical axis inrepresents the percentage of the on-resistance of the tested transistor structure in an “OFF” state relative to the on-resistance of the standard transistor structure. In, symbol “x” represents the transistor structure of the present disclosure, and symbol “•” represents the transistor structure of the comparative example. In the transistor structure of the comparative example, the isolation structure in a well and the lower surface of the isolation structure is completely covered by this well. As shown in, when the lengths of the isolation structures are the same, the transistor structure of the present disclosure has a higher breakdown voltage; the breakdown voltage of the transistor structure of the present disclosure increases significantly as the length of the isolation structure increases. As shown in, although increasing the breakdown voltage will lead to an increase in on-resistance, the transistor structure of the present disclosure can keep the on-resistance within an appropriate range, and the semiconductor structure has excellent electrical performance. Therefore, by making at least a portion of the lower surface of the isolation structure not covered by the well, the present disclosure can effectively increase the breakdown voltage, maintain a good balance between the breakdown voltage and the on-resistance, and improve the reliability and operation stability of the semiconductor structure. Moreover, the transistor structure of the present disclosure is compatible with existing manufacturing processes of metal oxide semiconductor and does not require additional photomasks. The manufacturing cost of the semiconductor structure of the present disclosure is low and the semiconductor structure of the present disclosure is easy to manufacture.

It is noted that the structures as described above are provided for illustration. The disclosure is not limited to the configurations disclosed above. Other embodiments with different configurations of known elements can be applicable, and the exemplified structures could be adjusted and changed based on the actual needs of the practical applications. It is, of course, noted that the configurations of figures are depicted only for demonstration, not for limitation. Thus, it is known by people skilled in the art that the related elements and layers in a semiconductor structure, the shapes or positional relationship of the elements and the procedure details could be adjusted or changed according to the actual requirements.

While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.