Semiconductor Device Structure and Methods of Forming the Same

This application is a divisional application of U.S. patent application Ser. No. 17/739,149 filed May 8, 2022, which is incorporated by reference in its entirety.

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.

In pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a multi-gate field effect transistor (FET), including a nanostructure FET. As transistor dimensions are continually scaled down, further improvements of the nanostructure FET are needed.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

show exemplary sequential processes for manufacturing a semiconductor device structure, in accordance with some embodiments. It is understood that additional operations can be provided before, during, and after processes shown byand some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

are perspective views of various stages of manufacturing a semiconductor device structure, in accordance with some embodiments. As shown in, a stack of semiconductor layersis formed over a substrate. The substratemay be a semiconductor substrate. In some embodiments, the substrateincludes a single crystalline semiconductor layer on at least the surface of the substrate. The substratemay include a single crystalline semiconductor material such as, but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In this embodiment, the substrateis made of Si. In some embodiments, the substrateis a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxide.

The substratemay include various regions that have been suitably doped with impurities (e.g., p-type or n-type impurities). The dopants are, for example boron for a p-type field effect transistor FET (NFET) and phosphorus for an n-type FET (PFET).

The stack of semiconductor layersincludes first semiconductor layers(-) and second semiconductor layers(-). The first semiconductor layersand the second semiconductor layersare made of semiconductor materials having different etch selectivity and/or oxidation rates. For example, the first semiconductor layersare made of SiGe and the second semiconductor layersare made of Si. In some embodiments, the stack of semiconductor layersincludes alternating first and second semiconductor layers,. The second semiconductor layersor portions thereof may form nanosheet channel(s) of the semiconductor device structureat a later stage. The semiconductor device structuremay include a nanostructure transistor. The term nanostructure is used herein to designate any material portion with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section. The nanostructure channel(s) of the semiconductor device structuremay be surrounded by the gate electrode layer. The nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistors having the gate electrode layer surrounding the channels. The use of the second semiconductor layersto define a channel or channels of the semiconductor device structureis further discussed below.

In some embodiments, the semiconductor device structureincludes a complementary FET (CFET), and the second semiconductor layersincludes channels for two or more nanostructure FETs. For example, the second semiconductor layersdefine the channels of a first FET, such as a PFET, and the second semiconductor layersdefine the channels of a second FET, such as an NFET. The thickness of the second semiconductor layersis chosen based on device performance considerations. In some embodiments, each second semiconductor layerhas a thickness ranging from about 7 nanometers (nm) to about 9 nm.

The second semiconductor layermay function as an etch stop layer during back side processes. The second semiconductor layermay have a thickness less than that of the second semiconductor layersorIn some embodiments, the thickness of the second semiconductor layerranges from about 1 nm to about 2 nm. The second semiconductor layersmay function as isolation layers that isolates the gate electrode layers and the dielectric material. The second semiconductor layermay have a thickness less than that of the second semiconductor layersorand greater than that of the second semiconductor layerIn some embodiments, the thickness of the second semiconductor layersranges from about 2 nm to about 4 nm. The use of the second semiconductor layersto form isolated channels of two FETs is further discussed below.

The first semiconductor layersmay eventually be removed and serve to define spaces for a gate stack to be formed therein. The thickness is chosen based on device performance considerations. In some embodiments, each first semiconductor layerhas a thickness ranging from about 7 nm to about 11 nm. The first semiconductor layermay eventually be removed and serve to define a space for a dielectric material to be formed therein. The thickness of the first semiconductor layermay be less than that of the first semiconductor layersIn some embodiments, the first semiconductor layerhas a thickness ranging from about 5 nm to about 9 nm. The first semiconductor layermay be eventually removed to define a space for an etch stop layer to be formed therein. The first semiconductor layermay have a composition different from the composition of the first semiconductor layersIn some embodiments, the first semiconductor layersinclude SiGe, and the first semiconductor layerhas a higher atomic percent Ge than that of the first semiconductor layersAs a result, the first semiconductor layermay be etched at a faster rate than the first semiconductor layersThe thickness of the first semiconductor layermay range from about 5 nm to about 30 nm.

The first and second semiconductor layers,are formed by any suitable deposition process, such as epitaxy. By way of example, epitaxial growth of the layers of the stack of semiconductor layersmay be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes.

is a perspective view of one of the various stages of manufacturing the semiconductor device structure, in accordance with some embodiments. As shown in, finsare formed. In some embodiments, each finincludes a substrate portionformed from the substrate, a portion of the stack of semiconductor layers, and a portion of a mask structure. The mask structureis formed over the stack of semiconductor layersprior to forming the fins. The mask structuremay include an oxygen-containing layerand a nitrogen-containing layer. The oxygen-containing layermay be a pad oxide layer, such as a SiOlayer. The nitrogen-containing layermay be a pad nitride layer, such as SiN. The mask structuremay be formed by any suitable deposition process, such as chemical vapor deposition (CVD) process.

The finsmay be fabricated using suitable processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the finsby etching the stack of semiconductor layersand the substrate. The etch process can include dry etch, wet etch, reactive ion etch (RIE), and/or other suitable processes. As shown in, two finsare formed, but the number of the fins is not limited to two.

In some embodiments, the finsmay be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer (not shown) over the mask structure, exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a patterned resist. In some embodiments, patterning the resist to form the patterned resist may be performed using an electron beam (e-beam) lithography process. The patterned resist may then be used to protect regions of the substrate, and layers formed thereupon, while an etch process forms trenchesin unprotected regions through the mask structure, the stack of semiconductor layers, and into the substrate, thereby leaving the extending fins. The trenchesmay be etched using a dry etch (e.g., RIE), a wet etch, and/or combination thereof.

As shown in, each finincludes a plurality of second semiconductor layers, which includes a first group of second semiconductor layersa second group of second semiconductor layersand a third group of second semiconductor layers. The second group of second semiconductor layersmay be disposed over the first group of second semiconductor layersand the third group of second semiconductor layersmay be disposed over the second group of second semiconductor layersThe first, second, third groups of the second semiconductor layersmay be aligned along the Z direction, which may be substantially perpendicular to a major surface of the substrate. In some embodiments, at least two edges of the second semiconductor layersare aligned along the Z direction. In some embodiments, the plurality of second semiconductor layersincludes a stack of second semiconductor layersspaced apart from and aligned with each other.

is a perspective view of one of the various stages of manufacturing the semiconductor device structure, in accordance with some embodiments. As shown in, an insulating materialis formed on the substrate. The insulating materialfills the trench(). The insulating materialmay be first formed over the substrateso that the finsare embedded in the insulating material. Then, a planarization operation, such as a chemical mechanical polishing (CMP) process and/or an etch-back process, is performed such that the tops of the fins(e.g., the nitrogen-containing layer) are exposed from the insulating material, as shown in. The insulating materialmay be made of an oxygen-containing material, such as silicon oxide or fluorine-doped silicate glass (FSG); a nitrogen-containing material, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; a low-k dielectric material; or any suitable dielectric material. The insulating materialmay be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or flowable CVD (FCVD).

Next, as shown in, the insulating materialmay be recessed by removing a portion of the insulating materiallocated between adjacent finsto form trenches. The trenchesmay be formed by any suitable removal process, such as dry etch or wet etch that selectively removes the insulating materialbut not the semiconductor material of the liner. The recessed insulating materialmay be the shallow trench isolation (STI). The insulating materialincludes a top surfacethat may be level with or below a surface of the first semiconductor layersin contact with the substrate portionsof the substrate.

Next, as shown in, one or more sacrificial gate stacksare formed on the semiconductor device structure. The sacrificial gate stackmay include a sacrificial gate dielectric layer, a sacrificial gate electrode layer, and a mask structure. The sacrificial gate dielectric layermay include one or more layers of dielectric material, such as SiO, SiN, a high-k dielectric material, and/or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layermay be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable process. The sacrificial gate electrode layermay include polycrystalline silicon (polysilicon). The mask structuremay include an oxygen-containing layerand a nitrogen-containing layer. In some embodiments, the sacrificial gate electrode layerand the mask structureare formed by various processes such as layer deposition, for example, CVD (including both LPCVD and PECVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof.

The sacrificial gate stacksmay be formed by first depositing blanket layers of the sacrificial gate dielectric layer, the sacrificial gate electrode layer, and the mask structure, followed by pattern and etch processes. For example, the pattern process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etch process may include dry etch (e.g., RIE), wet etch, other etch methods, and/or combinations thereof. By patterning the sacrificial gate stack, the stacks of semiconductor layersof the finsare partially exposed on opposite sides of the sacrificial gate stack. As shown in, one sacrificial gate stackis formed, but the number of the sacrificial gate stacksis not limited to one. Two or more sacrificial gate stacksmay be arranged along the Y direction in some embodiments. Three sacrificial gate stacksare arranged along the Y direction in some embodiments, as shown in.

As shown in, a spaceris formed on the sidewalls of the sacrificial gate stacks. The liners,are omitted for clarity. The spacermay be formed by first depositing a conformal layer that is subsequently etched back to form sidewall spacers. For example, a spacer material layer can be disposed conformally on the exposed surfaces of the semiconductor device structure. The conformal spacer material layer may be formed by an ALD process. Subsequently, anisotropic etch is performed on the spacer material layer using, for example, RIE. During the anisotropic etch process, most of the spacer material layer is removed from horizontal surfaces, such as the tops of the fins, leaving the spacerson the vertical surfaces, such as the sidewalls of sacrificial gate stack. The spacermay be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof. In some embodiments, the spacerincludes multiple layers, such as main spacer walls, liner layers, and the like.

Next, as shown in, exposed portions of the finsnot covered by the sacrificial gate stacksand the spacersare recessed by using one or more suitable etch processes, such as dry etch, wet etch, or a combination thereof. In some embodiments, exposed portions of the stacks of semiconductor layersof the finsare removed, exposing portions of the substrate portions. As shown in, the exposed portions of the finsare recessed to a level at or below the top surfaceof the insulating material. The recess processes may include an etch process that recesses the exposed portions of the finsbut not the spacersand the nitrogen-containing layer.

are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line A-A of, in accordance with some embodiments.are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line B-B of, in accordance with some embodiments. As shown in, three sacrificial gate stacksare disposed on the fin, and portions of the stack of semiconductor layersnot covered by the sacrificial gate stacksare removed to expose the substrate portions. At this stage, end portions of the stacks of semiconductor layersunder the sacrificial gate stacksand the spacershave substantially flat surfaces which may be flush with corresponding spacers. In some embodiments, the end portions of the stacks of semiconductor layersunder the sacrificial gate stacksand spacersare slightly horizontally etched.

As shown in, after recessing the exposed materials not covered by the sacrificial gate stacks, the first semiconductor layerand the edge portions of each first semiconductor layerare removed. In some embodiments, the removal is a selective wet etch process. For example, in cases where the first semiconductor layersare made of SiGe having a first atomic percent germanium, the first semiconductor layeris made of SiGe having a second atomic percent germanium greater than the first atomic percent germanium, and the second semiconductor layers,are made of silicon, a selective wet etch using an ammonia and hydrogen peroxide mixtures (APM) may be used. With the APM etch, the first semiconductor layeris etched at a first etch rate, the first semiconductor layersare etched at a second etch rate slower than the first etch rate due to different atomic percentages of germanium in the layers, and the second semiconductor layersare etched at a third etch rate slower than the second etch rate. As a result, the first semiconductor layermay be completely removed, while edge portions of the first semiconductor layersare removed, and the second semiconductor layersare substantially unchanged. In some embodiments, the selective removal process may include SiGe oxidation followed by a SiGeOx removal.

Next, as show in, a dielectric layeris formed in the space created by the removal of the first semiconductor layerand dielectric spacersare formed in the space created by the removal of the edge portions of the first semiconductor layersIn other words, the first semiconductor layeris replaced with the dielectric layer. In some embodiments, the dielectric spacersmay be flush with the spacers. In some embodiments, small amount of each second semiconductor layersmay be removed during the removal process, and the dielectric spacersdisposed on opposite sides of the first semiconductor layersmay be thicker than the corresponding first semiconductor layer, as shown in. In some embodiments, edge portions of the second semiconductor layerare removed, and the sides of the second semiconductor layerare in contact with the dielectric spacers.

In some embodiments, the dielectric layermay include SiO, SiN, SiCN, SiOC, SiOCN, HfO2, ZrOx, ZrAlOx, HfAlOx, HfSiOx, AlOx, or other suitable dielectric material. In some embodiments, the dielectric layermay include TiO, TaO, LaO, YO, TaCN, or ZrN. The dielectric spacersmay include SiON, SiCN, SiOC, SiOCN, or SiN. In some embodiments, the dielectric layerand the dielectric spacersinclude the same dielectric material. For example, the dielectric layerand the dielectric spacersmay be formed by first forming a conformal dielectric layer using a conformal deposition process, such as ALD, followed by an anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric layerand the dielectric spacers. The dielectric layerand the dielectric spacersmay be protected by the second semiconductor layersduring the anisotropic etching process. The dielectric layermay have a thickness ranging from about 5 nm to about 30 nm. The dielectric layerserves to protect the channel regions during the subsequent removal of the substrate. Thus, if the thickness of the dielectric layeris less than about 5 nm, the dielectric layermay not be sufficient to protect the channel regions. On the other hand, if the thickness of the dielectric layeris greater than about 30 nm, the manufacturing cost is increased without significant advantage.

Next, as shown in, S/D epitaxial featuresare formed on the substrate portionsof the fins. The S/D epitaxial featuremay include one or more layers of Si, SiP, SiC and SiCP for an NFET or Si, SiGe, Ge for a PFET. In some embodiments, the S/D epitaxial featuresincludes one or more layers of Si, SiGe, and Ge for a PFET. The S/D epitaxial featuresmay grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the material used for the substrate portions. The S/D epitaxial featuresmay be formed by an epitaxial growth method using CVD, ALD or MBE. The S/D epitaxial featuresare in contact with the second semiconductor layersand dielectric spacers, as shown in. The S/D epitaxial featuresmay be the S/D regions. In this disclosure, a source region and a drain region are interchangeably used, and the structures thereof are substantially the same.

Next, as shown in, the S/D epitaxial featuresare recessed by removing a portion of each S/D epitaxial feature. The recess of the S/D epitaxial featuresmay be performed by any suitable process, such as dry etch or wet etch that selectively removes a portion of each S/D epitaxial featurebut not the dielectric materials of the nitrogen-containing layer, the spacer, and the insulating material. As shown in, the S/D epitaxial featuresare in contact with the second semiconductor layersIn some embodiments, the semiconductor device structureincludes a nanostructure PFET having a source epitaxial featureand a drain epitaxial featureboth in contact with one or more second semiconductor layersor one or more channels. In some embodiments, the nanostructure PFET includes two second semiconductor layersas shown in.

Next, as shown in, a dielectric materialis formed on the exposed surfaces of the semiconductor device structure. In some embodiments, the dielectric materialis formed on the S/D epitaxial featuresand the insulating material. The dielectric materialmay include a material different from the nitrogen-containing layer, the spacer, and the dielectric spacers. In some embodiments, the dielectric materialan oxide that is formed by FCVD. In some embodiments, the dielectric materialmay be formed by ALD. In some embodiments, the dielectric materialincludes a material different from the insulating material.

Next, as shown in, the dielectric materialis recessed to a level below the level of the second semiconductor layersThe recess of the dielectric materialmay be performed by any suitable process, such as dry etch or wet etch that selectively removes a portion of the dielectric materialbut not the nitrogen-containing layer, the spacer, the second semiconductor layers, and the dielectric spacers. The recessed dielectric materialmay be in contact with the second semiconductor layers

Next, as shown in, S/D epitaxial featuresare formed on the dielectric material. The S/D epitaxial featuremay include one or more layers of Si, SiP, SiC and SiCP for an NFET or Si, SiGe, Ge for a PFET. In some embodiments, the S/D epitaxial featuresincludes one or more layers of Si, SiP, SiC and SiCP for an NFET. The S/D epitaxial featuresmay be formed from the second semiconductor layers. The S/D epitaxial featuresmay grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the material used for the second semiconductor layersThe S/D epitaxial featuresmay be formed by an epitaxial growth method using CVD, ALD or MBE. The S/D epitaxial featuresmay be the S/D regions.

The semiconductor device structureshown incan reduce the area of semiconductor devices, such as SRAMs having NFETs and PFETs. The source regions of the NFETs and PFETs may be vertically stacked, and the drain regions of the NFETs and the PFETs may be vertically stacked to increase the density of the FETs. The source of the NFET and the source of the PFET may be separated by the dielectric material.

Next, as shown in, the portion of the dielectric materialdisposed on the insulating materialis removed by any suitable process, such as dry etch or wet etch that selectively removes a portion of the dielectric materialbut not the nitrogen-containing material, the spacer, the S/D epitaxial features, and the insulating material. After the removal process, side surfacesof the S/D epitaxial featuresare exposed, and side surfacesof the dielectric materialare formed. The removal of the portion of the dielectric materialmay be performed by an isotropic etch process in order to expose the side surfacesof the S/D epitaxial features. As a result, the side surfacesof the dielectric materialmay have a concave profile, as shown in.

Next, as shown in, a contact etch stop layer (CESL)may be formed on the S/D epitaxial features,, such as covering the exposed surfaces of the S/D epitaxial features,. The CESLmay be also formed on the insulating material. The CESLmay include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, the like, or a combination thereof. The CESLmay be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESLis a conformal layer formed by the ALD process. An interlayer dielectric (ILD) layermay be formed on the CESL. The materials for the ILD layermay include an oxide formed from tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layerand the etch stop layerinclude different materials having different etch selectivity. The ILD layermay be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the ILD layer, the semiconductor device structuremay be subject to a thermal process to anneal the ILD layer.

A planarization process is performed to expose the sacrificial gate electrode layer. The planarization process may be any suitable process, such as a CMP process. The planarization process removes portions of the ILD layerand the CESLdisposed on the sacrificial gate stacks. The planarization process may also remove the mask structure.

Next, as shown in, the sacrificial gate electrode layerand the sacrificial gate dielectric layerare removed, exposing the stacks of first semiconductor layers. The sacrificial gate electrode layermay be first removed by any suitable process, such as dry etch, wet etch, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer, which may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layerbut not the spacers, the CESL, and the ILD layer. In some embodiments, the spacersmay be recessed by the etchant used to remove the sacrificial gate electrode layerand/or the sacrificial gate dielectric layer.

Next, the first semiconductor layersare removed. The removal processes expose the dielectric spacersand the second semiconductor layers. The removal process may be any suitable processes, such as dry etch, wet etch, or a combination thereof. The etch process may be a selective etch process that removes the first semiconductor layersbut not the dielectric spacers, the spacers, the CESL, the ILD layer, and the second semiconductor layers. As a result, openings are formed between adjacent second semiconductor layersand between the dielectric spacers. The portion of the second semiconductor layersnot covered by the dielectric spacersmay be exposed in the openings. Each second semiconductor layermay be a nanostructure channel of a first nanostructure transistor, and each second semiconductor layermay be a nanostructure channel of a second nanostructure transistor disposed over and aligned with the first nanostructure transistor.

As shown in, oxygen-containing layersmay be formed around the exposed surfaces of the second semiconductor layersin the openings. Gate dielectric layersare formed on the oxygen-containing layers, as shown in. The oxygen-containing layermay be an oxide layer, and the gate dielectric layermay include the same material as the sacrificial gate dielectric layer. In some embodiments, the gate dielectric layerincludes a high-k dielectric material. The oxygen-containing layersand the gate dielectric layersmay be formed by any suitable processes, such as ALD processes. In some embodiments, the oxygen-containing layersand the gate dielectric layersare formed by conformal processes.

Next, a first gate electrode layeris formed in each opening and on the gate dielectric layers. The first gate electrode layeris formed on the gate dielectric layerto surround a portion of each second semiconductor layerThe first gate electrode layerincludes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The first gate electrode layersmay be formed by PVD, CVD, ALD, electro-plating, or other suitable method. In some embodiments, the first gate electrode layerincludes a p-type gate electrode layer such as TiN, TaN, TiTaN, TiAlN, WCN, W, Ni, Co, or other suitable material, and the first gate electrode layeris a gate electrode layer of a PFET. The first gate electrode layermay be formed by first forming a gate electrode layer filling the opening, followed by an etch back process to recess the gate electrode layer to a level just below the bottom-most second semiconductor layeras shown in.

Next, as shown in, an isolation layeris formed in each openingand on the first gate electrode layer. The isolation layeris formed on the gate dielectric layerto surround a portion of each second semiconductor layerThe isolation layerincludes one or more layers of dielectric material, such as a metal oxide, for example a refractory metal oxide. The isolation layermay be formed by PVD, CVD, PECVD, ALD, electro-plating, or other suitable method. The isolation layermay be formed by first forming a dielectric layer filling the opening, followed by an etch back process to recess the dielectric layer to a level just above the top-most second semiconductor layeras shown in.

Next, as shown in, a second gate electrode layeris formed in each opening and on the isolation layer. The second gate electrode layeris formed on the gate dielectric layerto surround a portion of each second semiconductor layer. The second gate electrode layerincludes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The second gate electrode layersmay be formed by PVD, CVD, ALD, electro-plating, or other suitable method. The first gate electrode layerand the second gate electrode layermay include the same material or different materials. In some embodiments, the second gate electrode layerincludes an n-type gate electrode layer such as TiAlC, TaAlC, TiSiAlC, TiC, TaSiAlC, or other suitable material, and the second gate electrode layeris a gate electrode layer of an NFET.

are cross-sectional side views of various stages of manufacturing the semiconductor device structuretaken along line B-B of, in accordance with some embodiments. As shown in, an openingis formed in the ILD layerbetween adjacent S/D epitaxial features. The openingmay be a via having a critical dimension ranging from about 1 nm to about 5 nm. Because the openingis formed between adjacent S/D epitaxial features, if the critical dimension of the opening is greater than about 5 nm, the conductive feature() formed in the openingmay be electrically connected to both of the adjacent S/D epitaxial features. On the other hand, if the critical dimension of the opening is less than about 1 nm, the openingmay be too small for the conductive featureto be formed therein. The openingis formed at a location so a portion of the CESLis exposed in the opening. For example, a portion of the CESLis a part of the sidewall that defines the opening. The openingis formed by any suitable process, such as a dry etch, a wet etch, or a combination thereof. In some embodiments, the openingis formed by a selective dry etch process that removes the portion of the ILD layerbut does not remove the CESL, the spacer, and the second gate electrode layer.

Next, as shown in, the exposed portion of the CESLis removed by any suitable process. In some embodiments, the exposed portion of the CESLis removed by a selective etch process that removes the exposed portion of the CESLbut does not substantially affect the ILD, the spacer, and the second gate electrode layer. An openingis formed in the CESL, and a portion of the side surface of the S/D epitaxial featureis exposed in the opening. The openingsandare connected, as shown in. Next, as shown in, the conductive featureis formed in the openings,. The conductive featuremay include an electrically conductive material having one or more of Ru, Mo, Co, Ni. W, Ti, Ta, Cu, Al, TiN and TaN, and may be formed by any suitable process, such as ALD, PVD, ECP, or CVD. In some embodiments, the conductive featureis a metal, such as copper. The conductive featureis electrically connected to the S/D epitaxial feature.

is an enlarged cross-sectional side view of the conductive feature, in accordance with some embodiments. As shown in, the conductive featureincludes a first portionand a second portionextending from the first portion. The first portionhas a first width Walong the x-axis, and the second portionhas a second width Walong the x-axis. In some embodiments, the second width Wis the same as the thickness of the CESL. In some embodiments, the first width Wis substantially greater than the second width Wso the openings,can be filled with the conductive featurewithout voids or seams. An angle A is formed between the first portionand the second portion. The angle A is less than 180 degrees, such as from about 30 degrees to about 120 degrees. The angle A may be determined by the location of the openingand the process time when removing the exposed CESLto form the opening. For example, the angle A may be greater than about 90 degrees if the etch process to remove the exposed portion of the CESLis relatively long, and the angle A may be less than about 90 degrees if the etch process is relatively short. The second portionincludes a surface. In some embodiments, the surfaceis in direct contact with a side surface of the S/D epitaxial feature. In some embodiments, a silicide layer (not shown) may be formed between the second portionand the S/D epitaxial feature, and the surfaceis in direct contact with the silicide layer. The first portionincludes a bottom surface, and the second portionincludes a bottom surface. In some embodiments, the bottom surfaceis located at a level below the level of the bottom surface. The locations of the bottom surfaces,may be determined by the depth of the opening. For example, the openingmay be deep so the exposed portion of the CESLmay be a part of the sidewall defining the openingin order to maximize the exposed portion of the CESLin the opening. As a result, the bottom surfaceis located below the bottom, as shown in. In some embodiments, the exposed portion of the CESLis a part of the bottom of the opening, and the bottommay be located below the bottom.

is a top view of the conductive featureof, in accordance with some embodiments. As shown in, the first portionhas a first dimension Dalong the y-axis, and the second portionhas a second dimension Dalong the y-axis. The second dimension Dmay be less than, greater than, or equal to the first dimension D. Similar to the angle A, the second dimension Dmay be determined by the timing of the etch process to remove the exposed portion of the CESL. For example, the second dimension Dmay be greater than the first dimension Dif the etch process to remove the exposed portion of the CESLis relatively long, and the second dimensions Dmay be less than the first dimension Dif the etch process is relatively short. In some embodiments, in order to increase the contact area of the S/D epitaxial feature, the second dimension Dis substantially greater than the first dimension D. As shown in, in some embodiments, the surfaceis concave and includes a curvature, which may be the same curvature of the side surface of the S/D epitaxial feature.

is a cross-sectional side view of the semiconductor device structure, in accordance with an alternative embodiment. As shown in, in some embodiments, the conductive featureis electrically connected to both of the adjacent S/D epitaxial features. The conductive featuremay include the first portion, the second portionextending from the first portion, and a third portionextending from the first portion. The third portionmay be extending in opposite direction as the second portion. An angle B is formed between the first portionand the third portion. The angle B may be the same as the angle A or different from the angle A. The conductive featureshown inmay be formed by forming the opening() to expose both portions of the CESLdisposed on the adjacent S/D epitaxial features. Then the exposed portions of the CESLare removed to form two opening(). The side surfaces of the adjacent S/D epitaxial featuresare exposed in the openings, and the conductive featureformed in the openings,is electrically connected to both of the adjacent S/D epitaxial features.

After forming the conductive feature, addition processes may be performed, such as middle of line (MOL) and back end of line (BEOL) processes. For example, conductive features (not shown) for the second gate electrode layermay be formed, and an interconnect structuremay be formed over the ILD, as shown in. The interconnect structureincludes a plurality of intermetal dielectric (IMD) layers, and a plurality of conductive features, such as lines and vias, are disposed in the IMD layers. The conductive features disposed in the interconnect structureprovide electrical path to the S/D epitaxial featuresvia the conductive feature. The conductive featureis disposed between two adjacent S/D epitaxial featuresinstead of disposed over the S/D epitaxial feature. As a result, the electrical routing to the S/D epitaxial featurebecomes more flexible.

Next, as shown in, the semiconductor device structureis flipped over for back side processing. The substratemay be removed and replaced with a dielectric material, as shown in. The substratemay be removed by any suitable method, and the dielectric materialmay be formed by any suitable method. In some embodiments, the dielectric materialincludes the same material as the insulating material. As shown in, an openingis formed in the dielectric material, the insulating material, and the ILD layer. The openingmay be formed by one or more etch processes. The openingmay have the same critical dimension as the opening. Similar to the opening, a portion of the CESLdisposed on the S/D epitaxial featureis exposed in the opening. In some embodiments, the exposed portion of the CESLis a part of the sidewall defining the opening, as shown in. The exposed portion of the CESLis removed to form the opening, as shown in. The S/D epitaxial featureis exposed in the opening. The openingmay be formed by the same process as the opening.

Next, as shown in, a conductive featureis formed in the openings,. The conductive featuremay include the same material as the conductive featureand may be formed by the same process as the conductive feature. Similar to the conductive feature, the conductive featureincludes a first portionand a second portionextending from the first portion, and the angle A is formed between the first portionand the second portion. The second portionincludes a surface in electrical contact with the S/D epitaxial feature. In some embodiments, the conductive featuremay have the same shape as the conductive feature. For example, the conductive featuremay be the conductive featureshown in. In some embodiments, the first portionof the conductive featuremay have a length along the z-axis that is substantially longer than the length of the first portionof the conductive feature, because the conductive featureis formed in the ILD layer, the insulating material, and the dielectric material. The conductive featuremay be electrically connected to both of the adjacent S/D epitaxial featuresin a similar fashion as the conductive featureshown in. After the formation of the conductive feature, additional processes may be performed, such as forming a back side power rail to electrically connect to the conductive feature.