Gate Structure in Semiconductor Method and Method of Forming the Same

This application is a continuation of U.S. patent application Ser. No. 18/934,076, filed on Oct. 31, 2024, and entitled “GATE STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME,” which is a continuation of U.S. patent application Ser. No. 17/651,869, filed on Feb. 21, 2022, and entitled “GATE STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME,” now U.S. Pat. No. 12,166,074, issued Dec. 10, 2024, which claims the benefit of U.S. Provisional Application No. 63/229,677, filed on Aug. 5, 2021, and entitled “F Incorporation Method for Nanosheet Replacement Gate (RPG) Scheme and Structure Formed Thereby,” and Application No. 63/219,894, filed on Jul. 9, 2021, and entitled “Novel F Incorporation with Dipole Insertion Method and Structure Formed Thereby,” which applications are hereby incorporated herein by reference.

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.

The semiconductor industry continues to improve the integration density of various electronic components (for example, transistors, diodes, resistors, capacitors, etc.) through continual reduction in minimum feature size, which allows more components to be integrated into a given chip area. As the minimum feature sizes are reduced, however, additional problems arise and should be addressed.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A method of selectively incorporating fluorine into a gate dielectric of a replacement gate stack and the corresponding transistor are provided. In accordance with some embodiments, dummy gate stacks are removed from a first and a second device region, and nanostructures are exposed. A first and a second gate dielectrics are formed encircling the nanostructures. A protection layer may be formed on the gate dielectrics, followed by the deposition of a fluorine-containing layer. The fluorine-containing layer is removed from the second device region and left in the first device region. An annealing process is then performed to diffuse fluorine into the first gate dielectric. The fluorine-containing layer in the first device region may then be removed. Work-function layers may then be formed over the first and the second gate dielectrics.

According to some embodiments, a fluorine treatment is applied to one or more gate dielectric layers of a gate structure, and a dipole dopant species is diffused into the gate dielectric layers, thereby tuning the work functions (and thus threshold voltages) of the subsequently formed transistors. These aspects can further be implemented in various combinations, with or without additional work function tuning layers in the gate structures to tune threshold voltages. In some embodiments, the work functions of the transistors may be tuned by dipole doping, so that a work function tuning layer can be omitted from the gate structure, allowing the gate structures to be formed to a smaller size. Threshold voltages of subsequently formed transistors may thus be tuned without negatively affecting respective spacings for the gate structures of the transistors by controlling the concentration of the dipole dopant species in the gate dielectric layers. Introduction of the dipole dopant species in the gate dielectric layers may cause charge buildup in the gate dielectric layers, leading to leakage path and reliability issues of the transistors. That charge buildup may be reduced by additionally diffusing the fluorine into the gate dielectric layers.

In the description of the present disclosure, Gate All-Around (GAA) transistors (also referred to as nanostructure, e.g., nanosheet, nanowire, or the like, field effect transistors (NSFETs)), and Fin Field-Effect Transistors (FinFETs) are discussed to explain the concept of the present disclosure. The embodiments of the present disclosure may also be applied to other types of transistors such as planar transistors and the like.

Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

,B,-,A,B,,,A,B,A,B,A,B,A,B,A,B,A,B,C,D, andE illustrate various views of intermediate stages in the formation of GAA transistors in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow shown in.

Referring to, a perspective view of waferis shown. Waferincludes a multilayer structure comprising multilayer stackon substrate. In accordance with some embodiments, substrateis a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, or the like, while other substrates and/or structures, such as semiconductor-on-insulator (SOI), strained SOI, silicon germanium on insulator, or the like, could be used. Substratemay be doped as a p-type semiconductor, although in other embodiments, it may be doped as an n-type semiconductor.

In accordance with some embodiments, multilayer stackis formed through a series of deposition processes for depositing alternating materials. The respective process is illustrated as processin the process flowshown in. In accordance with some embodiments, multilayer stackcomprises first layersA formed of a first semiconductor material and second layersB formed of a second semiconductor material different from the first semiconductor material.

In accordance with some embodiments, the first semiconductor material of a first layerA is formed of or comprises SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. In accordance with some embodiments, the deposition of first layersA (for example, SiGe) is through epitaxial growth, and the corresponding deposition method may be Vapor-Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Chemical Vapor deposition (CVD), Low Pressure CVD (LPCVD), Atomic Layer Deposition (ALD), Ultra High Vacuum CVD (UHVCVD), Reduced Pressure CVD (RPCVD), or the like. In accordance with some embodiments, the first layerA is formed to a first thickness in the range between about 30 Å and about 300 Å. However, any suitable thickness may be utilized while remaining within the scope of the embodiments.

Once the first layerA has been deposited over substrate, a second layerB is deposited over the first layerA. In accordance with some embodiments, the second layersB is formed of or comprises a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these, or the like, with the second semiconductor material being different from the first semiconductor material of first layerA. For example, in accordance with some embodiments in which the first layerA is silicon germanium, the second layerB may be formed of silicon, or vice versa. It is appreciated that any suitable combination of materials may be utilized for first layersA and the second layersB.

In accordance with some embodiments, the second layerB is epitaxially grown on the first layerA using a deposition technique similar to that is used to form the first layerA. In accordance with some embodiments, the second layerB is formed to a similar thickness to that of the first layerA. The second layerB may also be formed to a thickness that is different from the first layerA. In accordance with some embodiments, the second layerB may be formed to a second thickness in the range between about 10 Å and about 500 Å, for example.

Once the second layerB has been formed over the first layerA, the deposition process is repeated to form the remaining layers in multilayer stack, until a desired topmost layer of multilayer stackhas been formed. In accordance with some embodiments, first layersA have thicknesses the same as or similar to each other, and second layersB have thicknesses the same as or similar to each other. First layersA may also have the same thicknesses as, or different thicknesses from, that of second layersB. In accordance with some embodiments, first layersA are removed in the subsequent processes, and are alternatively referred to as sacrificial layersA throughout the description. In accordance with alternative embodiments, second layersB are sacrificial, and are removed in the subsequent processes.

In accordance with some embodiments, there are some pad oxide layer(s) and hard mask layer(s) (not shown) formed over multilayer stack. These layers are patterned, and are used for the subsequent patterning of multilayer stack.

Referring to, multilayer stackand a portion of the underlying substrateare patterned in an etching process(es), so that trenchesare formed. The respective process is illustrated as processin the process flowshown in. Trenchesextend into substrate. The remaining portions of multilayer stacks are referred to as multilayer stacks′ hereinafter. Underlying multilayer stacks′, some portions of substrateare left, and are referred to as substrate strips′ hereinafter. Multilayer stacks′ include semiconductor layersA andB. Semiconductor layersA are alternatively referred to as sacrificial layers, and Semiconductor layersB are alternatively referred to as nanostructures hereinafter. The portions of multilayer stacks′ and the underlying substrate strips′ are collectively referred to as semiconductor strips.

In above-illustrated embodiments, the GAA transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

illustrates the formation of isolation regions, which are also referred to as Shallow Trench Isolation (STI) regions throughout the description. The respective process is illustrated as processin the process flowshown in. STI regionsmay include a liner oxide (not shown), which may be a thermal oxide formed through the thermal oxidation of a surface layer of substrate. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, High-Density Plasma Chemical Vapor Deposition (HDPCVD), CVD, or the like. STI regionsmay also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on coating, HDPCVD, or the like. A planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process may then be performed to level the top surface of the dielectric material, and the remaining portions of the dielectric material are STI regions.

STI regionsare then recessed, so that the top portions of semiconductor stripsprotrude higher than the top surfacesT of the remaining portions of STI regionsto form protruding fins. Protruding finsinclude multilayer stacks′ and the top portions of substrate strips′. The recessing of STI regionsmay be performed through a dry etching process, wherein NFand NH, for example, are used as the etching gases. During the etching process, plasma may be generated. Argon may also be included. In accordance with alternative embodiments of the present disclosure, the recessing of STI regionsis performed through a wet etching process. The etching chemical may include HF, for example.

Referring to, dummy gate stacksand gate spacersare formed on the top surfaces and the sidewalls of (protruding) fins. The respective process is illustrated as processin the process flowshown in. Dummy gate stacksmay include dummy gate dielectricsand dummy gate electrodesover dummy gate dielectrics. Dummy gate dielectricsmay be formed by oxidizing the surface portions of protruding finsto form oxide layers, or by depositing a dielectric layer such as a silicon oxide layer. Dummy gate electrodesmay be formed, for example, using polysilicon or amorphous silicon, and other materials such as amorphous carbon may also be used.

Each of dummy gate stacksmay also include one (or a plurality of) hard mask layerover dummy gate electrode. Hard mask layersmay be formed of silicon nitride, silicon oxide, silicon carbo-nitride, silicon oxy-carbo nitride, or multilayers thereof. Dummy gate stacksmay cross over a single one or a plurality of protruding finsand the STI regionsbetween protruding fins. Dummy gate stacksalso have lengthwise directions perpendicular to the lengthwise directions of protruding fins. The formation of dummy gate stacksincludes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer over the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layers through a pattering process(es).

Next, gate spacersare formed on the sidewalls of dummy gate stacks. In accordance with some embodiments of the present disclosure, gate spacersare formed of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO), silicon carbo-nitride (SiCN), silicon oxynitride (SiON), silicon oxy-carbo-nitride (SiOCN), or the like, and may have a single-layer structure or a multilayer structure including a plurality of dielectric layers. The formation process of gate spacersmay include depositing one or a plurality of dielectric layers, and then performing an anisotropic etching process(es) on the dielectric layer(s). The remaining portions of the dielectric layer(s) are gate spacers.

illustrate the cross-sectional views of the structure shown in.illustrates the reference cross-section A-Ain, which cross-section cuts through the portions of protruding finsnot covered by gate stacksand gate spacers, and is perpendicular to the gate-length direction. Fin spacers, which are on the sidewalls of protruding fins, are also illustrated.illustrates the reference cross-section B-B in, which reference cross-section is parallel to the lengthwise directions of protruding fins.

Referring to, the portions of protruding finsthat are not directly underlying dummy gate stacksand gate spacersare recessed through an etching process to form recesses. The respective process is illustrated as processin the process flowshown in. For example, a dry etch process may be performed using CF, CF, SO, the mixture of HBr, Cl, and O, the mixture of HBr, Cl, O, and CHF, or the like to etch multilayer semiconductor stacks′ and the underlying substrate strips′. The bottoms of recessesare at least level with, or may be lower than (as shown in), the bottoms of multilayer semiconductor stacks′. The etching may be anisotropic, so that the sidewalls of multilayer semiconductor stacks′ facing recessesare vertical and straight, as shown in.

Referring to, sacrificial semiconductor layersA are laterally recessed to form lateral recesses, which are recessed from the edges of the respective overlying and underlying nanostructuresB. The respective process is illustrated as processin the process flowshown in. The lateral recessing of sacrificial semiconductor layersA may be achieved through a wet etching process using an etchant that is more selective to the material (for example, silicon germanium (SiGe)) of sacrificial semiconductor layersA than the material (for example, silicon (Si)) of the nanostructuresB and substrate. For example, in an embodiment in which sacrificial semiconductor layersA are formed of silicon germanium and the nanostructuresB are formed of silicon, the wet etching process may be performed using an etchant such as hydrochloric acid (HCl). The wet etching process may be performed using a dip process, a spray process, or the like, and may be performed using any suitable process temperatures (for example, between about 400° C. and about 600° C.) and a suitable process time (for example, between about 100 seconds and about 1,000 seconds). In accordance with alternative embodiments, the lateral recessing of sacrificial semiconductor layersA is performed through an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

illustrate the formation of inner spacers. The respective process is illustrated as processin the process flowshown in. The formation process incudes depositing a spacer layer extending into recesses, and performing an etching process to remove the portions of inner spacer layer outside of recesses, thus leaving inner spacersin recesses. Inner spacersmay be formed of or comprise SiOCN, SiON, SiOC, SiCN, or the like. Inner spacersmay also be porous so that they have a lower-k value lower than, for example, about 3.5. In accordance with some embodiments, the etching of the spacer layer may be performed through a wet etching process, in which the etching chemical may include HSO, diluted HF, ammonia solution (NHOH, ammonia in water), or the like, or combinations thereof.

Referring to, epitaxial source/drain regionsare formed in recesses. The respective process is illustrated as processin the process flowshown in. In accordance with some embodiments, the source/drain regionsmay exert stress on the nanostructuresB, which are used as the channels of the corresponding GAA transistors, thereby improving performance. In accordance with some embodiments, the corresponding transistor is n-type, and epitaxial source/drain regionsare accordingly formed as of n-type by doping an n-type dopant. For example, silicon phosphorous (SiP), silicon carbon phosphorous (SiCP), or the like may be grown to form epitaxial source/drain regions. After recessesare filled with epitaxy regions, the further epitaxial growth of epitaxy regionscauses epitaxy regionsto expand horizontally, and facets may be formed. The further growth of epitaxy regionsmay also cause neighboring epitaxy regionsto merge with each other.

After the epitaxy process, epitaxy regionsmay be further implanted with an n-type impurity to form source and drain regions, which are also denoted using reference numeral. In accordance with alternative embodiments of the present disclosure, the implantation process is skipped when epitaxy regionsare in-situ doped with the n-type impurity during the epitaxy, and the epitaxy regionsare also source/drain regions.

illustrate the cross-sectional views of the structure after the formation of Contact Etch Stop Layer (CESL)and Inter-Layer Dielectric (ILD).are obtained from the same cross-section same as the cross-sections A-A, B-B, and A-A, respectively, in. The respective process is illustrated as processin the process flowshown in. CESLmay be formed of silicon oxide, silicon nitride, silicon carbo-nitride, or the like, and may be formed using CVD, ALD, or the like. ILDmay include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or any other suitable deposition method. ILDmay be formed of an oxygen-containing dielectric material, which may be a silicon-oxide based material formed using Tetra Ethyl Ortho Silicate (TEOS) as a precursor, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Undoped Silicate Glass (USG), or the like.

In subsequent processes, replacement gate stacks are formed to replace dummy gate stacks. Referring to, a planarization process such as a CMP process or a mechanical grinding process is performed to level the top surface of ILD. The respective process is illustrated as processin the process flowshown in. In accordance with some embodiments, the planarization process may remove hard masksto reveal dummy gate electrodes, as shown in. In accordance with alternative embodiments, the planarization process may reveal, and is stopped on, hard masks. In accordance with some embodiments, after the planarization process, the top surfaces of dummy gate electrodes(or hard masks), gate spacers, and ILDare level with each other within process variations.

Next, dummy gate electrodes(and hard masks, if remaining) are removed in one or more etching processes, so that recessesare formed, as shown in. The respective process is illustrated as processin the process flowshown in.illustrates a perspective view of the structure, andillustrate the cross-sectionsA-A andB-B, respectively, in. The portions of the dummy gate dielectricsin recessesare also removed. In accordance with some embodiments, dummy gate electrodesand dummy gate dielectricsare removed through dry etching processes. For example, the etching process may be performed using reaction gas(es) that selectively etch dummy gate electrodesat a faster rate than ILD. Each recessexposes and/or overlies portions of multilayer stacks′, which include the future channel regions in subsequently completed nano-FETs. The corresponding portions of the multilayer stacks′ are between neighboring pairs of the epitaxial source/drain regions.

Sacrificial layersA are then removed to extend recessesbetween nanostructuresB, and the resulting structure is shown in. The respective process is illustrated as processin the process flowshown in. Sacrificial layersA may be removed by performing an isotropic etching process such as a wet etching process using etchants which are selective to the materials of sacrificial layersA. NanostructuresB, substrate, STI regionsremain relatively un-etched as compared to sacrificial layersA. In accordance with some embodiments in which sacrificial layersA include, for example, SiGe, and nanostructuresB include, for example, Si or SiC, tetra methyl ammonium hydroxide (TMAH), ammonium hydroxide (NHOH), or the like may be used to remove sacrificial layersA. It is appreciated that althoughand subsequent figures illustrate the cross-sections of nanostructuresB as being rectangular, nanostructuresB may have rounded corners, as illustrated by dashed lines in.

The preceding processes may be used for forming multiple types of GAA transistors. In subsequent discussion, two device regions are illustrated, each for forming a transistor therein. For example,illustrates two device regions-and-, and the structures shown therein are formed using the processes as discussed in preceding paragraphs. Each of device regions-and-may include an n-type transistor region or a p-type transistor region in any combination. For example, device regions-and-may be an n-type transistor region and a p-type transistor region, respectively, or may be a p-type transistor region and an n-type transistor region, respectively. Alternatively, both of device regions-and-are n-type transistor regions, or both of device regions-and-are p-type transistor regions.

Referring to, gate dielectricsare formed. The respective process is illustrated as processin the process flowshown in. In accordance with some embodiments, each of gate dielectricsincludes interfacial layerA and high-k dielectric layerB on the interfacial layerA. The interfacial layerA may be formed of or comprises silicon oxide, which may be deposited through a conformal deposition process such as ALD or CVD. In accordance with alternative embodiments, interfacial layerA is formed through thermal oxidation. When formed through thermal oxidation, the portions of interfacial layerA on the top surfaces of STI regionswill not be formed. In accordance with some embodiments, the high-k dielectric layersB comprise one or more dielectric layers. For example, the high-k dielectric layer(s)B may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

Referring to, protection layeris deposited conformally over the gate dielectrics. The respective process is illustrated as processin the process flowshown in. In accordance with some embodiments, protection layercomprises titanium nitride, tantalum nitride, titanium silicon nitride (TiSiN), or the like. Protection layermay be deposited through a conformal deposition process such as CVD, ALD, or the like, so that protection layerincludes portions encircling each of gate dielectrics.

The thickness of protection layeraffects the results, and hence is controlled to be in a selected range. When the thickness is too small, protection layermay not form a complete mono layer that fully encircles gate dielectrics, and cannot protect gate dielectrics. When the thickness is too big, it is difficult for fluorine to diffuse through it to reach gate dielectric layerin a short annealing time and at a low annealing temperature. Also, by controlling protection layernot to be too thick, and with the subsequent annealing being finished in a short period of time, the metal elements in subsequently deposited fluorine-containing layer, which metal elements diffuse slower than fluorine, is advantageously not significantly diffused through protection layerand diffuse into gate dielectrics.

Further referring to, fluorine-containing layeris formed on gate dielectric. The respective process is illustrated as processin the process flowshown in. In accordance with some embodiments, the formation process includes a deposition process, which includes CVD, ALD, or the like. The precursor used in the deposition process may include a fluorine-containing precursor and a reducing agent. The fluorine-containing precursor may include WF, and the reducing agent may include SiH, BH, H, the like, or combinations thereof. Protection layermay protect gate dielectricsin the deposition process, and may prevent the precursors (e.g., the fluorine-containing precursor) from etching gate dielectrics. The fluorine-containing layermay be deposited at temperatures in the range between about 250° C. and about 475° C. The pressure of the respective chamber may be in the range between about 0.5 Torr and about 400 Torr. In accordance with some embodiments, at a time the deposition of fluorine-containing layeris finished, an atomic percentage of fluorine in the deposited fluorine-containing layermay be in the range between about 3.5 percent and about 40 percent. It is appreciated that although fluorine-containing layermay be a continuous layer fully encircling the corresponding protection layer, fluorine-containing layermay form a discontinuous layer in accordance with alternative embodiments.

In accordance with alternative embodiments, as shown in, instead of forming a fluorine-contain layer on protection layer, fluorine is doped into protection layerthrough a soaking process. In the soaking process, a fluorine-containing gas is used to soak the exposed protection layer. As a result of the soaking process, a surface layer (or an entirety) of protection layerhas a high atomic percentage of fluorine, and hence forms the fluorine-containing layer. The respective process is again illustrated as processin the process flowshown in. The corresponding fluorine-containing gas may include WF, NF, CF, CaF, CrF, MoF, or the like, or combinations thereof. Some molecules of the fluorine-containing gas may remain intact while diffusing into the surface portion of protection layer, while some other molecules of the fluorine-containing precursor may at least partially dissociate, in which case, fluorine diffuses deeper into protection layer, while the metal elements such as tungsten may remain at the surface of protection layer.

The soaking process may be performed at temperatures in the range between about 250° C. and about 475° C., at a pressure in the range between about 0.5 Torr and about 50 Torr, and for a duration of between about 0.1 seconds and about 1 hour. In accordance with some embodiments, at a time the soaking process is finished, an atomic percentage of fluorine in fluorine-containing layermay be in the range between about 1.5 percent and about 55 percent.

schematically illustrates the distribution of fluorine in waferimmediately after the formation of fluorine-containing layer. Fluorine has a highest atomic percentage in fluorine-containing layer, which is either a deposited layer, or a surface layer of the original protection layer. The fluorine atomic percentage drops when going toward nanostructureB.

illustrates the formation of etching mask, which is used to remove the portions of fluorine-containing layerand protection layerin device region-. Etching maskmay include a photoresist, and may be a single-layer mask, a tri-layer mask, a quadri-layer mask, or the like. Etching maskis patterned, and is removed from device region-, while still has a portion left in device region-. Next, the portions of fluorine-containing layerand protection layerin device region-are removed through an etching process. The respective process is illustrated as processin the process flowshown in. The etching process may include a wet etching process. For example, the etching solution may include HCl, HO, NHOH, HO, or the like, or the combinations thereof. In accordance with some embodiments, the etching solution includes HCl, HO, and HO. In accordance with alternative embodiments, the etching solution includes HOand HO. In accordance with yet alternative embodiments, the etching solution includes NHOH and HO. The etching time may range between about 15 seconds and about 600 seconds. After the etching process, etching maskis removed, and the resulting structure is shown in.

In accordance with alternative embodiments, after the etching of fluorine-containing layerin device region-, the portion of protection layerin device region-is exposed, but is not removed in this stage. Rather, it will be removed after the subsequent annealing process.

The subsequent figure numbers inthroughmay have the corresponding numbers followed by letter A or B. The letter A indicates that the corresponding figure shows a cross-section same as the cross-section A-Ain, the letter B indicates that the corresponding figure shows a reference cross-section same as the reference cross-section B-B in.

In, an annealing processis performed to diffuse fluorine from the fluorine-containing layerinto protection layerand the gate dielectrics. The respective process is illustrated as processin the process flowshown in. Some of the fluorine may fill vacancies or micro-voids in the gate dielectrics, and some of the fluorine may attach to dangling silicon bonds at the interface between the interfacial layerA and nanostructuresB. The reliability of the resulting device is thus improved. The Time-Dependent Dielectric breakdown (TDDB) of gate dielectricsmay be advantageously reduced. The annealing processmay be performed at a temperature in the range between about 150° C. and about 750° C. The Annealing duration may be in the range between about 0.5 seconds and about 60 seconds.

As a result of the annealing process, the gate dielectricsin device region-have an increased fluorine atomic percentage FAP, which fluorine atomic percentage is also higher than the fluorine atomic percentage FAPin the gate dielectricsin device regions-. In accordance with some embodiments, the fluorine atomic percentage FAPis in the range between about 0.5 percent and about 20 percent. Furthermore, the difference (FAP−FAP) may be greater than about 0.5 atomic percent, and may be in the range between about 0.5 percent and about 20.

After the annealing process, the remaining portions of protection layerand fluorine-containing layerare removed from device region-through etching process, and the resulting structures are shown in. The respective process is illustrated as processin the process flowshown in. The etching process may also be performed through wet etching processes or dry etching processes. The etching chemicals may be selected from the candidate chemicals that may be used in the process shown in. For example, the etching process may include be a wet etching process, and HCl, HO, NHOH, HO, or the like, or the combinations thereof may be used.

In accordance with alternative embodiments, in which the portion of protection layerin device region-have not been removed in preceding processes, the portion of protection layerin device region-may be removed simultaneously when the portions of fluorine-containing layerand protection layerin device region-are removed.

In above discussed embodiments, the fluorine-containing layeris formed on protection layer, and is separated from high-k dielectric layerB by protection layer. In accordance with alternative embodiments, the formation of protection layeris skipped, and fluorine-containing layeris deposited directly on high-k dielectric layerB. When fluorine-containing layeris formed through deposition, as discussed above, the precursor such as WFmay etch a surface portion of high-k dielectric layerB before the newly deposited fluorine-containing layeracts as a protection layer to prevent the further etching of high-k dielectric layerB.