Epitaxial Die and Chip Die for Semiconductor Light-Emitting Device, and Manufacturing Method Thereof

The present invention relates to an epitaxial die and a chip die for a semiconductor light-emitting device, and a method of manufacturing the same, and more particularly, to an epitaxial die and a chip die for a semiconductor light-emitting device, in which only one of two electrodes is exposed to the outside, and a process of forming a p-ohmic contact electrode or an n-ohmic contact electrode is completed at the operation of manufacturing the epitaxial die, thereby enabling a significant reduction in thickness and facilitating a reduction in chip die size to improve light output, and a method of manufacturing the same.

In general, micro light-emitting diode (LED) displays (including mini LED displays) can be classified into micro LED displays with a passive matrix (PM) driving method and micro LED displays with an active matrix (AM) driving method.

Here, PM-driven micro LED displays typically have a sapphire support substrate, which finally remains, and use sorted thick BGR (Blue, Green, and Red) chips (with both fully fabricated positive and negative electrodes of the LED), which are transferred using a chip die-level process in which either horizontal chips or flip chips can be generally utilized.

In addition, AM-driven micro LED displays typically do not have a sapphire support substrate, which finally remains, and use unsorted thin BGR (Blue, Green, and Red) chips (with both fully fabricated positive and negative electrodes of the LED), which are transferred using a wafer-level process in which all horizontal chips, flip chips, and vertical chips can be generally utilized.

These conventional typical PM-and AM-driven micro LED displays have the following common issues.

First, when considering the application of vertical chips to reduce chip die size, there is a problem that, unlike flip chips, which allow defects to be immediately confirmed after bonding, in the case of vertical chips, defects can be confirmed after bonding and subsequent top-level wiring.

Further, in terms of a bonding process, higher precision is required in the bonding process due to the reduction in chip die size, and improved bonding strength is required due to the reduction in bonding area.

Further, in terms of a tiling process in which a plurality of unit displays are combined like tiles, there is an issue in which boundaries become distinct when the displays are turned off or show a black screen, and this is more noticeable in the PM driving method compared to the AM driving method. In addition, although many aspects have been improved, there is still an issue in which boundaries are visible on monochromatic screens and still images, and when tiling based on thin-film transistor (TFT) glass panels, the process is challenging due to the risk of glass breakage. Furthermore, due to the tolerance relationship between pixel pitch and tiling boundaries, various issues exist, including the expectation that the tiling process will be difficult to apply to products smaller than 100 inches.

Meanwhile, in the conventional PM-driven micro LED displays, the reduction in chip die size is the greatest challenge. That is, from an aspect ratio perspective, achieving a reduction in chip die size essentially requires decreasing a thickness of a final support substrate made of sapphire, but the current limit for the thickness of the sapphire support substrate is about 80 μm to 70 μm, and when reducing the thickness below 50 μm, a substrate breaking issue occurs. Further, there are complex issues related to chip measurement and classification in this type of micro LED display, and it is expected that flip chips will be mainly used in this type of display rather than horizontal and vertical chips, but when the flip chips are used, high-precision and high-speed bonding processes, as well as materials for them, are separately required.

Further, in conventional AM-driven micro LED displays, in which the final support substrate is not present and chip die size reduction is possible, there are issues related to resolving defects (No Good, NG). That is, the fundamental issues in epitaxial and fab processes, such as yield improvement related to wavelength and electrical characteristics at the chip-on-wafer (COW) level, have not been resolved, and there is difficulty in 100% sorting and removal of defective (NG) chips. In order to address these issues, approaches such as redundancy have been recently attempted, but have not provided a fundamental solution.

The present invention is directed to solving the above-mentioned conventional problems and providing an epitaxial die and a chip die for a semiconductor light-emitting device, in which only one of two electrodes is exposed to the outside, and a process of forming a p-ohmic contact electrode or an n-ohmic contact electrode is completed at the operation of manufacturing the epitaxial die, thereby enabling a significant reduction in thickness and facilitating a reduction in chip die size to improve light output, a semiconductor light-emitting device including the same, and a method of manufacturing the same.

According to the present invention, the above object is achieved by an epitaxial die for a semiconductor light-emitting device, including a support substrate, a bonding layer formed on the support substrate, an epitaxial protection layer formed on the bonding layer, a first ohmic electrode formed on the epitaxial protection layer, and a light-emitting part formed on the first ohmic electrode and configured to generate light, wherein the light-emitting part includes a first semiconductor region having a first conductivity type, an active region formed on the first semiconductor region and configured to generate light using recombination of electrons and holes, and a second semiconductor region formed on the active region and having a second conductivity type.

According to the present invention, the above object is achieved by an epitaxial die for a semiconductor light-emitting device, including a support substrate, a bonding layer formed on the support substrate, a first ohmic electrode formed on the bonding layer, and a light-emitting part formed on the first ohmic electrode and configured to generate light, wherein the light-emitting part includes a second semiconductor region having a second conductivity type, an active region formed on the second semiconductor region and configured to generate light using recombination of electrons and holes, and a first semiconductor region formed on the active region and having a first conductivity type.

According to the present invention, the above object is achieved by a method of manufacturing an epitaxial die for a semiconductor light-emitting device, including a light-emitting part forming operation of forming a light-emitting part, which generates light, on a growth substrate, a first electrode forming operation of forming a first ohmic electrode on the light-emitting part, a protection layer forming operation of forming an epitaxial protection layer on the first ohmic electrode, a bonding operation of bonding a support substrate and the epitaxial protection layer through a bonding layer, and a removal operation of removing the growth substrate, wherein the light-emitting part includes a first semiconductor region having a first conductivity type, an active region formed on the first semiconductor region and configured to generate light using recombination of electrons and holes, and a second semiconductor region formed on the active region and having a second conductivity type.

According to the present invention, the above object is achieved by a method of manufacturing an epitaxial die for a semiconductor light-emitting device, including a light-emitting part forming operation of forming a light-emitting part, which generates light, on a growth substrate, a protection layer forming operation of forming an epitaxial protection layer on the light-emitting part, an adhesion operation of bonding a temporary substrate and the epitaxial protection layer through an adhesive layer, a first removal operation of removing the growth substrate, a first electrode forming operation of forming a first ohmic electrode on a surface of the light-emitting part from which the growth substrate is removed, a bonding operation of bonding a support substrate and the first ohmic electrode through a bonding layer, and a second removal operation of removing the temporary substrate, and etching and removing the adhesive layer and the epitaxial protection layer, wherein the light-emitting part includes a second semiconductor region having a second conductivity type, an active region formed on the second semiconductor region and configured to generate light using recombination of electrons and holes, and a first semiconductor region formed on the active region and having a first conductivity type.

According to the present invention, the above object is achieved by a chip die for a semiconductor light-emitting device, including a support substrate, a bonding layer formed on the support substrate, an epitaxial protection layer formed on the bonding layer, a first ohmic electrode formed on the epitaxial protection layer, a light-emitting part formed on the first ohmic electrode and configured to generate light, and a second ohmic electrode formed on the light-emitting part, wherein the light-emitting part includes a first semiconductor region having a first conductivity type, an active region formed on the first semiconductor region and configured to generate light using recombination of electrons and holes, and a second semiconductor region formed on the active region and having a second conductivity type, and one side of each of the second ohmic electrode and the light-emitting part is etched to expose the first ohmic electrode to the outside.

According to the present invention, the above object is achieved by a chip die for a semiconductor light-emitting device, including a support substrate, a bonding layer formed on the support substrate, a first ohmic electrode formed on the epitaxial protection layer, a light-emitting part formed on the first ohmic electrode and configured to generate light, and a second ohmic electrode formed on the light-emitting part, wherein the light-emitting part includes a second semiconductor region having a second conductivity type, an active region formed on the second semiconductor region and configured to generate light using recombination of electrons and holes, and a first semiconductor region formed on the active region and having a first conductivity type, and one side of each of the second ohmic electrode and the light-emitting part is etched to expose the first ohmic electrode to the outside.

According to the present invention, the above object is achieved by a method of manufacturing a chip die for a semiconductor light-emitting device, including a light-emitting part forming operation of forming a light-emitting part, which generates light, on a growth substrate, a first electrode forming operation of forming a first ohmic electrode on the light-emitting part, a protection layer forming operation of forming an epitaxial protection layer on the first ohmic electrode, a bonding operation of bonding a support substrate and the epitaxial protection layer through a bonding layer, a removal operation of removing the growth substrate, an etching operation of etching one side of the light-emitting part to expose the first ohmic electrode to the outside, and a second electrode forming operation of forming a second ohmic electrode on the etched light-emitting part, wherein the light-emitting part includes a first semiconductor region having a first conductivity type, an active region formed on the first semiconductor region and configured to generate light using recombination of electrons and holes, and a second semiconductor region formed on the active region and having a second conductivity type.

According to the present invention, the above object is achieved by a method of manufacturing a chip die for a semiconductor light-emitting device, including a light-emitting part forming operation of forming a light-emitting part, which generates light, on a growth substrate, a protection layer forming operation of forming an epitaxial protection layer on the light-emitting part, an adhesion operation of bonding a temporary substrate and the epitaxial protection layer through an adhesive layer, a first removal operation of removing the growth substrate, a first electrode forming operation of forming a first ohmic electrode on a surface of the light-emitting part from which the growth substrate is removed, a bonding operation of bonding a support substrate and the first ohmic electrode through a bonding layer, a second removal operation of removing the temporary substrate, and etching and removing the adhesive layer and the epitaxial protection layer, an etching operation of etching one side of the light-emitting part to expose the first ohmic electrode to the outside, and a second electrode forming operation of forming a second ohmic electrode on the etched light-emitting part, wherein the light-emitting part includes a second semiconductor region having a second conductivity type, an active region formed on the second semiconductor region and configured to generate light using recombination of electrons and holes, and a first semiconductor region formed on the active region and having a first conductivity type.

According to the present invention, it is possible to simultaneously achieve both the advantage of a mini light-emitting diode (LED) manufacturing process, such as ease of defect classification, and low process and facility investment costs due to the use of existing general-purpose transfer equipment as is, and the advantage of a micro LED manufacturing process, such as a dramatic reduction in thickness and a reduction in chip die size by removing a final support substrate made of sapphire, thereby improving light output.

In addition, according to the present invention, unlike conventional chip dies, in which two electrodes, i.e., a positive electrode and a negative electrode, are exposed to the outside, an epitaxial die of the present invention has a structure in which only one electrode is exposed to the outside, and thus, although electrical sorting through an electro luminescence (EL) measurement method is not possible, the epitaxial die can be optically sorted through high-speed photo luminescence (PL) measurement method, thereby enabling defects (No Good, NG) to be easily identified initially using only optical characteristics (such as wavelength, full-width at half maximum (FWHM), and intensity).

In addition, an epitaxial die of the present invention has the advantage that a process of forming a p-ohmic contact electrode or an n-ohmic contact electrode, which requires high-temperature heat treatment of 300° C. or higher, is completed at the operation of manufacturing the epitaxial die, so that the epitaxial die of the present invention does not require a high-temperature heat treatment process after transfer.

In addition, an epitaxial die of the present invention is attached to a final support substrate made of sapphire, which can be removed after transfer onto a targeted wafer, thereby enabling the die to be repositioned collectively or unitarily (selectively) through conventional chip die transfer processes such as pick & place and replace.

Meanwhile, the effects of the present invention are not limited to the above-mentioned effects, and various effects may be included within the scope which is apparent to those skilled in the art from contents to be described below.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that in adding reference numerals to the components of each drawing, the same components have the same number when possible, even though the same components are shown in different drawings

In addition, in describing the embodiments of the present invention, when detailed descriptions of related known structures or functions may obscure the gist of the present invention, the detailed description thereof will be omitted.

In addition, terms such as first, second, A, B, (a), (b), and the like may be used herein to describe components of the embodiments of the present invention. Each of these terms is not used to define an essence, order, or sequence of a corresponding component but used merely to distinguish the corresponding component from other component(s).

The present invention relates to an epitaxial die and a chip die for a semiconductor light-emitting device that emits blue light, green light, or red light. In the present invention, a semi-finished light source die with a size less than or equal to that of a mini light-emitting diode (LED), which can be sorted and has the following characteristics, is defined as the epitaxial die of the present invention.

First, unlike conventional chip dies in which two electrodes, i.e., a positive electrode and a negative electrode, are all exposed to the outside, the epitaxial die of the present invention has a structure in which no electrodes are exposed or only one electrode is exposed to the outside. Accordingly, the epitaxial die of the present invention is not electrically sorted by an electro luminescence (EL) measurement method, but can be optically sorted by a high-speed photo luminescence (PL) measurement method, so that defects (NG) can detected initially using only optical characteristics (wavelength, full width half maximum (FWHM), intensity, and the like).

Second, in the epitaxial die of the present invention, a process of forming a p-ohmic contact electrode or an n-ohmic contact electrode, which requires a high-temperature heat treatment of 300° C. or higher, is completed at the operation of manufacturing the epitaxial die. Accordingly, the epitaxial die of the present invention has the advantage of not requiring a high-temperature heat treatment process after transfer to a substrate part.

Third, the epitaxial die of the present invention includes a sapphire final support substrate attached thereto, which is removed after transfer. Accordingly, the epitaxial die of the present invention has the advantage of being repositionable collectively or per unit (selectively), through typical chip die transfer processes such as pick & place and replace.

That is, the epitaxial die of the present invention and a chip die manufactured therefrom can simultaneously satisfy both the advantage of a mini light-emitting diode (LED) manufacturing process, such as ease of defect classification, and low process and facility investment costs due to the use of existing general-purpose transfer equipment as is, and the advantage of a micro LED manufacturing process, such as a dramatic reduction in thickness and a reduction in chip die size by removing a final support substrate, thereby improving light output.

Hereinafter, with reference to the accompanying drawings, an epitaxial diefor a semiconductor light-emitting device according to a first embodiment of the present invention will be described in detail.

illustrates an overall view of the epitaxial die for a semiconductor light-emitting device according to the first embodiment of the present invention.

As shown in, an epitaxial diefor a semiconductor light-emitting device according to the first embodiment of the present invention includes a support substrate, a sacrificial separation layer, a bonding layer, an epitaxial protection layer, a first ohmic electrode, and a light-emitting part.

The support substratesupports the sacrificial separation layer, the bonding layer, the epitaxial protection layer, the first ohmic electrode, and the light-emitting part, and when the support substrateis removed through a laser lift-off (LLO) technique after the epitaxial die of the present invention is transferred to a substrate part, the support substrateis preferably formed of an optically transparent and high-temperature resistant substrate made of a material that theoretically transmits 100% of a laser beam (single-wavelength light) without absorption, such as sapphire (α-phase AlO), ScMgAlO4, 4H-SiC, or 6H-SiC.

The sacrificial separation layeris a layer that is sacrificed and removed to separate the support substratefrom the bonding layerusing a laser beam in the LLO technique, and is formed by being directly grown or formed on the support substrate.

That is, the sacrificial separation layermay be composed of oxides and/or nitrides capable of being sacrificially separated by a thermal-chemical decomposition reaction due to the laser beam. The sacrificial separation layermay be formed using physical vapor deposition (PVD) techniques such as sputtering, pulsed laser deposition (PLD), or evaporators, and may also be directly grown on the support substratethrough chemical vapor deposition (CVD), and specific examples of materials thereof may include ITO, GaN, InGaN, AlGaN, InAlN, GaOx, GaON, ZnO, InGaZnO, InZnO, or InGaO.

The bonding layermay be formed of a dielectric material that does not undergo physical property changes at temperatures above 1000° C. and in a reducing atmosphere, and has excellent thermal conductivity. For example, the bonding layermay include SiO2, SiNx, SiCN, AlN, and Al2O3, and furthermore, may also include flowable oxides (FOx) such as spin-on glass (SOG, liquid SiO2) or hydrogen silsesquioxane (HSQ) to improve surface roughness.

Meanwhile, a reinforcing layer that enhances bonding strength and induces compressive stress may be formed on at least one of an upper surface and a lower surface of the bonding layer.

The reinforcing layer is a layer that enhances the bonding strength with the support substrateand induces compressive stress, and more specifically, the reinforcing layer includes a bonding reinforcing layer and a compressive stress layer.

The compressive stress layer is a layer that induces compressive stress and is formed on at least one of the upper surface and the lower surface of the bonding layer. The compressive stress layer includes dielectric materials with a coefficient of thermal expansion greater than that of the support substrate, i.e., AlN (4.6 ppm), AlNO (4.6-6.8 ppm), Al2O3 (6.8 ppm), SiC (4.8 ppm), SiCN (3.8-4.8 ppm), GaN (5.6 ppm), and GaNO (5.6-6.8 ppm), which serve to relieve tensile stress, i.e., induce compressive stress, which in turn plays a role in improving product quality by controlling stress.

The bonding reinforcing layer is a layer introduced to enhance bonding strength when the epitaxial protection layeris bonded to the sacrificial separation layerof the support substratethrough the bonding layer, and is formed on the compressive stress layer. It is preferable that the materials constituting the bonding reinforcing layer are preferentially selected from SiO2, SiNx, and the like.

Meanwhile, in the present invention, the bonding reinforcing layer or the compressive stress layer may be omitted in some cases, and in some cases, the entire reinforcing layer may be omitted, thereby allowing the epitaxial protection layerto come into direct contact with the bonding layer, or the sacrificial separation layerto come into direct contact with the bonding layer. In such a case, the bonding layermay be a structure formed by depositing a material with a coefficient of thermal expansion greater than that of the support substrate, thereby providing bonding functionality while also inducing compressive stress.

The epitaxial protection layeris a layer that prevents the light-emitting partand the first ohmic electrodefrom being damaged during the process, and may include materials selected in consideration of selective wet etching, such as oxides including SiO2 or the like and nitrides including SiNx or the like, and may also include metals and alloys.

The first ohmic electrodeis formed on the epitaxial protection layer, and is electrically connected to a first semiconductor region, which will be described below, through a p-ohmic contact. The first ohmic electrodemay be formed of materials that inherently have high transparency and/or reflectance and excellent electrical conductivity, but the present invention is not limited thereto. The materials of the first ohmic electrodemay include optically transparent materials such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and titanium nitride (TiN), and optically reflective materials such as Ag, Al, Rh, Pt, Ni, Pd, Ru, Cu, and Au, and may be used alone, or a combination of the above-described optically transparent materials and optically reflective materials may be used.

At this time, since the first semiconductor regionand the first ohmic electrodetypically have a surface roughness of less than 1 nm, there is no need for a planarization process such as chemical-mechanical polishing (CMP). However, in some cases, the surface of the first semiconductor regionwith gallium polarity may be polished and smoothly planarized through CMP, and the surface of the first ohmic electrodemay also be polished and smoothly planarized through mechanical polishing (MP) or CMP, and this improvement in surface roughness may result in enhanced bonding strength and improved quality of each layer.

The light-emitting partgenerates light and can emit blue light, green light, or red light. In the present invention, when the light-emitting partemits blue light or green light, binary, ternary, and quaternary compounds such as InN, InGaN, GaN, AlGaN, AlN, and AlGaInN, which are Group III (Al, Ga, and In) nitride semiconductors among the Group III-V compound semiconductors, may be epitaxially grown on an initial growth substrate G wafer by being arranged at appropriate positions and sequence.

In particular, in order to emit blue light or green light, a high-quality InGaN Group III nitride semiconductor with a high In composition should be preferentially formed on top of Group III nitride semiconductors composed of GaN, AlGaN, AlN, and AlGaInN, but the present invention is not limited thereto.

Further, in the present invention, when the light-emitting partemits red light, binary, ternary, and quaternary compounds such as InP, InGaP, GaP, AlInP, AlGaP, AlP, and AlGaInP, which are Group III (Al, Ga, and In) phosphide semiconductors among Group III-V compound semiconductors, may be epitaxially grown on the initial growth wafer by being arranged at appropriate positions and sequence. In addition, to further improve the value of display panel products and the recent development of equipment and process technology, when emitting red light, a high-quality InGaN group III nitride semiconductor with a high In composition of 30% or more may be preferentially formed on top of Group III nitride semiconductors composed of GaN, AlGaN, AlN, and AlGaInN, in addition to group III phosphide semiconductors.