Phase Change Material in an Electronic Switch Having a Flat Profile

This present application is a continuation of U.S. patent application Ser. No. 18/340,253 filed Jun. 23, 2023, entitled “Phase Change Material In An Electronic Switch Having A Flat Profile” which claims benefit of provisional U.S. patent application 63/494,924, filed on Apr. 7, 2023, entitled “Radio Frequency Switch With Flat Phase Change Material”, the disclosure of each which is hereby incorporated by reference in their respective entireties.

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

However, as the scaling down process continues, certain challenges may arise. For example, IC components may be implemented as electronic switches to control the transmission of electrical signals. When devices had larger sizes in older technology nodes, the performance of the electronic switches was not overly sensitive to the geometric shapes of the electronic switches. However, as device sizes shrink, the shapes of the electronic switches may begin to negatively impact the performance of the electronic switches. For example, a step height in an electronic switch (e.g., due to a part of the electronic switch being formed in a bent manner) may degrade the performance and/or the lifetime of the electronic switch.

Therefore, although existing IC devices and their methods of fabrication have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

The following disclosure provides many different embodiments, or examples, for implementing unique features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

The present disclosure is generally related to an electronic switch, and more particularly, to an electronic switch that is implemented at least in part using a phase change material (PCM), where the PCM has a substantially flat profile. For example, through the performance of unique fabrication process flows according to various embodiments of the present disclosure, the resulting PCM herein may achieve a shape that includes a substantially flat upper surface and/or a substantially flat bottom surface. Such a flat profile of the PCM avoids (or at least significantly reduces) the presence of a step height that exists in conventional electronic switches. In that regard, the fabrication process flow used to form conventional electronic switches typically lead to a step height in the PCM, which may be a result of the PCM being formed in a “bent” manner. When IC device sizes were greater in older IC fabrication technology generations, such a step height was not a significant concern, as its impact on device performance and/or lifetime was minimal. However, as device sizes shrink, the existence of such a step height in the PCM may lead to a clustering of certain types of atoms (e.g., a clustering of germanium atoms) in regions of the PCM at or near the step height. When this occurs, the material composition of the PCM is effectively altered, which may adversely impact its intended functionality as a switchable component in the electronic switch. Furthermore, the lifetime of the PCM may also be shortened, and the electronic switch may experience premature failure.

To address these issues discussed above, the present disclosure utilizes unique fabrication process flows to ensure that the resulting PCM can achieve a substantially flat shape (e.g., a substantially flat top surface and a substantially flat bottom surface), which eliminates or at least reduces the step height that is found in the PCM of conventional electronic switches. Consequently, the resulting PCM may be free of the undesirable clusters that are typically found in conventional devices. Therefore, the performance and/or longevity of the electronic switches (where the PCM is implemented) may be improved.

The various aspects of the present disclosure will now be discussed below with reference to, IC and-. In more detail,illustrate an example FinFET device, andillustrates an example GAA device.illustrate cross-sectional side views of an IC device at various stages of fabrication according to embodiments of the present disclosure.illustrates a planar top view of a portion of an IC device.illustrates a semiconductor fabrication system.illustrates a flowchart of a method of fabricating an IC device according to various aspects of the present disclosure.

Referring now to, a three-dimensional perspective view and a top view of a portion of an Integrated Circuit (IC) deviceare illustrated, respectively. The IC deviceis implemented using field-effect transistors (FETs) such as three-dimensional fin-line FETs (FinFETs). FinFET devices have semiconductor fin structures that protrude vertically out of a substrate. The fin structures are active regions, from which source/drain region(s) and/or channel regions are formed. Source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context. A source/drain region may also refer to a region that provides a source and/or drain for multiple devices. The gate structures partially wrap around the fin structures. In recent years, FinFET devices have gained popularity due to their enhanced performance compared to conventional planar transistors.

As shown in, the IC deviceincludes a substrate. The substratemay comprise an elementary (single element) semiconductor, such as silicon, germanium, and/or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/or other suitable materials. The substratemay be a single-layer material having a uniform composition. Alternatively, the substratemay include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substratemay be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substratemay include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source/drain regions, may be formed in or on the substrate. The doped regions may be doped with n-type dopants, such as phosphorus or arsenic, and/or p-type dopants, such as boron, depending on design requirements. The doped regions may be formed directly on the substrate, in a p-well structure, in an n-well structure, in a dual-well structure, or using a raised structure. Doped regions may be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques.

Three-dimensional active regionsare formed on the substrate. The active regionsmay include elongated fin-like structures that protrude upwardly out of the substrate. As such, the active regionsmay be interchangeably referred to as fin structuresor finshereinafter. The fin structuresmay be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer overlying the substrate, exposing the photoresist to a pattern, performing post-exposure bake processes, and developing the photoresist to form a masking element (not shown) including the resist. The masking element is then used for etching recesses into the substrate, leaving the fin structureson the substrate. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. In some embodiments, the fin structuremay be formed by double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. As an example, a layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned layer using a self-aligned process. The layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fin structures.

The IC devicealso includes source/drain componentsformed over the fin structures. The source/drain componentsmay include epi-layers that are epitaxially grown on the fin structures. The IC devicefurther includes isolation structuresformed over the substrate. The isolation structureselectrically separate various components of the IC device. The isolation structuresmay include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable materials. In some embodiments, the isolation structuresmay include shallow trench isolation (STI) features. In one embodiment, the isolation structuresare formed by etching trenches in the substrateduring the formation of the fin structures. The trenches may then be filled with an isolating material described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structure such as field oxide, local oxidation of silicon (LOCOS), and/or other suitable structures may also be implemented as the isolation structures. Alternatively, the isolation structuresmay include a multi-layer structure, for example, having one or more thermal oxide liner layers.

The IC devicealso includes gate structuresformed over and engaging the fin structureson three sides in a channel region of each fin. In other words, the gate structureseach wrap around a plurality of fin structures. The gate structuresmay be dummy gate structures (e.g., containing an oxide gate dielectric and a polysilicon gate electrode), or they may be High-k metal gate (HKMG) structures that contain a high-k gate dielectric and a metal gate electrode, where the HKMG structures are formed by replacing the dummy gate structures. Though not depicted herein, the gate structuremay include additional material layers, such as an interfacial layer over the fin structures, a capping layer, other suitable layers, or combinations thereof.

Referring to, multiple fin structuresare each oriented lengthwise along the X-direction, and multiple gate structureare each oriented lengthwise along the Y-direction, i.e., generally perpendicular to the fin structures. In many embodiments, the IC deviceincludes additional features such as gate spacers disposed along sidewalls of the gate structures, hard mask layer(s) disposed over the gate structures, and numerous other features.

illustrates a three-dimensional perspective view of an example multi-channel gate-all-around (GAA) device. GAA devices have multiple elongated nano-structure channels that may be implemented as nano-tubes, nano-sheets, or nano-wires. For reasons of consistency and clarity, similar components inandwill be labeled the same. For example, active regions such as fin structuresrise vertically upwards out of the substratein the Z-direction. The isolation structuresprovide electrical separation between the fin structures. The gate structureis located over the fin structuresand over the isolation structures. A maskis located over the gate structure, and gate spacersare located on sidewalls of the gate structure. A capping layeris formed over the fin structuresto protect the fin structuresfrom oxidation during the forming of the isolation structures.

A plurality of nano-structuresis disposed over each of the fin structures. The nano-structuresmay include nano-sheets, nano-tubes, or nano-wires, or some other type of nano-structure that extends horizontally in the X-direction. Portions of the nano-structuresunder the gate structuremay serve as the channels of the GAA device. Dielectric inner spacersmay be disposed between the nano-structures. In addition, although not illustrated for reasons of simplicity, each stack of the nano-structuresmay be wrapped around circumferentially by a gate dielectric as well as a gate electrode. In the illustrated embodiment, the portions of the nano-structuresoutside the gate structuremay serve as the source/drain features of the GAA device. However, in some embodiments, continuous source/drain features may be epitaxially grown over portions of the fin structuresoutside of the gate structure. Regardless, conductive source/drain contactsmay be formed over the source/drain features to provide electrical connectivity thereto. An interlayer dielectric (ILD)is formed over the isolation structuresand around the gate structureand the source/drain contacts. The ILDmay be referred to as an ILDO layer. In some embodiments, the ILDmay include silicon oxide, silicon nitride, or a low-k dielectric material.

The FinFET devices ofand the GAA devices ofmay be utilized to implement electrical circuitries having various functionalities, such as memory devices (e.g., static random access memory (SRAM) devices), logic circuitries, application specific integrated circuit (ASIC) devices, radio frequency (RF) circuitries, drivers, micro-controllers, central processing units (CPUs), image sensors, etc., as non-limiting examples.

illustrate diagrammatic fragmentary cross-sectional views of a portion of an IC device(in which the FinFET or GAA devices may be implemented) at various stages of fabrication according to various embodiments of the present disclosure. In some embodiments, the portion of IC deviceillustrated may include an electronic switch implemented using a phase change material (PCM), as discussed below. Note thatillustrate the cross-sectional views along an X-Z plane defined by the X-direction horizontally and the Z-direction vertically.

As shown in, the IC deviceincludes a material layer. In some embodiments, the material layerincludes silicon carbide (SiC). The IC devicealso includes an insulating materialthat is formed over the material layer. In some embodiments, the insulating material includes silicon oxide (SiO). The IC devicefurther includes a conductive component, a conductive component, and a heater component, which are all embedded in the insulating material. The conductive componentsandare separated from one another in the X-direction by the heater component, and also by portions of the insulating material.

The conductive componentsandserve as electrical terminals (or electrodes) for the transmission of an electrical signal, for example, a radio frequency (RF) signal. In other words, the conductive componentsandmay each be connected to RF circuitry (which may be implemented using the FinFET and/or GAA devices discussed above with reference to) that are capable of generating electrical signals such as the RF signal. For reasons of simplicity, such RF circuitry is not illustrated in, as the details of the RF circuitry are not the main focus of the scope of the present disclosure. In any case, to facilitate the transmission of the electrical signals, the conductive componentsandare implemented using a low resistance material. In some embodiments, the conductive componentsandare implemented using tungsten (W).

The heater componentis configured to generate heat. Therefore, the heater componentis implemented using a material that can tolerate a high temperature. In some embodiments, the heater component is also implemented using tungsten. It is understood that the portion of the heater componentshown inmay correspond to a middle segment of the heater component, which may be connected to two opposite end segments of the heater component. The two opposite end segments of the heater componentare not visible in, but they will be illustrated in the top view figurethat is discussed below in more detail. Electrical voltages may be applied to the heater componentvia the two end segments to produce thermal energy in the form of heat. As will be discussed below in more detail, the heat produced by the heater componentmay change a phase of a PCM structure that is to be formed over the heater componentin a subsequent fabrication process. As the PCM structure undergoes a phase change, its resistivity may also change, which allows it to function as either a conductor or an insulator, depending on the phase that the PCM structure is in. As such, the PCM structure may function as an electrical switch that can be selectively opened or closed to regulate the transmission of electrical signals therethrough.

The conductive components-and the heater componentmay be formed by etching openings in the insulating material, and subsequently depositing the suitable conductive materials (e.g., tungsten) to fill these openings. It is understood that a planarization process, such as a chemical mechanical polishing (CMP) process may be performed following the deposition of the conductive materials to planarize the upper surfaces of the conductive components-and the heater component. At this stage of fabrication, the conductive components-and the heater componentmay have substantially flat and co-planar upper surfaces.

Referring now to, a patterned photoresist layer formation processis performed to the IC device. For example, a photoresist material may be spin-coated over the IC device. The photoresist material may undergo an exposure process, followed by a post exposure baking process and a developing process to remove portions of the photoresist material. The remaining portions of the photoresist material may form a patterned photoresist layer. The patterned photoresist layermay define a plurality of openings, such as openings,, and. As is shown in, the openingexposes the upper surfaces of the heater componentand portions of the insulating materialsurrounding the heater component. The openingexposes a portion of the conductive componentand a portion of the insulating materialadjacent to the conductive component. The openingexposes a portion of the conductive componentand a portion of the insulating materialadjacent to the conductive component.

Referring now to, an etching processis performed to the IC deviceto extend the openings-further downwards vertically, for example, the etching processmay include one or more wet etching processes or dry etching processes to remove portions of the heater component, the conductive components-, as well as the insulating materialthat are exposed by the openings-, while portions of the IC devicelocated under the patterned photoresist layerare protected. In this manner, the patterned photoresist layerserves as an etching mask. In some embodiments, the etching processuses an etchant gas that comprises SF, CF, CHF, or O.

As a result of the etching process, a heightof the heater componentis less than a maximum heightof the conductive componentor conductive component. In some embodiments, a ratio between the heightand the heightis in a range between about 1:1.5 and about 1:2.5. It is understood that the above range is not randomly chosen but specifically configured to optimize the performance of the IC device. For example, at least the openingwill be filled by a dielectric layer in a subsequent process, so that such a dielectric layer may provide electrical isolation between the heater componentand the PCM structure that is to be formed over the dielectric layer. If the ratio between the heightand the heightis too high, that may indicate that the openinghas not been extended deep enough, which may result in the dielectric layerfilling the openingnot being thick enough to provide a sufficient amount of electrical isolation between the heater componentand the PCM structure.

On the other hand, if the ratio between the heightand the heightis too low, that may indicate the openinghas been extended unnecessarily deep, which may mean that an excessive amount of the heater componenthas been removed. When this occurs, the heater componentmay not be able to generate a sufficient amount of heat to alter the phase of the PCM structure. In addition, the resulting dielectric layer filling the openingmay be too thick, in the sense that a substantial amount of the heat generated by the heater componentmay not be able to reach the PCM above. As such, it may be more difficult to control the temperature of the PCM via the heat generated by the heater component.

Here, the above ratio range is optimized to ensure that the subsequently-formed dielectric layer is thick enough to adequately serve as an electrical isolation structure, while also thin enough to not disrupt the intended heat generation functionality of the heater component.

Referring now to, a photoresist removal processis performed to the IC deviceto remove the patterned photoresist layer. In some embodiments, the photoresist removal processincludes a photoresist stripping process or a photoresist ashing process. The openings-that are etched into the insulating material, the conductive components-, and the heater componentstill remain after the patterned photoresist layeris removed.

Referring now to, a dielectric layer formation processis performed to the IC device. In some embodiments, the dielectric layer formation processincludes a deposition process, such as a PVD process, a CVD process, an ALD process, or combinations thereof. The deposition process deposits a dielectric material into the openings-. In some embodiments, the deposition process deposits silicon nitride (SiN) as the dielectric material deposited into the openings-. The dielectric layer formation processmay also include a planarization process, such as a CMP process, to remove excess portions of the dielectric material deposited outside of the openings-and to planarize the upper surface of the deposited dielectric material with the upper surfaces of the insulating materialand the conductive components-. As a result of the dielectric layer formation process, dielectric layers,, andare formed in the openings,, and, respectively.

Referring now to, a PCM formation processis performed to the IC deviceto form a phase change material (PCM). In some embodiments, the PCM formation processincludes a deposition process, such as a PVD process, a CVD process, an ALD process, or combinations thereof. As shown in, the PCMis formed over the upper surfaces of the dielectric layer, portions of the insulating materialsurrounding the dielectric layer, as well as portions of the conductive componentsand. Note that as an inherent result of the unique fabrication process flow being performed herein, a side surfaceof the dielectric layeris in direct physical contact with the insulating material, but not with the PCM. Rather, an upper surfaceof the dielectric layeris in direct physical contact with a portionA of a bottom surface of the PCM. Another portionB of the bottom surface of the PCMis in direct contact with an upper surfaceof the conductive component, and yet another portionC of the bottom surface of the PCMis in direct contact with an upper surfaceof the conductive component. This is because the upper surfacesand-have been planarized prior to the formation of the PCM, which results in the flat bottom surface of the PCM(but not other parts of the PCM) that is in direct contact with the conductive components-and the heater component.

In some embodiments, the PCM formation processdeposits a germanium telluride (GeTe) material as the PCM. The GeTe material can change its phase from an amorphous phase to a crystal phase, or vice versa, based on a temperature of the GeTe material. The temperature of the GeTe material (i.e., a temperature of the PCM) can change in response to the heat generated by the heater component. In that regard, although the PCMis electrically insulated from the heater componentby the dielectric layer, the heat produced by the heater component can and will affect the PCM. For example, as an electrical voltage is applied to the heater componentto cause the heater componentto generate heat, the temperature at the PCMmay begin to rise. When such a temperature reaches a crystallization temperature of the PCM(e.g., at about 200 degrees Celsius), the PCMwill change into a crystal phase, which is highly conductive (e.g., has a low resistivity). In other words, when the heat generated by the heater componentcauses the PCMto switch into the crystal phase, the high conductivity and/or low resistivity causes the PCMto effectively function as a closed electrical switch. In this state, electrical signals (e.g., RF signals) may be transmitted between the conductive components-through the PCM.

If it is desired for the PCMto continue to function as a closed electrical switch, then the heater componentmay be configured to not generate additional heat. For example, no electrical voltage may be applied to the heater component, which may cause the heater componentto cease the heat generation (at least temporarily). As a result, the temperature at the PCMmay no longer rise, and in fact may drop back down to room temperature (e.g., around 25 degrees Celsius). Since the PCMis already in the crystal state, it may remain in the crystal state under the room temperature and therefore continue to serve as a closed electrical switch.

However, if it is desired for the PCMto begin to function as an open electrical switch, then the heater componentmay be configured to generate even more heat, such that the temperature at the PCMreaches a melting point (e.g., at 500 degrees Celsius or higher). Thereafter, the PCMmay be cooled rapidly. This process will return the PCMto an amorphous state, which is associated with a low conductivity and/or high resistivity. Such a low conductivity and/or high resistivity effectively turns the PCMinto an electrically insulating material, which allows it to serve as an open electrical switch. Therefore, the PCMmay prevent the transmission of electrical signals between the conductive components-when the PCMis operating under the electrical open state.

As discussed above, since the prior fabrication processes (e.g., CMP) have already planarized the upper surfaceof the dielectric layerwith the upper surfaces-of the conductive components-, the PCMherein is formed as a substantially flat structure. For example, a bottom surface of the PCMis substantially flat (e.g., flat in its entirety). This is manifested at least in part by the fact that the portionA of the bottom surface of the PCMis substantially co-planar with the portionB of the bottom surface of the PCM. In addition, the PCMalso has a substantially flat top surface(e.g., an entirety of the top surfaceis flat). According to various aspects of the present disclosure, the substantially flat top and bottom surfaces of the PCMare unique physical characteristics of the IC device. Such a flat cross-sectional profile of the PCM eliminates (or at least substantially reduces) the step height issue that plagues conventional PCM devices. Advantageously, the flat profile (and lack of step height) reduces the clustering of germanium atoms, which will lead to an improved device performance and a longer lifetime.

Referring now to, a capping layer formation processis performed to the IC deviceto form a capping layer. In some embodiments, the capping layer formation processincludes a deposition process, such as a PVD process, a CVD process, an ALD process, or combinations thereof. The deposition process deposits a dielectric material, such as silicon nitride, as the capping layerover the upper surfaces of the PCM, the dielectric layers-, and the conductive components-. A bottom surface of a portion of the capping layeris in direct physical contact with the upper surface of the PCMand forms an interfacewith the upper surface of the PCM. Since the upper surface of the PCMis substantially flat, this interfacebetween the capping layerand the PCMis also substantially flat. The capping layermay protect the PCMfrom various elements. For example, since the capping layerseals the PCMunderneath, the PCMwill not be exposed to oxygen, and as such, will not become oxidized. Since oxidation would have adversely affected the performance of the PCMas an electronic switch, the capping layerhelps to protect the PCMfrom undesirable oxidation, and therefore, improves device performance.

It is understood thatillustrate the cross-sectional side views corresponding to a first embodiment of the fabrication process flow of the present disclosure.illustrate the cross-sectional side views corresponding to a second embodiment of the fabrication process flow of the present disclosure. For reasons of consistency and clarity, similar components and/or processes in the first embodiment and the second embodiment are labeled the same.

Referring now to, the IC deviceis provided that includes the material layer, the insulating material, the conductive components-, and the heater component. The patterned photoresist layer formation processis also performed to the IC deviceto form a patterned photoresist layer. However, unlike the patterned photoresist layerin, the patterned photoresist layerindoes not define the openings-. Instead, the patterned photoresist layerdefines just the openingthat exposes the upper surfaces of the heater componentand portions of the insulating materialsurrounding the heater component, while the conductive components-are covered up by the patterned photoresist layer.

Referring now to, the etching processis performed to the IC deviceto extend the openingfurther downwards. For example, the etching processmay include one or more wet etching processes or dry etching processes to remove portions of the heater componentand the insulating materialthat are exposed by the opening, while portions of the IC devicelocated under the patterned photoresist layerare protected. In this manner, the patterned photoresist layerserves as an etching mask. As was the case in the first embodiment, the etching processresults in a lower heightof the heater componentthan the heightof the conductive components-.

Referring now to, the photoresist removal processis performed to the IC deviceto remove the patterned photoresist layer. In some embodiments, the photoresist removal processincludes a photoresist stripping process or a photoresist ashing process. The openingthat is etched into the insulating materialand the heater componentstill remains after the patterned photoresist layeris removed.

Referring now to, the dielectric layer formation processis performed to the IC deviceto deposit a dielectric material (e.g., SiN) into the opening. A planarization process, such as a CMP process, may also be performed to remove excess portions of the dielectric material deposited outside of the openingand to planarize the upper surface of the deposited dielectric material with the upper surfaces of the insulating materialand the conductive components-. As a result of the dielectric layer formation process, the dielectric layeris formed in the opening.

Referring now to, the PCM formation processis performed to the IC deviceto form the PCM. The PCMis formed over the upper surfaces of the dielectric layer, portions of the insulating materialsurrounding the dielectric layer, as well as portions of the conductive componentsand. The operation of the PCM(e.g., by changing its phase in response to the heat generated by the heater component) is substantially similar to that discussed above in the first embodiment.

Similar to the first embodiment, the PCMin the second embodiment (shown inherein) also has a flat upper surfaceand a flat bottom surface. For example, the portionA of the bottom surface of the PCMis in direct physical contact with the upper surfaceof the dielectric layer, and the portionsB-C of the bottom surface of the PCMare in direct contact with the upper surfaces-of the conductive components-, respectively. Such a flat cross-sectional profile of the PCMeliminates (or at least substantially reduces) the step height issue that plagues conventional PCM devices, and consequently will lead to an improved device performance and a longer lifetime (e.g., since the reduction in the step height also reduces the clustering of germanium atoms). Note that another inherent result of the flat profile of the PCMis that the side surfaceof the dielectric layeris in direct physical contact with the insulating material, rather than being in direct physical contact with the PCM.

Referring now to, the capping layer formation processis performed to the IC deviceto form the capping layerover the upper surfaces of the PCMand the conductive components-. As is the case in the first embodiment, the bottom surface of the capping layerin the second embodiment also forms a flat interfacewith the upper surface of the PCM. As discussed above, the capping layerhelps to protect the PCMfrom elements such as undesirable oxidation.

illustrate the cross-sectional side views corresponding to a third embodiment of the fabrication process flow of the present disclosure. For reasons of consistency and clarity, similar components and/or processes in the first embodiment, the second embodiment, and the third embodiment are labeled the same.

Referring now to, the IC deviceis provided that includes the material layer, the insulating material, the conductive components-, and the heater component. The patterned photoresist layer formation processis also performed to the IC deviceto form a patterned photoresist layer. As is the case for the second embodiment, the patterned photoresist layerin the third embodiment is formed to define just the openingthat exposes the upper surfaces of the heater componentand portions of the insulating materialsurrounding the heater component, while the conductive components-are covered up by the patterned photoresist layer.

Referring now to, the etching processis performed to the IC deviceto extend the openingfurther downwards. Similar to the second embodiment, the etching processherein remove portions of the heater componentand the insulating materialthat are exposed by the opening, while portions of the IC devicelocated under the patterned photoresist layerare protected. However, compared to the etching processof the first or the second embodiments discussed above, the etching processin the third embodiment shown inis configured with a greater etching selectivity between the insulating materialand the heater component. For example, the etching processmay be configured to etch away the insulating materialat a greater rate than the heater component. As a result, a heightof the portion of the insulating materialexposed by the openingis less than the heightof the heater component, which itself is less than the heightof the conductive components-. Alternatively stated, the upper surface of the heater componentis more elevated vertically than an upper surface of the remaining portion of the insulating materialexposed by the opening.

Referring now to, the photoresist removal processis performed to the IC deviceto remove the patterned photoresist layer. In some embodiments, the photoresist removal processincludes a photoresist stripping process or a photoresist ashing process. The openingthat is etched into the insulating materialand the heater componentstill remains after the patterned photoresist layeris removed.

Referring now to, the dielectric layer formation processis performed to the IC deviceto deposit a dielectric material (e.g., SiN) into the opening. A planarization process, such as a CMP process, may also be performed to remove excess portions of the dielectric material deposited outside of the openingand to planarize the upper surface of the deposited dielectric material with the upper surfaces of the insulating materialand the conductive components-. As a result of the dielectric layer formation process, the dielectric layeris formed in the opening. Note that due to the greater heightof the heater component(e.g., compared to the heightof the insulating material), the heater componentprotrudes vertically into the dielectric layer.